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Zeldax64Zeldax64
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Use better define names to control project
1 parent 8e26308 commit 34a3692

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13 files changed

+66
-68
lines changed

13 files changed

+66
-68
lines changed

‎rtl/arvi_defines.svh‎

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,24 +2,22 @@
22
`define __ARVI_DEFINES
33

44
`define INSTRUCTION_SIZE 31
5-
`define WORD_SIZE 31
65
`define XLEN 32
7-
// Start address
6+
// Start address.
87
`define PC_RESET 32'h80000000
98

10-
`define PROGRAM_DATA "./test/asm/addi.bin"
11-
9+
// Select number of cores.
1210
`define __SINGLE_CORE
1311
//`define __DUAL_CORE
1412

1513
`ifdef __DUAL_CORE
16-
`define __ATOMIC
14+
`define __RVA
1715
`endif
1816

19-
// Remove comments to enable extensions RV32A or RV32M extensions.
20-
//`define __ATOMIC
21-
//`define __RV32_M
22-
//`define __RV32_M_EXTERNAL
17+
// Remove comments to enable extensions.
18+
//`define __RVA
19+
//`define __RVM
20+
//`define __RVM_EXTERNAL
2321

2422
`include "arvi_interfaces.svh"
2523

‎rtl/arvi_interfaces.svh‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -17,23 +17,23 @@ interface bus_if;
1717
logic [31:0] addr;
1818
logic [3:0] byte_en;
1919

20-
`ifdef __ATOMIC
20+
`ifdef __RVA
2121
logic [6:0] operation;
2222
logic atomic;
2323
`endif
2424

2525
modport master(
2626
input ack, rd_data,
2727
output bus_en, wr_en, wr_data, addr, byte_en
28-
`ifdef __ATOMIC
28+
`ifdef __RVA
2929
, operation, atomic
3030
`endif
3131
);
3232

3333
modport slave(
3434
output ack, rd_data,
3535
input bus_en, wr_en, wr_data, addr, byte_en
36-
`ifdef __ATOMIC
36+
`ifdef __RVA
3737
, operation, atomic
3838
`endif
3939
);
@@ -48,7 +48,7 @@ endinterface
4848
output [31:0] o_wr_data, \
4949
output [31:0] o_addr, \
5050
output [3:0] o_byte_en \
51-
`ifdef __ATOMIC \
51+
`ifdef __RVA \
5252
, \
5353
output [6:0] o_operation, \
5454
output o_atomic \
@@ -72,22 +72,22 @@ interface dmem_if;
7272
logic [3:0] DM_byte_en;
7373
logic DM_Wen;
7474
logic DM_MemRead;
75-
`ifdef __ATOMIC
75+
`ifdef __RVA
7676
logic DM_atomic;
7777
logic [6:0] DM_operation;
7878
`endif
7979

8080
modport master(
8181
input DM_data_ready, DM_ReadData,
82-
`ifdef __ATOMIC
82+
`ifdef __RVA
8383
output DM_atomic, DM_operation,
8484
`endif
8585
output DM_Wd, DM_Addr, DM_byte_en, DM_Wen, DM_MemRead
8686
);
8787

8888
modport slave(
8989
input DM_Wd, DM_Addr, DM_byte_en, DM_Wen, DM_MemRead,
90-
`ifdef __ATOMIC
90+
`ifdef __RVA
9191
input DM_atomic, DM_operation,
9292
`endif
9393
output DM_data_ready, DM_ReadData

‎rtl/bus/arbiter_2x1.sv‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ module arbiter_2x1(
1818
output logic [31:0] o_addr,
1919
output logic [3:0] o_byte_en,
2020
output logic o_id,
21-
`ifdef __ATOMIC
21+
`ifdef __RVA
2222
output logic o_atomic,
2323
output logic [6:0] o_operation,
2424
`endif
@@ -34,7 +34,7 @@ module arbiter_2x1(
3434
logic ack1, ack2;
3535
logic [31:0] rd_data1, rd_data2;
3636
logic id;
37-
`ifdef __ATOMIC
37+
`ifdef __RVA
3838
logic atomic;
3939
logic [6:0] operation;
4040
`endif
@@ -71,7 +71,7 @@ module arbiter_2x1(
7171
o_rd_data1 = rd_data1;
7272
o_ack2 = ack2;
7373
o_rd_data2 = rd_data2;
74-
`ifdef __ATOMIC
74+
`ifdef __RVA
7575
o_atomic = atomic;
7676
o_operation = operation;
7777
`endif
@@ -104,7 +104,7 @@ module arbiter_2x1(
104104
wr_data = 0;
105105
addr = 0;
106106
byte_en = 0;
107-
`ifdef __ATOMIC
107+
`ifdef __RVA
108108
atomic = 0;
109109
operation = 0;
110110
`endif
@@ -122,7 +122,7 @@ module arbiter_2x1(
122122
byte_en = i_byte_en1;
123123
ack1 = i_ack;
124124
rd_data1 = i_rd_data;
125-
`ifdef __ATOMIC
125+
`ifdef __RVA
126126
atomic = i_atomic1;
127127
operation = i_operation1;
128128
`endif
@@ -136,7 +136,7 @@ module arbiter_2x1(
136136
byte_en = i_byte_en2;
137137
ack2 = i_ack;
138138
rd_data2 = i_rd_data;
139-
`ifdef __ATOMIC
139+
`ifdef __RVA
140140
atomic = i_atomic2;
141141
operation = i_operation2;
142142
`endif
@@ -149,7 +149,7 @@ module arbiter_2x1(
149149
logic [31:0] i_wr_data1;
150150
logic [31:0] i_addr1;
151151
logic [3:0] i_byte_en1;
152-
`ifdef __ATOMIC
152+
`ifdef __RVA
153153
logic i_atomic1;
154154
logic [6:0] i_operation1;
155155
`endif
@@ -161,7 +161,7 @@ module arbiter_2x1(
161161
assign i_wr_data1 = bus0.wr_data;
162162
assign i_addr1 = bus0.addr;
163163
assign i_byte_en1 = bus0.byte_en;
164-
`ifdef __ATOMIC
164+
`ifdef __RVA
165165
assign i_atomic1 = bus0.atomic;
166166
assign i_operation1 = bus0.operation;
167167
`endif
@@ -174,7 +174,7 @@ module arbiter_2x1(
174174
logic [31:0] i_wr_data2;
175175
logic [31:0] i_addr2;
176176
logic [3:0] i_byte_en2;
177-
`ifdef __ATOMIC
177+
`ifdef __RVA
178178
logic i_atomic2;
179179
logic [6:0] i_operation2;
180180
`endif
@@ -186,7 +186,7 @@ module arbiter_2x1(
186186
assign i_wr_data2 = bus1.wr_data;
187187
assign i_addr2 = bus1.addr;
188188
assign i_byte_en2 = bus1.byte_en;
189-
`ifdef __ATOMIC
189+
`ifdef __RVA
190190
assign i_atomic2 = bus1.atomic;
191191
assign i_operation2 = bus1.operation;
192192
`endif

‎rtl/bus/bus.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ module bus (
4747
bus_m.addr <= addr;
4848
bus_m.byte_en <= dmem.DM_byte_en;
4949
bus_m.bus_en <= bus_req;
50-
`ifdef __ATOMIC
50+
`ifdef __RVA
5151
bus_m.atomic <= dmem.DM_atomic;
5252
bus_m.operation <= dmem.DM_operation;
5353
`endif

‎rtl/modules/d_mem/d_mem.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ module d_mem(
1616
input [2:0] i_f3,
1717
input i_wr_en,
1818
input i_rd_en,
19-
`ifdef __ATOMIC
19+
`ifdef __RVA
2020
input i_atomic,
2121
input [6:0] i_operation,
2222
`endif
@@ -45,7 +45,7 @@ module d_mem(
4545
assign to_mem.DM_byte_en = o_DM_byte_en;
4646
assign to_mem.DM_Wen = o_DM_Wen;
4747
assign to_mem.DM_MemRead = o_DM_MemRead;
48-
`ifdef __ATOMIC
48+
`ifdef __RVA
4949
assign to_mem.DM_atomic = i_atomic;
5050
assign to_mem.DM_operation = i_operation;
5151
`endif

‎rtl/modules/datapath/datapath_sc.sv‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ module datapath_sc
2323
dmem_if.master DM_to_mem,
2424

2525
// External RV32-M implementation
26-
`ifdef __RV32_M_EXTERNAL
26+
`ifdef __RVM_EXTERNAL
2727
output o_EX_en,
2828
output [`XLEN-1:0] o_EX_rs1,
2929
output [`XLEN-1:0] o_EX_rs2,
@@ -96,10 +96,10 @@ module datapath_sc
9696
logic id_MC_PCplus4;
9797
logic id_MC_CSR_en;
9898
logic id_MC_Ex_inst_illegal;
99-
`ifdef __RV32_M
99+
`ifdef __RVM
100100
logic id_MC_ALUM_en;
101101
`endif
102-
`ifdef __ATOMIC
102+
`ifdef __RVA
103103
logic id_MC_atomic;
104104
`endif
105105

@@ -120,7 +120,7 @@ module datapath_sc
120120
logic ex_MC_PCplus4;
121121
logic ex_MC_CSR_en;
122122
logic ex_MC_Ex_inst_illegal;
123-
`ifdef __ATOMIC
123+
`ifdef __RVA
124124
logic ex_MC_atomic;
125125
`endif
126126

@@ -219,10 +219,10 @@ module datapath_sc
219219
.o_pc_plus4 (id_MC_PCplus4),
220220
.o_csr_en (id_MC_CSR_en),
221221
.o_ex_inst_illegal (id_MC_Ex_inst_illegal),
222-
`ifdef __ATOMIC
222+
`ifdef __RVA
223223
.o_atomic (id_MC_atomic),
224224
`endif
225-
`ifdef __RV32_M
225+
`ifdef __RVM
226226
.o_m_en (id_MC_ALUM_en),
227227
`endif
228228
.o_inst (id_inst),
@@ -250,12 +250,12 @@ module datapath_sc
250250

251251
.i_pc (id_pc),
252252

253-
`ifdef __RV32_M
253+
`ifdef __RVM
254254
.i_clk (i_clk),
255255
.i_rst (i_rst),
256256
`endif
257257

258-
`ifdef __RV32_M_EXTERNAL
258+
`ifdef __RVM_EXTERNAL
259259
.i_res (i_EX_res),
260260
.i_ack (i_EX_ack),
261261
.o_en (o_EX_en),
@@ -279,10 +279,10 @@ module datapath_sc
279279
.i_csr_en (id_MC_CSR_en),
280280
.i_ex_inst_illegal (id_MC_Ex_inst_illegal),
281281

282-
`ifdef __ATOMIC
282+
`ifdef __RVA
283283
.i_atomic (id_MC_atomic),
284284
`endif
285-
`ifdef __RV32_M
285+
`ifdef __RVM
286286
.i_m_en (id_MC_ALUM_en),
287287
`endif
288288

@@ -297,7 +297,7 @@ module datapath_sc
297297
.o_csr_en (ex_MC_CSR_en),
298298
.o_ex_inst_illegal (ex_MC_Ex_inst_illegal),
299299

300-
`ifdef __ATOMIC
300+
`ifdef __RVA
301301
.o_atomic (ex_MC_atomic),
302302
`endif
303303
//----- Forward signals -----//
@@ -354,7 +354,7 @@ module datapath_sc
354354
.i_mc_regwrite (ex_MC_RegWrite),
355355
.i_mc_pcplus4 (ex_MC_PCplus4),
356356
.i_mc_ex_inst_illegal (ex_MC_Ex_inst_illegal),
357-
`ifdef __ATOMIC
357+
`ifdef __RVA
358358
.i_mc_atomic (ex_MC_atomic),
359359
`endif
360360
// Control signals to next stage

‎rtl/modules/main_control/main_control.sv‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
`define OP_SYSTEM_TYPE 7'b1110011
1717
`define OP_FENCE 7'b0001111
1818

19-
`ifdef __ATOMIC
19+
`ifdef __RVA
2020
// RV-A
2121
`define OP_ATOMIC 7'b0101111
2222
`endif
@@ -40,10 +40,10 @@ module main_control (
4040
output logic o_CSR_en,
4141
output logic o_Ex_inst_illegal,
4242

43-
`ifdef __ATOMIC
43+
`ifdef __RVA
4444
output logic o_atomic,
4545
`endif
46-
`ifdef __RV32_M
46+
`ifdef __RVM
4747
output logic o_ALUM_en,
4848
`endif
4949

@@ -73,10 +73,10 @@ module main_control (
7373
o_CSR_en = 0;
7474
o_Ex_inst_illegal = 0; // Illegal instruction signal
7575

76-
`ifdef __ATOMIC
76+
`ifdef __RVA
7777
o_atomic = 0; // RV-A
7878
`endif
79-
`ifdef __RV32_M
79+
`ifdef __RVM
8080
o_ALUM_en = 0; // RV-M signal
8181
`endif
8282

@@ -87,7 +87,7 @@ module main_control (
8787
`OP_R_TYPE : begin
8888
o_RegWrite = 1;
8989
o_ALUOp = 3'b010;
90-
`ifdef __RV32_M
90+
`ifdef __RVM
9191
if(f7[0]) begin
9292
//o_ALUOp = 3'b000; // Don't care
9393
o_ALUM_en = 1;
@@ -162,7 +162,7 @@ module main_control (
162162
o_CSR_en = 1;
163163
end
164164

165-
`ifdef __ATOMIC
165+
`ifdef __RVA
166166
`OP_ATOMIC : begin
167167
o_ALUSrcA = 2'b0;
168168
o_ALUSrcB = 1'b0;

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