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Adhil-IgnMuhammedZamroodh
Adhil-Ign
authored and
MuhammedZamroodh
committed
Release: v3.0
Highlights: - Context switching and thread creation - Timer driver and system timer integartion - UART driver and LOG integration - Fixes for linking and toolchain support - Power management (idle state) - Interrupt support in OS - Twister and flash support - General fixes Signed-off-by: Muhammed Zamroodh <[email protected]>
1 parent fd7bde7 commit 0c5f7e8

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59 files changed

+1376
-796
lines changed

‎arch/Kconfig‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -175,7 +175,6 @@ config DSPIC
175175
bool
176176
select ARCH_IS_SET
177177
select STACK_GROWS_UP
178-
select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
179178
select LITTLE_ENDIAN
180179
select ARCH_HAS_THREAD_LOCAL_STORAGE
181180
select TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE
@@ -185,9 +184,6 @@ config DSPIC
185184
select ATOMIC_OPERATIONS_C
186185
select ARCH_HAS_VECTOR_TABLE_RELOCATION
187186
select CPU_HAS_ICACHE
188-
select ARCH_HAS_CUSTOM_CPU_IDLE
189-
select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
190-
select DYNAMIC_INTERRUPTS
191187
select CACHE_MANAGEMENT
192188
select TICKLESS_CAPABLE
193189
help

‎arch/dspic/Kconfig‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,16 @@ config ARCH
88
string
99
default "dspic"
1010

11+
config GEN_ISR_TABLES
12+
default y
13+
14+
config DYNAMIC_INTERRUPTS
15+
default n
16+
1117
config NUM_IRQS
12-
default 287
18+
default 279
1319

1420
config GEN_IRQ_START_VECTOR
15-
default 8
21+
default 0
1622

1723
endmenu

‎arch/dspic/core/CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,4 +15,4 @@ zephyr_library_sources(
1515
reset1.S
1616
)
1717

18-
zephyr_linker_sources(ROM_START SORT_KEY 0x04 vector_table.ld)
18+
zephyr_linker_sources(ROM_START SORT_KEY 0x00 vector_table.ld)

‎arch/dspic/core/cpu_idle.c‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,17 +6,24 @@
66
#include <zephyr/irq.h>
77
#include <zephyr/tracing/tracing.h>
88
#include <zephyr/arch/cpu.h>
9+
#include <xc.h>
910

1011
#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
1112
void arch_cpu_idle(void)
1213
{
14+
__builtin_disable_interrupts();
15+
Idle();
16+
__builtin_enable_interrupts();
1317
}
1418
#endif
1519

1620
#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
1721
void arch_cpu_atomic_idle(unsigned int key)
1822
{
19-
(void)key;
23+
__builtin_disable_interrupts();
24+
Idle();
25+
arch_irq_unlock(key);
26+
__builtin_enable_interrupts();
2027
}
2128
#endif
2229

‎arch/dspic/core/fatal.c‎

Lines changed: 67 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,23 @@
44
*/
55

66
#include <zephyr/kernel.h>
7+
#include <zephyr/logging/log.h>
8+
9+
#ifndef _ASMLANGUAGE
10+
#include <xc.h>
11+
#ifdef __cplusplus
12+
extern "C" {
13+
#endif
14+
15+
LOG_MODULE_REGISTER(dspic, 4);
716

817
volatile uint32_t reason, address;
918

10-
#define EXCEPTION_HANDLER __attribute__((interrupt, no_auto_psv, keep))
19+
#define EXCEPTION_HANDLER __attribute__((interrupt, no_auto_psv, weak))
20+
#define BUS_ERROR_MASK 0xF
21+
#define MATH_ERROR_MASK 0x1F
22+
#define GENERAL_TRAP_MASK 0x8000000Fu
1123

12-
void EXCEPTION_HANDLER _ReservedTrap7(void);
1324
void __attribute__((weak)) TRAPS_halt_on_error(void);
1425
void EXCEPTION_HANDLER _BusErrorTrap(void);
1526
void EXCEPTION_HANDLER _AddressErrorTrap(void);
@@ -20,62 +31,93 @@ void EXCEPTION_HANDLER _GeneralTrap(void);
2031
void EXCEPTION_HANDLER _ReservedTrap0(void);
2132
void EXCEPTION_HANDLER _ReservedTrap7(void);
2233

34+
void EXCEPTION_HANDLER _ReservedTrap0(void)
35+
{
36+
}
37+
void EXCEPTION_HANDLER _ReservedTrap7(void)
38+
{
39+
}
40+
2341
void __attribute__((weak)) TRAPS_halt_on_error(void)
2442
{
43+
/* stay here forever */
44+
while (1) {
45+
}
2546
}
2647

2748
/** Bus error.**/
2849
void EXCEPTION_HANDLER _BusErrorTrap(void)
2950
{
30-
__asm__("nop");
31-
__asm__("retfie");
51+
/* Identify bus error via INTCON3, fetch trap address from
52+
* PCTRAP, and reset error flags
53+
*/
54+
reason = INTCON3 & BUS_ERROR_MASK;
55+
address = PCTRAP;
56+
LOG_ERR("ERROR !!! Exception reason = %d, address = 0x%x\n", reason, address);
57+
INTCON3 &= ~(BUS_ERROR_MASK);
58+
PCTRAP = 0;
59+
TRAPS_halt_on_error();
3260
}
3361

3462
/** Address error.**/
3563
void EXCEPTION_HANDLER _AddressErrorTrap(void)
3664
{
37-
__asm__("nop");
38-
__asm__("retfie");
65+
/* fetch trap address from PCTRAP
66+
* and reset error flags
67+
*/
68+
address = PCTRAP;
69+
LOG_ERR("ERROR !!! Exception reason = %s, address = 0x%x\n", "Address Error", address);
70+
INTCON1bits.ADDRERR = 0;
71+
PCTRAP = 0;
72+
TRAPS_halt_on_error();
3973
}
4074

4175
/** Illegal instruction.**/
4276
void EXCEPTION_HANDLER _IllegalInstructionTrap(void)
4377
{
44-
__asm__("nop");
45-
__asm__("retfie");
78+
address = PCTRAP;
79+
LOG_ERR("ERROR !!! Exception reason = %s, address = 0x%x\n", "Illegal Instruction",
80+
address);
81+
INTCON1bits.BADOPERR = 0;
82+
PCTRAP = 0;
83+
TRAPS_halt_on_error();
4684
}
4785

4886
/** Math error.**/
4987
void EXCEPTION_HANDLER _MathErrorTrap(void)
5088
{
51-
__asm__("nop");
52-
__asm__("retfie");
89+
/* Identify math error via INTCON4, fetch trap address from
90+
* PCTRAP, and reset error flags
91+
*/
92+
reason = INTCON4 & MATH_ERROR_MASK;
93+
address = PCTRAP;
94+
LOG_ERR("ERROR !!! Exception reason = %d, address = 0x%x\n", reason, address);
95+
INTCON4 &= ~(MATH_ERROR_MASK);
96+
PCTRAP = 0;
97+
TRAPS_halt_on_error();
5398
}
5499

55100
/** Stack error.**/
56101
void EXCEPTION_HANDLER _StackErrorTrap(void)
57102
{
58-
__asm__("nop");
59-
__asm__("retfie");
103+
INTCON1bits.STKERR = 0;
104+
PCTRAP = 0;
105+
TRAPS_halt_on_error();
60106
}
61107

62108
/** Generic error.**/
63109
void EXCEPTION_HANDLER _GeneralTrap(void)
64110
{
65-
__asm__("nop");
66-
__asm__("retfie");
111+
reason = INTCON5 & GENERAL_TRAP_MASK;
112+
address = PCTRAP;
113+
LOG_ERR("ERROR !!! Exception reason = %d, address = 0x%x\n", reason, address);
114+
INTCON5 &= ~(GENERAL_TRAP_MASK);
115+
PCTRAP = 0;
116+
TRAPS_halt_on_error();
67117
}
68118

69-
/** Reserved Trap0.**/
70-
void EXCEPTION_HANDLER _ReservedTrap0(void)
71-
{
72-
__asm__("nop");
73-
__asm__("retfie");
119+
#ifdef __cplusplus
74120
}
121+
#endif
75122

76-
/** Reserved Trap7.**/
77-
void EXCEPTION_HANDLER _ReservedTrap7(void)
78-
{
79-
__asm__("nop");
80-
__asm__("retfie");
81-
}
123+
#endif /* _ASMLANGUAGE */

‎arch/dspic/core/irq_manage.c‎

Lines changed: 44 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6,23 +6,62 @@
66
#include <zephyr/kernel.h>
77
#include <kswap.h>
88

9+
#ifndef _ASMLANGUAGE
10+
#include <xc.h>
11+
12+
#ifdef __cplusplus
13+
extern "C" {
14+
#endif
15+
916
void z_irq_spurious(const void *unused)
1017
{
11-
(void)unused;
18+
ARG_UNUSED(unused);
19+
while (1) {
20+
}
21+
return;
1222
}
1323

1424
void arch_irq_enable(unsigned int irq)
1525
{
16-
(void)irq;
26+
volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
27+
&IEC5, &IEC6, &IEC7, &IEC8};
28+
29+
unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
30+
unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
31+
32+
/* Enable the interrupt by setting it's bit in interrupt enable register*/
33+
*int_enable_reg[reg_index] |= (uint32_t)(1u << bit_pos);
34+
35+
return;
1736
}
1837

1938
int arch_irq_is_enabled(unsigned int irq)
2039
{
21-
(void)irq;
22-
return 0;
40+
volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
41+
&IEC5, &IEC6, &IEC7, &IEC8};
42+
43+
unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
44+
unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
45+
46+
return ((*int_enable_reg[reg_index] >> bit_pos) & 0x1u);
2347
}
2448

2549
void arch_irq_disable(unsigned int irq)
2650
{
27-
(void)irq;
51+
volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
52+
&IEC5, &IEC6, &IEC7, &IEC8};
53+
54+
unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
55+
unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
56+
57+
/* Disable the interrupt by clearing it's bit in interrupt enable register*/
58+
*int_enable_reg[reg_index] &= (uint32_t)(~(1u << bit_pos));
59+
60+
return;
2861
}
62+
63+
#ifdef __cplusplus
64+
}
65+
#endif
66+
67+
#endif /* _ASMLANGUAGE */

‎arch/dspic/core/isr_wrapper.c‎

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,17 +6,43 @@
66
#include <zephyr/kernel.h>
77
#include <zephyr/irq.h>
88
#include <zephyr/pm/pm.h>
9-
#include <zephyr/sw_isr_table.h>
109
#include <kernel_arch_func.h>
10+
#include <kernel_arch_swap.h>
1111

1212
/* dsPIC33A interrtup exit routine. Will check if a context
1313
* switch is required. If so, z_dspic_do_swap() will be called
1414
* to affect the context switch
1515
*/
16-
void __attribute__((naked)) z_dspic_exc_exit(void)
16+
static inline __attribute__((always_inline)) void z_dspic_exc_exit(void)
1717
{
18+
#ifdef CONFIG_PREEMPT_ENABLED
19+
if ((_current_cpu->nested == 0) && (_kernel.ready_q.cache != _current) &&
20+
!k_is_pre_kernel()) {
21+
z_dspic_do_swap();
22+
}
23+
24+
#endif /* CONFIG_PREEMPT_ENABLED */
25+
#ifdef CONFIG_STACK_SENTINEL
26+
z_check_stack_sentinel();
27+
#endif /* CONFIG_STACK_SENTINEL */
28+
return;
1829
}
1930

20-
void __attribute__((interrupt, naked)) _COMMONInterrupt(void)
31+
void __attribute__((interrupt)) _isr_wrapper(void)
2132
{
33+
#ifdef CONFIG_TRACING_ISR
34+
sys_trace_isr_enter();
35+
#endif /* CONFIG_TRACING_ISR */
36+
37+
_current_cpu->nested++;
38+
int32_t irq_number = INTTREGbits.VECNUM - 9;
39+
const struct _isr_table_entry *entry = &_sw_isr_table[irq_number];
40+
(entry->isr)(entry->arg);
41+
_current_cpu->nested--;
42+
43+
#ifdef CONFIG_TRACING_ISR
44+
sys_trace_isr_exit();
45+
#endif /* CONFIG_TRACING_ISR */
46+
47+
z_dspic_exc_exit();
2248
}

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