drivers: pinctrl: nxp: drop soc name from siul2 driver

manuargue · henrikbrixandersen · commit 0f0cad00d492 · 2025-09-17T10:07:31.000+02:00
The SIUL2 pin control driver is a native implementation usable across
all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.

Signed-off-by: Manuel Argüelles &lt;manuel.arguelles@nxp.com&gt;
diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt
@@ -36,7 +36,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_INFINEON_CAT1 pinctrl_ifx_cat1.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQ pinctrl_xlnx_zynq.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQMP pinctrl_xlnx_zynqmp.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XMC4XXX pinctrl_xmc4xxx.c)
-zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_S32 pinctrl_nxp_s32.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_SIUL2 pinctrl_nxp_siul2.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_GECKO pinctrl_gecko.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SILABS_SIWX91X pinctrl_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SILABS_DBUS pinctrl_silabs_dbus.c)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
@@ -68,7 +68,7 @@ source "drivers/pinctrl/Kconfig.rv32m1"
 source "drivers/pinctrl/Kconfig.ifx_cat1"
 source "drivers/pinctrl/Kconfig.xlnx"
 source "drivers/pinctrl/Kconfig.xmc4xxx"
-source "drivers/pinctrl/Kconfig.nxp_s32"
+source "drivers/pinctrl/Kconfig.nxp_siul2"
 source "drivers/pinctrl/Kconfig.gecko"
 source "drivers/pinctrl/Kconfig.silabs_dbus"
 source "drivers/pinctrl/Kconfig.siwx91x"
diff --git a/drivers/pinctrl/Kconfig.nxp_s32 b/drivers/pinctrl/Kconfig.nxp_s32
diff --git a/drivers/pinctrl/Kconfig.nxp_siul2 b/drivers/pinctrl/Kconfig.nxp_siul2
@@ -0,0 +1,9 @@
+# Copyright 2022-2023, 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_NXP_SIUL2
+	bool "Pin controller driver for NXP SIUL2"
+	default y
+	depends on DT_HAS_NXP_S32ZE_SIUL2_PINCTRL_ENABLED || DT_HAS_NXP_S32K3_SIUL2_PINCTRL_ENABLED
+	help
+	  Enable pin controller driver for NXP SIUL2.
diff --git a/drivers/pinctrl/pinctrl_nxp_siul2.c b/drivers/pinctrl/pinctrl_nxp_siul2.c
diff --git a/dts/arm/nxp/nxp_s32k344_m7.dtsi b/dts/arm/nxp/nxp_s32k344_m7.dtsi
@@ -35,7 +35,7 @@
 
 	/* Dummy pinctrl node, filled with pin mux options at board level */
 	pinctrl: pinctrl {
-		compatible = "nxp,s32k3-pinctrl";
+		compatible = "nxp,s32k3-siul2-pinctrl";
 		status = "okay";
 	};
 
diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
@@ -75,7 +75,7 @@
 
 	/* Dummy pinctrl node, filled with pin mux options at board level */
 	pinctrl: pinctrl {
-		compatible = "nxp,s32ze-pinctrl";
+		compatible = "nxp,s32ze-siul2-pinctrl";
 		status = "okay";
 	};
 
diff --git a/dts/bindings/pinctrl/nxp,s32k3-siul2-pinctrl.yaml b/dts/bindings/pinctrl/nxp,s32k3-siul2-pinctrl.yaml
@@ -1,10 +1,10 @@
-# Copyright 2023 NXP
+# Copyright 2023, 2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  NXP S32 Pin Controller for S32K3 SoCs
+  NXP SIUL2 Pin Controller for S32K3 SoCs
 
-  The NXP S32 pin controller is a singleton node responsible for controlling
+  The NXP SIUL2 pin controller is a singleton node responsible for controlling
   the pin function selection and pin properties. This node, labeled 'pinctrl' in
   the SoC's devicetree, will define pin configurations in pin groups. Each group
   within the pin configuration defines the pin configuration for a peripheral,
@@ -65,14 +65,14 @@ description: |
     - Pad Keeping (disabled)
     - Input Filter (disabled).
 
-compatible: "nxp,s32k3-pinctrl"
+compatible: "nxp,s32k3-siul2-pinctrl"
 
 include: base.yaml
 
 child-binding:
-  description: NXP S32 pin controller pin group.
+  description: NXP SIUL2 pin controller pin group.
   child-binding:
-    description: NXP S32 pin controller pin configuration node.
+    description: NXP SIUL2 pin controller pin configuration node.
 
     include:
       - name: pincfg-node.yaml
@@ -89,8 +89,8 @@ child-binding:
         type: array
         description: |
           An array of pins sharing the same group properties. The pins must be
-          defined using the S32_PINMUX macros that encodes all the pin muxing
-          information in a 32-bit value.
+          defined using the macros from the SoC package header. These macros
+          encode all the pin muxing information in a 32-bit value.
 
       slew-rate:
         type: string
diff --git a/dts/bindings/pinctrl/nxp,s32ze-siul2-pinctrl.yaml b/dts/bindings/pinctrl/nxp,s32ze-siul2-pinctrl.yaml
@@ -1,10 +1,10 @@
-# Copyright 2022, 2024 NXP
+# Copyright 2022, 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  NXP S32 Pin Controller for S32Z/E SoCs
+  NXP SIUL2 Pin Controller for S32Z/E SoCs
 
-  The NXP S32 pin controller is a singleton node responsible for controlling
+  The NXP SIUL2 pin controller is a singleton node responsible for controlling
   the pin function selection and pin properties. This node, labeled 'pinctrl' in
   the SoC's devicetree, will define pin configurations in pin groups. Each group
   within the pin configuration defines the pin configuration for a peripheral,
@@ -65,14 +65,14 @@ description: |
   - Safe Mode is always kept as reset value (disabled).
   - Receiver Select is always kept as reset value (enables the differential vref based receiver).
 
-compatible: "nxp,s32ze-pinctrl"
+compatible: "nxp,s32ze-siul2-pinctrl"
 
 include: base.yaml
 
 child-binding:
-  description: NXP S32 pin controller pin group.
+  description: NXP SIUL2 pin controller pin group.
   child-binding:
-    description: NXP S32 pin controller pin configuration node.
+    description: NXP SIUL2 pin controller pin configuration node.
 
     include:
       - name: pincfg-node.yaml
diff --git a/include/zephyr/drivers/pinctrl/pinctrl_nxp_siul2_common.h b/include/zephyr/drivers/pinctrl/pinctrl_nxp_siul2_common.h
@@ -1,11 +1,11 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_SOC_NXP_S32_COMMON_SIUL2_PINCTRL_H_
-#define ZEPHYR_SOC_NXP_S32_COMMON_SIUL2_PINCTRL_H_
+#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_SIUL2_COMMON_H_
+#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_SIUL2_COMMON_H_
 
 #include <zephyr/devicetree.h>
 #include <zephyr/types.h>
@@ -33,7 +33,7 @@ typedef struct {
  * @param idx Property entry index.
  */
 #define Z_PINCTRL_STATE_PIN_INIT(group, prop, idx)                                                 \
-	{NXP_S32_PINMUX_INIT(group, DT_PROP_BY_IDX(group, prop, idx))},
+	{NXP_SIUL2_PINMUX_INIT(group, DT_PROP_BY_IDX(group, prop, idx))},
 
 /**
  * @brief Utility macro to initialize state pins contained in a given property.
@@ -49,4 +49,4 @@ typedef struct {
 
 /** @endcond */
 
-#endif /* ZEPHYR_SOC_NXP_S32_COMMON_SIUL2_PINCTRL_H_ */
+#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_SIUL2_COMMON_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h
diff --git a/include/zephyr/dt-bindings/pinctrl/nxp-siul2-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nxp-siul2-pinctrl.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2022, 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_SIUL2_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_SIUL2_PINCTRL_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+
+/*
+ * The NXP S32 pinmux configuration is encoded in a 32-bit field value as follows:
+ *
+ * - 0..2:   Output mux Source Signal Selection (MSCR.SSS)
+ * - 3..6:   Input mux Source Signal Selection (IMCR.SSS)
+ * - 7..15:  Input Multiplexed Signal Configuration Register (IMCR) index
+ * - 16..24: Multiplexed Signal Configuration Register (MSCR) index
+ * - 25..27: MSCR SIUL2 instance index (0..7)
+ * - 28..30: IMCR SIUL2 instance index (0..7)
+ * - 31:     Reserved for future use
+ */
+#define NXP_SIUL2_MSCR_SSS_SHIFT       0U
+#define NXP_SIUL2_MSCR_SSS_MASK        BIT_MASK(3)
+#define NXP_SIUL2_IMCR_SSS_SHIFT       3U
+#define NXP_SIUL2_IMCR_SSS_MASK        BIT_MASK(4)
+#define NXP_SIUL2_IMCR_IDX_SHIFT       7U
+#define NXP_SIUL2_IMCR_IDX_MASK        BIT_MASK(9)
+#define NXP_SIUL2_MSCR_IDX_SHIFT       16U
+#define NXP_SIUL2_MSCR_IDX_MASK        BIT_MASK(9)
+#define NXP_SIUL2_MSCR_SIUL2_IDX_SHIFT 25U
+#define NXP_SIUL2_MSCR_SIUL2_IDX_MASK  BIT_MASK(3)
+#define NXP_SIUL2_IMCR_SIUL2_IDX_SHIFT 28U
+#define NXP_SIUL2_IMCR_SIUL2_IDX_MASK  BIT_MASK(3)
+
+#define NXP_SIUL2_PINMUX_MSCR_SSS(cfg)                                                             \
+	(((cfg) & NXP_SIUL2_MSCR_SSS_MASK) << NXP_SIUL2_MSCR_SSS_SHIFT)
+
+#define NXP_SIUL2_PINMUX_IMCR_SSS(cfg)                                                             \
+	(((cfg) & NXP_SIUL2_IMCR_SSS_MASK) << NXP_SIUL2_IMCR_SSS_SHIFT)
+
+#define NXP_SIUL2_PINMUX_IMCR_IDX(cfg)                                                             \
+	(((cfg) & NXP_SIUL2_IMCR_IDX_MASK) << NXP_SIUL2_IMCR_IDX_SHIFT)
+
+#define NXP_SIUL2_PINMUX_MSCR_IDX(cfg)                                                             \
+	(((cfg) & NXP_SIUL2_MSCR_IDX_MASK) << NXP_SIUL2_MSCR_IDX_SHIFT)
+
+#define NXP_SIUL2_PINMUX_MSCR_SIUL2_IDX(cfg)                                                       \
+	(((cfg) & NXP_SIUL2_MSCR_SIUL2_IDX_MASK) << NXP_SIUL2_MSCR_SIUL2_IDX_SHIFT)
+
+#define NXP_SIUL2_PINMUX_IMCR_SIUL2_IDX(cfg)                                                       \
+	(((cfg) & NXP_SIUL2_IMCR_SIUL2_IDX_MASK) << NXP_SIUL2_IMCR_SIUL2_IDX_SHIFT)
+
+#define NXP_SIUL2_PINMUX_GET_MSCR_SSS(cfg)                                                         \
+	(((cfg) >> NXP_SIUL2_MSCR_SSS_SHIFT) & NXP_SIUL2_MSCR_SSS_MASK)
+
+#define NXP_SIUL2_PINMUX_GET_IMCR_SSS(cfg)                                                         \
+	(((cfg) >> NXP_SIUL2_IMCR_SSS_SHIFT) & NXP_SIUL2_IMCR_SSS_MASK)
+
+#define NXP_SIUL2_PINMUX_GET_IMCR_IDX(cfg)                                                         \
+	(((cfg) >> NXP_SIUL2_IMCR_IDX_SHIFT) & NXP_SIUL2_IMCR_IDX_MASK)
+
+#define NXP_SIUL2_PINMUX_GET_MSCR_IDX(cfg)                                                         \
+	(((cfg) >> NXP_SIUL2_MSCR_IDX_SHIFT) & NXP_SIUL2_MSCR_IDX_MASK)
+
+#define NXP_SIUL2_PINMUX_GET_MSCR_SIUL2_IDX(cfg)                                                   \
+	(((cfg) >> NXP_SIUL2_MSCR_SIUL2_IDX_SHIFT) & NXP_SIUL2_MSCR_SIUL2_IDX_MASK)
+
+#define NXP_SIUL2_PINMUX_GET_IMCR_SIUL2_IDX(cfg)                                                   \
+	(((cfg) >> NXP_SIUL2_IMCR_SIUL2_IDX_SHIFT) & NXP_SIUL2_IMCR_SIUL2_IDX_MASK)
+
+/**
+ * @brief Utility macro to build NXP S32 pinmux property for pinctrl nodes.
+ *
+ * @param mscr_siul2_idx MSCR SIUL2 instance index
+ * @param imcr_siul2_idx IMCR SIUL2 instance index
+ * @param mscr_idx Multiplexed Signal Configuration Register (MSCR) index
+ * @param mscr_sss Output mux Source Signal Selection (MSCR.SSS)
+ * @param imcr_idx Input Multiplexed Signal Configuration Register (IMCR) index
+ * @param imcr_sss Input mux Source Signal Selection (IMCR.SSS)
+ */
+#define NXP_SIUL2_PINMUX(mscr_siul2_idx, imcr_siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss)   \
+	(NXP_SIUL2_PINMUX_MSCR_SIUL2_IDX(mscr_siul2_idx) |                                         \
+	 NXP_SIUL2_PINMUX_IMCR_SIUL2_IDX(imcr_siul2_idx) |                                         \
+	 NXP_SIUL2_PINMUX_MSCR_IDX(mscr_idx) |                                                     \
+	 NXP_SIUL2_PINMUX_MSCR_SSS(mscr_sss) |                                                     \
+	 NXP_SIUL2_PINMUX_IMCR_IDX(imcr_idx) |                                                     \
+	 NXP_SIUL2_PINMUX_IMCR_SSS(imcr_sss))
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_SIUL2_PINCTRL_H_ */
diff --git a/soc/nxp/s32/s32k3/pinctrl_soc.h b/soc/nxp/s32/s32k3/pinctrl_soc.h
@@ -1,17 +1,16 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #ifndef ZEPHYR_SOC_NXP_S32_S32K3_PINCTRL_SOC_H_
 #define ZEPHYR_SOC_NXP_S32_S32K3_PINCTRL_SOC_H_
 
-#include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
+#include <zephyr/drivers/pinctrl/pinctrl_nxp_siul2_common.h>
+#include <zephyr/dt-bindings/pinctrl/nxp-siul2-pinctrl.h>
 #include <zephyr/sys/util.h>
 
-#include "../common/siul2_pinctrl.h"
-
 /* SIUL2 Multiplexed Signal Configuration */
 #define SIUL2_MSCR_SSS_MASK GENMASK(3, 0)
 #define SIUL2_MSCR_SSS(v)   FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v))
@@ -39,11 +38,11 @@
 #define SIUL2_IMCR_SSS_MASK GENMASK(3, 0)
 #define SIUL2_IMCR_SSS(v)   FIELD_PREP(SIUL2_IMCR_SSS_MASK, (v))
 
-#define NXP_S32_PINMUX_INIT(group, value)                                                          \
+#define NXP_SIUL2_PINMUX_INIT(group, value)                                                        \
 	.mscr = {                                                                                  \
-		.inst = NXP_S32_PINMUX_GET_MSCR_SIUL2_IDX(value),                                  \
-		.idx = NXP_S32_PINMUX_GET_MSCR_IDX(value),                                         \
-		.val = SIUL2_MSCR_SSS(NXP_S32_PINMUX_GET_MSCR_SSS(value)) |                        \
+		.inst = NXP_SIUL2_PINMUX_GET_MSCR_SIUL2_IDX(value),                                \
+		.idx = NXP_SIUL2_PINMUX_GET_MSCR_IDX(value),                                       \
+		.val = SIUL2_MSCR_SSS(NXP_SIUL2_PINMUX_GET_MSCR_SSS(value)) |                      \
 		       SIUL2_MSCR_OBE(DT_PROP(group, output_enable)) |                             \
 		       SIUL2_MSCR_IBE(DT_PROP(group, input_enable)) |                              \
 		       SIUL2_MSCR_PUE(DT_PROP(group, bias_pull_up) ||                              \
@@ -54,9 +53,9 @@
 		       SIUL2_MSCR_INV(DT_PROP(group, nxp_invert))                                  \
 	},                                                                                         \
 	.imcr = {                                                                                  \
-		.inst = NXP_S32_PINMUX_GET_IMCR_SIUL2_IDX(value),                                  \
-		.idx = NXP_S32_PINMUX_GET_IMCR_IDX(value),                                         \
-		.val = SIUL2_IMCR_SSS(NXP_S32_PINMUX_GET_IMCR_SSS(value)),                         \
+		.inst = NXP_SIUL2_PINMUX_GET_IMCR_SIUL2_IDX(value),                                \
+		.idx = NXP_SIUL2_PINMUX_GET_IMCR_IDX(value),                                       \
+		.val = SIUL2_IMCR_SSS(NXP_SIUL2_PINMUX_GET_IMCR_SSS(value)),                       \
 	}
 
 #endif /* ZEPHYR_SOC_NXP_S32_S32K3_PINCTRL_SOC_H_ */
diff --git a/soc/nxp/s32/s32ze/pinctrl_soc.h b/soc/nxp/s32/s32ze/pinctrl_soc.h
diff --git a/west.yml b/west.yml
