Release: v5.0

Highlights:
        * Added support for dsPIC33AK512MPS512
        * Fixes for kernel and arch test cases
        * Context switching refignments
        * Change console to on board USB-UART
        * Added satck protection
Fixes:
        * Context switch fixes
        * System timer fixes

Signed-off-by: Muhammed Zamroodh <[email protected]>

Author: MuhammedZamroodh

arch/Kconfig

@@ -183,7 +183,9 @@ config DSPIC
 	select STACK_SENTINAL
 	select ATOMIC_OPERATIONS_C
 	select ARCH_HAS_VECTOR_TABLE_RELOCATION
+	select ARCH_HAS_STACK_PROTECTION
 	select TICKLESS_CAPABLE
+	select ARCH_HAS_CUSTOM_BUSY_WAIT
 	help
 	  dspic architecture
 

arch/dspic/Kconfig

@@ -14,9 +14,6 @@ config GEN_ISR_TABLES
 config DYNAMIC_INTERRUPTS
 	default n
 
-config NUM_IRQS
-	default 279
-
 config GEN_IRQ_START_VECTOR
 	default 0
 
@@ -27,4 +24,14 @@ config DSPIC33_IRQ_OFFLOAD_IRQ
 	  Select the interrupt number used by irq_offload().
 	  This must be a valid, software-triggerable interrupt on the dsPIC33.
 
+config DSPIC_STACK_PROTECTION
+	bool
+	default y if HW_STACK_PROTECTION
+	select THREAD_STACK_INFO
+	help
+	  Enable stack overflow detection
+	  Will cause a fatal exception on stack overflow
+
+config TEST_EXTRA_STACK_SIZE
+	default 512
 endmenu

arch/dspic/core/irq_manage.c

@@ -22,65 +22,57 @@ void z_irq_spurious(const void *unused)
 
 void arch_irq_enable(unsigned int irq)
 {
-	volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
-					       &IEC5, &IEC6, &IEC7, &IEC8};
+	volatile uint32_t *int_enable_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), ie_offset);
 
 	unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
 	unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
-
 	/* Enable the interrupt by setting it's bit in interrupt enable register*/
-	*int_enable_reg[reg_index] |= (uint32_t)(1u << bit_pos);
+	int_enable_reg[reg_index] |= (uint32_t)(1u << bit_pos);
 }
 
 int arch_irq_is_enabled(unsigned int irq)
 {
-	volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
-					       &IEC5, &IEC6, &IEC7, &IEC8};
+	volatile uint32_t *int_enable_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), ie_offset);
 
 	unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
 	unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
 
-	return ((*int_enable_reg[reg_index] >> bit_pos) & 0x1u);
+	return ((int_enable_reg[reg_index] >> bit_pos) & 0x1u);
 }
 
 void arch_irq_disable(unsigned int irq)
 {
-	volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
-					       &IEC5, &IEC6, &IEC7, &IEC8};
+	volatile uint32_t *int_enable_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), ie_offset);
 
 	unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
 	unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
 
 	/* Disable the interrupt by clearing it's bit in interrupt enable register*/
-	*int_enable_reg[reg_index] &= (uint32_t)(~(1u << bit_pos));
+	int_enable_reg[reg_index] &= (uint32_t)(~(1u << bit_pos));
 }
 
 bool arch_dspic_irq_isset(unsigned int irq)
 {
-	volatile uint32_t *int_ifs_reg[] = {&IFS0, &IFS1, &IFS2, &IFS3, &IFS4,
-					    &IFS5, &IFS6, &IFS7, &IFS8};
+	volatile uint32_t *int_ifs_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), if_offset);
 	volatile int ret_ifs = false;
 	unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
 	unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
 
-	if ((bool)(void *)(*int_ifs_reg[reg_index] & (uint32_t)(1U << bit_pos))) {
+	if ( (int_ifs_reg[reg_index] & (1u << bit_pos)) != 0u ) {
 		ret_ifs = true;
 	}
 	return ret_ifs;
 }
 
-
-
 void z_dspic_enter_irq(int irq)
 {
-	volatile uint32_t *int_ifs_reg[] = {&IFS0, &IFS1, &IFS2, &IFS3, &IFS4,
-					    &IFS5, &IFS6, &IFS7, &IFS8};
+	volatile uint32_t *int_ifs_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), if_offset);
 
 	unsigned int reg_index = (unsigned int)irq / (sizeof(uint32_t) << 3);
 	unsigned int bit_pos = (unsigned int)irq % (sizeof(uint32_t) << 3);
 
 	/* Enable the interrupt by setting it's bit in interrupt enable register*/
-	*int_ifs_reg[reg_index] |= (uint32_t)(1u << bit_pos);
+	int_ifs_reg[reg_index] |= (uint32_t)(1u << bit_pos);
 }
 
 #ifdef __cplusplus

arch/dspic/core/isr_wrapper.S

@@ -2,19 +2,18 @@
  * Copyright (c) 2025, Microchip Technology Inc.
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <zephyr/devicetree.h>
+#include <offsets.h>
+#define OFFSET DT_PROP(DT_NODELABEL(intc0), if_offset)
 
+#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512)
+#define RAM_END 0x00013FFC
+#elif defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106)
+#define RAM_END 0x00007FFC
+#endif
 
 
-.LC0:
-    .long	_IFS0
-    .long	_IFS1
-    .long	_IFS2
-    .long	_IFS3
-    .long	_IFS4
-    .long	_IFS5
-    .long	_IFS6
-    .long	_IFS7
-    .long	_IFS8
+.equ IF_OFFSET, OFFSET
 
     .section .text,code
     .section .isr.text._COMMONInterrupt,keep,code,keep
@@ -38,6 +37,9 @@ __COMMONInterrupt:
 
 
     call	w1
+    mov.w _INTTREGbits,w0
+    and.l #(0x1ff&0xFFFF),w0
+    sub.l w0,#9,w0
     call	_arch_dspic_irq_clear
 
 
@@ -53,15 +55,12 @@ __COMMONInterrupt:
     bra	z,.L2
     cp0.b _z_sys_post_kernel
     bra	z,.L2
-    mov.bz _INTCON1bits+1,w0
-    bfext.l	#7,#1,w0,w0
-    mov.l w0,[w14]
-    bclr.b _INTCON1+1,#7
-    mov.l [w14],w0
     mov.l [--w15], w8
     ulnk
     CTXTSWP #0x0
     mov.l w0, [w15++]
+    mov.l #RAM_END, w0
+    mov.l w0, SPLIM
     mov.l sr, w0
     and #0xe0, w0
     bra nz, 1f
@@ -105,10 +104,10 @@ __COMMONInterrupt:
     lnk #0x4
 
     mov.l #__kernel, w0
-    mov.l #0x8, w1
+    mov.l #___cpu_t_current_OFFSET, w1
     add w0, w1, w1
     mov.l [w1], w2
-    mov.l #0x28, w1
+    mov.l #___thread_t_callee_saved_OFFSET, w1
     add w2, w1, w1
 
     mov.l w8, [w1++]
@@ -158,8 +157,6 @@ __COMMONInterrupt:
     mov.l [w2], [w1++]
     mov.l #XBREV, w2
     mov.l [w2], [w1++]
-    clr A
-    clr B
     slac.l A, [W1++]
     sac.l A, [W1++]
     suac.l A, [W1++]
@@ -174,15 +171,15 @@ __COMMONInterrupt:
     mov.sl	#__kernel+20,w0
     mov.l	[w0],w0
     mov.sl	#__kernel,w1
-    mov.l	w0,[w1+8]
-    mov.l	[w0+300],w0
+    mov.l	w0,[w1 + ___cpu_t_current_OFFSET]
+    mov.l	[w0 + ___thread_t_tls_OFFSET],w0
     rcall	__set_tls
 
     mov.l #__kernel, w0
-    mov.l #0x8, w1
+    mov.l #___cpu_t_current_OFFSET, w1
     add w0, w1, w1
     mov.l [w1], w2
-    mov.l #0x28, w1
+    mov.l #___thread_t_callee_saved_OFFSET, w1
     add w2, w1, w1
 
     mov.l [w1++], w8
@@ -234,12 +231,12 @@ __COMMONInterrupt:
     mov.l [w1++], [w2]
     clr A
     clr B
-    slac.l A, [W1++]
-    sac.l A, [W1++]
-    suac.l A, [W1++]
-    slac.l B, [W1++]
-    sac.l B, [W1++]
-    suac.l B, [W1++]
+    llac.l [w1++], A
+    lac.l [w1++], A
+    luac.l [w1++], A
+    llac.l [w1++], B
+    lac.l [w1++], B
+    luac.l [w1++], B
     mov.l [w1++], w15
     mov.l [w1++], w14
     mov.l #SPLIM, w2
@@ -286,10 +283,24 @@ __COMMONInterrupt:
     mov.l [w0], w0
     lnk #0x4
     1:
+    mov.l w2, [w15++]
+    mov.l w1, [w15++]
+    mov.l w0, [w15++]
+    mov.sl #__kernel, w0
+    mov.l [w0 + ___cpu_t_current_OFFSET], w1
+    mov.l #___thread_t_arch_OFFSET, w2
+    add.l w2, w1, w1
+    mov.l [w1 + ___thread_arch_t_swapped_from_thread_OFFSET], w0
+    mov.l #0, w2
+    cp.l  w2, w0
+    mov.l [--w15], w0
+    bra  z, 1f
+    mov.l [w1 + ___thread_arch_t_swap_return_value_OFFSET], w0
+    mov.l w2, [w1 + ___thread_arch_t_swapped_from_thread_OFFSET]
+    1:
+    mov.l [--w15], w1
+    mov.l [--w15], w2
     nop
-    cp.l w0,#0
-    bra	z,.L1
-    bset.b _INTCON1+1,#7
     retfie
 
 
@@ -307,23 +318,14 @@ __COMMONInterrupt:
     .type _arch_dspic_irq_clear,@function
 _arch_dspic_irq_clear:
 
-    lnk	#36
-    mov.w _INTTREGbits,w0
-    mov.sl #.LC0,w1
-    repeat #9-1
-    mov.l [w1++],[w14++]
-    sub.l #36,w14
-    sub.l #36,w1
-    and.l #(0x1ff&0xFFFF),w0
-    sub.l w0,#9,w0
-    lsr.l w0,#5,w1
-    sl.l w1,#2,w1
-    add.l w1,w14,w1
-    mov.l [w1],w2
-    and.l w0,#(0x1f&0x7F),w0
-    movs.l #0x1,w1
-    sl.l w1,w0,w0
-    com.l w0,w0
-    and.l w0,[w2],[w2]
-    ulnk
-    return
+	lnk	#0
+	lsr.l	w0,#5,w1
+	sl.l	w1,#2,w1
+	add.l	#IF_OFFSET,w1
+	and.l	w0,#(0x1f&0x7F),w2
+	movs.l	#0x1,w0
+	sl.l	w0,w2,w0
+	com.l	w0,w0
+	and.l	w0,[w1],[w1]
+	ulnk	
+	return

arch/dspic/core/offsets/offsets.c

@@ -7,4 +7,7 @@
 #include <zephyr/kernel.h>
 #include <kernel_offsets.h>
 
+GEN_OFFSET_SYM(_thread_arch_t, swap_return_value);
+GEN_OFFSET_SYM(_thread_arch_t, swapped_from_thread);
+
 GEN_ABS_SYM_END

arch/dspic/core/swap.c

@@ -19,9 +19,12 @@ int arch_swap(unsigned int key)
 	z_thread_mark_switched_out();
 #endif
 
+	register int result __asm__("w0");
 	/* store off key and return value */
 	_current->arch.cpu_level = key;
 	_current->arch.swap_return_value = -EAGAIN;
+	_current->arch.swapped_from_thread = 1;
+	result = _current->arch.swap_return_value;
 
 	/*Check if swap is needed*/
 	if (_kernel.ready_q.cache != _current) {
@@ -39,8 +42,17 @@ int arch_swap(unsigned int key)
 	 *       Make sure the return value is not being intrepreted
 	 *       wrongly
 	 */
-	irq_unlock(key);
-	register int result __asm__("w0");
+	__asm__ volatile(
+			"mov.l w1, [w15++]\n\t"
+			"mov.l w2, [w15++]\n\t"
+	);
+	_current->arch.swapped_from_thread = 0;
+	result = _current->arch.swap_return_value;
+	irq_unlock(_current->arch.cpu_level);
+	__asm__ volatile(
+			"mov.l [--w15], w2\n\t"
+			"mov.l [--w15], w1\n\t"
+	);
 	return result;
 
 	/* Context switch is performed here. Returning implies the

arch/dspic/core/thread.c

@@ -4,9 +4,9 @@
  */
 
 #include <zephyr/kernel.h>
+#include <kernel_arch_func.h>
 #include <string.h>
 
-#define RAM_END 0x00007FFC
 #define DSPIC_STATUS_DEFAULT 0
 
 void z_thread_entry(k_thread_entry_t thread, void *arg1, void *arg2, void *arg3);
@@ -23,7 +23,13 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *sta
 	/* Setting all register to zero*/
 	(void)memset(init_frame, 0, sizeof(struct arch_esf));
 
-	/* Setup initial stack frame*/
+	/* Setup initial stack frame
+	 * During the initial thread entry the w0 serves the function of thread
+	 * entry function pointer, but the general usage of w0 as per the C ABI
+	 * is to pass back the return data. Here set return value as entry pointer
+	 * value
+	 */
+	arch_thread_return_value_set(thread, (unsigned int)entry);
 	init_frame->W0 = (uint32_t)entry;
 	init_frame->W1 = (uint32_t)(void *)p1;
 	init_frame->W2 = (uint32_t)(void *)p2;
@@ -51,11 +57,13 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *sta
 	 */
 	thread->callee_saved.stack = (uint32_t)(void *)init_frame + (sizeof(struct arch_esf));
 	thread->callee_saved.frame = (uint32_t)thread->callee_saved.stack;
-	/*TODO: Need to handle splim properly*/
-	thread->callee_saved.splim = RAM_END;
+	thread->callee_saved.splim = (uint32_t)(thread->stack_info.start + thread->stack_info.size);
+	/*Set the initial key for irq unlock*/
+	thread->arch.cpu_level = 1;
 }
 
 int arch_coprocessors_disable(struct k_thread *thread)
 {
+	(void)thread;
 	return -ENOTSUP;
 }