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Merge pull request #2 from Zephyr4Microchip/mchp_zephyr_dspic_release_v3.0
Mchp zephyr dspic release v3.0
2 parents ad4c3e3 + c0b81b1 commit 38268f3

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‎arch/Kconfig‎

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@@ -167,6 +167,24 @@ config RX
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help
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Renesas RX architecture
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config DSPIC
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bool
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select ARCH_IS_SET
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select STACK_GROWS_UP
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select LITTLE_ENDIAN
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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select TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE
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select THREAD_LOCAL_STORAGE
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select INIT_STACKS
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select STACK_SENTINAL
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select ATOMIC_OPERATIONS_C
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select ARCH_HAS_VECTOR_TABLE_RELOCATION
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select CPU_HAS_ICACHE
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select CACHE_MANAGEMENT
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select TICKLESS_CAPABLE
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help
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dspic architecture
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config ARCH_IS_SET
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bool
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help
@@ -376,6 +394,11 @@ config STACK_GROWS_UP
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Select this option if the architecture has upward growing thread
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stacks. This is not common.
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config STACK_SENTINAL
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bool
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help
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It is a debugging and safety feature at the boundaries of the stack.
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config NO_UNUSED_STACK_INSPECTION
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bool
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help

‎arch/archs.yml‎

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@@ -29,3 +29,6 @@ archs:
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- name: rx
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path: rx
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full_name: Renesas RX
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- name: dspic
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path: dspic
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full_name: Microchip dsPIC

‎arch/dspic/CMakeLists.txt‎

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@@ -0,0 +1,8 @@
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if(CONFIG_BIG_ENDIAN)
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-big)
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else()
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-little)
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endif()
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zephyr_include_directories(${XCDSC_TOOLCHAIN_PATH}/support/generic/h/)
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zephyr_include_directories(include)
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add_subdirectory(core)

‎arch/dspic/Kconfig‎

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@@ -0,0 +1,23 @@
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# Copyright (c) 2025, Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "DSPIC Options"
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depends on DSPIC
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config ARCH
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string
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default "dspic"
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config GEN_ISR_TABLES
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default y
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config DYNAMIC_INTERRUPTS
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default n
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config NUM_IRQS
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default 279
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config GEN_IRQ_START_VECTOR
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default 0
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endmenu

‎arch/dspic/core/CMakeLists.txt‎

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@@ -0,0 +1,18 @@
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zephyr_library()
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zephyr_library_sources(
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cpu_idle.c
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fatal.c
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irq_manage.c
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isr_wrapper.c
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prep_c.c
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thread.c
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swap.c
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tls.c
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reset0.S
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init.S
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vector_table.S
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reset1.S
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)
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zephyr_linker_sources(ROM_START SORT_KEY 0x00 vector_table.ld)

‎arch/dspic/core/cpu_idle.c‎

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@@ -0,0 +1,34 @@
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/**
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* Copyright (c) 2025, Microchip Technology Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/irq.h>
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#include <zephyr/tracing/tracing.h>
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#include <zephyr/arch/cpu.h>
9+
#include <xc.h>
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#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
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void arch_cpu_idle(void)
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{
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__builtin_disable_interrupts();
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Idle();
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__builtin_enable_interrupts();
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}
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#endif
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#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
21+
void arch_cpu_atomic_idle(unsigned int key)
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{
23+
__builtin_disable_interrupts();
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Idle();
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arch_irq_unlock(key);
26+
__builtin_enable_interrupts();
27+
}
28+
#endif
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30+
FUNC_NORETURN void arch_system_halt(unsigned int reason)
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{
32+
(void)reason;
33+
CODE_UNREACHABLE;
34+
}

‎arch/dspic/core/fatal.c‎

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/*
2+
* Copyright (c) 2025, Microchip Technology Inc.
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* SPDX-License-Identifier: Apache-2.0
4+
*/
5+
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#include <zephyr/kernel.h>
7+
#include <zephyr/logging/log.h>
8+
9+
#ifndef _ASMLANGUAGE
10+
#include <xc.h>
11+
#ifdef __cplusplus
12+
extern "C" {
13+
#endif
14+
15+
LOG_MODULE_REGISTER(dspic, 4);
16+
17+
volatile uint32_t reason, address;
18+
19+
#define EXCEPTION_HANDLER __attribute__((interrupt, no_auto_psv, weak))
20+
#define BUS_ERROR_MASK 0xF
21+
#define MATH_ERROR_MASK 0x1F
22+
#define GENERAL_TRAP_MASK 0x8000000Fu
23+
24+
void __attribute__((weak)) TRAPS_halt_on_error(void);
25+
void EXCEPTION_HANDLER _BusErrorTrap(void);
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void EXCEPTION_HANDLER _AddressErrorTrap(void);
27+
void EXCEPTION_HANDLER _IllegalInstructionTrap(void);
28+
void EXCEPTION_HANDLER _MathErrorTrap(void);
29+
void EXCEPTION_HANDLER _StackErrorTrap(void);
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void EXCEPTION_HANDLER _GeneralTrap(void);
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void EXCEPTION_HANDLER _ReservedTrap0(void);
32+
void EXCEPTION_HANDLER _ReservedTrap7(void);
33+
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void EXCEPTION_HANDLER _ReservedTrap0(void)
35+
{
36+
}
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void EXCEPTION_HANDLER _ReservedTrap7(void)
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{
39+
}
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void __attribute__((weak)) TRAPS_halt_on_error(void)
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{
43+
/* stay here forever */
44+
while (1) {
45+
}
46+
}
47+
48+
/** Bus error.**/
49+
void EXCEPTION_HANDLER _BusErrorTrap(void)
50+
{
51+
/* Identify bus error via INTCON3, fetch trap address from
52+
* PCTRAP, and reset error flags
53+
*/
54+
reason = INTCON3 & BUS_ERROR_MASK;
55+
address = PCTRAP;
56+
LOG_ERR("ERROR !!! Exception reason = %d, address = 0x%x\n", reason, address);
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INTCON3 &= ~(BUS_ERROR_MASK);
58+
PCTRAP = 0;
59+
TRAPS_halt_on_error();
60+
}
61+
62+
/** Address error.**/
63+
void EXCEPTION_HANDLER _AddressErrorTrap(void)
64+
{
65+
/* fetch trap address from PCTRAP
66+
* and reset error flags
67+
*/
68+
address = PCTRAP;
69+
LOG_ERR("ERROR !!! Exception reason = %s, address = 0x%x\n", "Address Error", address);
70+
INTCON1bits.ADDRERR = 0;
71+
PCTRAP = 0;
72+
TRAPS_halt_on_error();
73+
}
74+
75+
/** Illegal instruction.**/
76+
void EXCEPTION_HANDLER _IllegalInstructionTrap(void)
77+
{
78+
address = PCTRAP;
79+
LOG_ERR("ERROR !!! Exception reason = %s, address = 0x%x\n", "Illegal Instruction",
80+
address);
81+
INTCON1bits.BADOPERR = 0;
82+
PCTRAP = 0;
83+
TRAPS_halt_on_error();
84+
}
85+
86+
/** Math error.**/
87+
void EXCEPTION_HANDLER _MathErrorTrap(void)
88+
{
89+
/* Identify math error via INTCON4, fetch trap address from
90+
* PCTRAP, and reset error flags
91+
*/
92+
reason = INTCON4 & MATH_ERROR_MASK;
93+
address = PCTRAP;
94+
LOG_ERR("ERROR !!! Exception reason = %d, address = 0x%x\n", reason, address);
95+
INTCON4 &= ~(MATH_ERROR_MASK);
96+
PCTRAP = 0;
97+
TRAPS_halt_on_error();
98+
}
99+
100+
/** Stack error.**/
101+
void EXCEPTION_HANDLER _StackErrorTrap(void)
102+
{
103+
INTCON1bits.STKERR = 0;
104+
PCTRAP = 0;
105+
TRAPS_halt_on_error();
106+
}
107+
108+
/** Generic error.**/
109+
void EXCEPTION_HANDLER _GeneralTrap(void)
110+
{
111+
reason = INTCON5 & GENERAL_TRAP_MASK;
112+
address = PCTRAP;
113+
LOG_ERR("ERROR !!! Exception reason = %d, address = 0x%x\n", reason, address);
114+
INTCON5 &= ~(GENERAL_TRAP_MASK);
115+
PCTRAP = 0;
116+
TRAPS_halt_on_error();
117+
}
118+
119+
#ifdef __cplusplus
120+
}
121+
#endif
122+
123+
#endif /* _ASMLANGUAGE */

‎arch/dspic/core/init.S‎

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1+
/*
2+
* Copyright (c) 2025, Microchip Technology Inc.
3+
* SPDX-License-Identifier: Apache-2.0
4+
*/
5+
6+
.section .init,code
7+
.global __custom_data_init
8+
.global __custom_data_init_extended
9+
10+
.equ __custom_data_init, __custom_data_init_extended
11+
__custom_data_init_extended:
12+
13+
.equiv FMT_CLEAR,0
14+
.equiv FMT_COPY2,1
15+
.equiv FMT_COPY3,2
16+
.equiv FMT_CALL, 3
17+
.equiv FMT_DUO_COPY3,0x1F
18+
19+
#define DINIT w0
20+
#define TLSOFFSET w1
21+
#define TBLOFFSET w9
22+
#define DSTOFFSET w10
23+
#define LEN w11
24+
#define FORMAT w12
25+
26+
mov.l w0, TBLOFFSET
27+
bra 4f
28+
29+
1:
30+
add.l DSTOFFSET,TLSOFFSET,DSTOFFSET
31+
mov.l [TBLOFFSET++], LEN
32+
mov.l [TBLOFFSET++], FORMAT
33+
34+
cp.b FORMAT, #FMT_CALL
35+
bra nz, 2f
36+
call DSTOFFSET
37+
bra 4f
38+
39+
2:
40+
cp.b FORMAT, #FMT_CLEAR
41+
bra nz, 2f
42+
9:
43+
sub.l LEN, #1, LEN
44+
repeat LEN
45+
clr.b [DSTOFFSET++]
46+
bra 4f
47+
48+
2:
49+
cp.b FORMAT, #FMT_COPY2
50+
bra z, 3f
51+
52+
3:
53+
sub.l LEN, #1, LEN
54+
repeat LEN
55+
mov.b [TBLOFFSET++], [DSTOFFSET++]
56+
add.l TBLOFFSET, #3, TBLOFFSET
57+
and1.l TBLOFFSET, #0x7C, TBLOFFSET
58+
59+
4:
60+
sub.l [TBLOFFSET++], #0, DSTOFFSET
61+
bra nz, 1b
62+
return

‎arch/dspic/core/irq_manage.c‎

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1+
/*
2+
* Copyright (c) 2025, Microchip Technology Inc.
3+
* SPDX-License-Identifier: Apache-2.0
4+
*/
5+
6+
#include <zephyr/kernel.h>
7+
#include <kswap.h>
8+
9+
#ifndef _ASMLANGUAGE
10+
#include <xc.h>
11+
12+
#ifdef __cplusplus
13+
extern "C" {
14+
#endif
15+
16+
void z_irq_spurious(const void *unused)
17+
{
18+
ARG_UNUSED(unused);
19+
while (1) {
20+
}
21+
return;
22+
}
23+
24+
void arch_irq_enable(unsigned int irq)
25+
{
26+
volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
27+
&IEC5, &IEC6, &IEC7, &IEC8};
28+
29+
unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
30+
unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
31+
32+
/* Enable the interrupt by setting it's bit in interrupt enable register*/
33+
*int_enable_reg[reg_index] |= (uint32_t)(1u << bit_pos);
34+
35+
return;
36+
}
37+
38+
int arch_irq_is_enabled(unsigned int irq)
39+
{
40+
volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
41+
&IEC5, &IEC6, &IEC7, &IEC8};
42+
43+
unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
44+
unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
45+
46+
return ((*int_enable_reg[reg_index] >> bit_pos) & 0x1u);
47+
}
48+
49+
void arch_irq_disable(unsigned int irq)
50+
{
51+
volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
52+
&IEC5, &IEC6, &IEC7, &IEC8};
53+
54+
unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
55+
unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
56+
57+
/* Disable the interrupt by clearing it's bit in interrupt enable register*/
58+
*int_enable_reg[reg_index] &= (uint32_t)(~(1u << bit_pos));
59+
60+
return;
61+
}
62+
63+
#ifdef __cplusplus
64+
}
65+
#endif
66+
67+
#endif /* _ASMLANGUAGE */

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