xtensa: fix Python script formatting via ruff

Uses ruff to format the gen_* python scripts.

Signed-off-by: Daniel Leung <[email protected]>

Author: dcpleung

.ruff-excludes.toml

@@ -1146,8 +1146,6 @@ exclude = [
     "./arch/x86/gen_idt.py",
     "./arch/x86/gen_mmu.py",
     "./arch/x86/zefi/zefi.py",
-    "./arch/xtensa/core/gen_vectors.py",
-    "./arch/xtensa/core/gen_zsr.py",
     "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py",
     "./doc/_scripts/gen_devicetree_rest.py",
     "./doc/_scripts/redirects.py",

arch/xtensa/core/gen_vectors.py

@@ -55,10 +55,12 @@
 debug_level = 0
 
 # Translation for the core-isa.h vs. linker section naming conventions
-sect_names = { "DOUBLEEXC" : "DoubleException",
-               "KERNEL" : "KernelException",
-               "NMI" : "NMIException",
-               "USER" : "UserException" }
+sect_names = {
+    "DOUBLEEXC": "DoubleException",
+    "KERNEL": "KernelException",
+    "NMI": "NMIException",
+    "USER": "UserException",
+}
 
 offsets = {}
 
@@ -112,9 +114,9 @@
 # The 1k alignment is experimental, the docs on the Relocatable Vector
 # Option doesn't specify an alignment at all, but writes to the
 # bottom bits don't take...
-print( "  .z_xtensa_vectors : ALIGN(1024) {")
-print( "    z_xtensa_vecbase = .;")
-print( "    KEEP(*(.WindowVectors.text));")
+print("  .z_xtensa_vectors : ALIGN(1024) {")
+print("    z_xtensa_vecbase = .;")
+print("    KEEP(*(.WindowVectors.text));")
 for s in sects:
     print(f"    KEEP(*(.{s}Vector.literal));")
     print(f"    . = 0x{offsets[s]:x};")

arch/xtensa/core/gen_zsr.py

@@ -11,22 +11,27 @@
 # -dM") core-isa.h file for the current architecture and assigns
 # registers to usages.
 
+
 def parse_args():
     parser = argparse.ArgumentParser(allow_abbrev=False)
 
-    parser.add_argument("--flush-reg", action="store_true",
-                        help="Enable scratch register ZSR_FLUSH for cache flushing")
-    parser.add_argument("--mmu", action="store_true",
-                        help="Enable scratch registers for MMU usage")
-    parser.add_argument("--syscall-scratch", action="store_true",
-                        help="Enable scratch registers for syscalls if needed")
-    parser.add_argument("coreisa",
-                        help="Path to preprocessed core-isa.h")
-    parser.add_argument("outfile",
-                        help="Output file")
+    parser.add_argument(
+        "--flush-reg",
+        action="store_true",
+        help="Enable scratch register ZSR_FLUSH for cache flushing",
+    )
+    parser.add_argument("--mmu", action="store_true", help="Enable scratch registers for MMU usage")
+    parser.add_argument(
+        "--syscall-scratch",
+        action="store_true",
+        help="Enable scratch registers for syscalls if needed",
+    )
+    parser.add_argument("coreisa", help="Path to preprocessed core-isa.h")
+    parser.add_argument("outfile", help="Output file")
 
     return parser.parse_args()
 
+
 args = parse_args()
 
 NEEDED = ["A0SAVE", "CPU"]
@@ -40,17 +45,19 @@ def parse_args():
 
 syms = {}
 
+
 def get(s):
     return syms.get(s, 0)
 
+
 with open(coreisa) as infile:
     for line in infile.readlines():
         m = re.match(r"^#define\s+([^ ]+)\s*(.*)", line.rstrip())
         if m:
             syms[m.group(1)] = m.group(2)
 
 # Use MISC registers first if available, that's what they're for
-regs = [ f"MISC{n}" for n in range(0, int(get("XCHAL_NUM_MISC_REGS"))) ]
+regs = [f"MISC{n}" for n in range(0, int(get("XCHAL_NUM_MISC_REGS")))]
 
 if args.syscall_scratch:
     # If there is no THREADPTR, we need to use syscall for