Release: v2.0

Highlights:
- Added support for xc-dsc toolchain: CMake scripts, linker files
- Arch bring-up for dsPIC (Curiosity board): thread creation,
  early boot, swap
- CMake: Improved path detection, removed debug messages, static lib fixes
- Interrupt vector table (IVT) initialization and macro definition
- MISRA compliance fixes
- Various bug fixes, stylistic cleanup, and compliance-related updates

Changes:
* cmake: Add xc-dsc toolchain support and linker script
* arch: dspic: Rename isr_table_vt.ld to vector_table.ld
* camke: Fix path detection for build dependencies
* cmake: Resolve include path issues
* cmake: Remove debug messages
* arch: dspic: Add thread creation and init logic
* arch: Resolve arch_swap implicit declaration warning
* arch: Add vector tables and common ISR wrapper
* cmake: Enable compiling assembly files
* cmake: Fix static library linking
* arch: Support IVT table placement and macros
* cmake: Skip init priorities check for xc-dsc
* toolchain: Remove stdlib usage (use picolibc instead)
* arch: Remove use of unimplemented functions
* arch: Early boot sequence implementation
* arch: Task swap and main thread entry logic

Signed-off-by: Udhayanandhan Jayakumar <[email protected]>

Author: Udhayanandhan-Jayakumar

arch/Kconfig

@@ -171,6 +171,28 @@ config RX
 	help
 	  Renesas RX architecture
 
+config DSPIC
+	bool
+	select ARCH_IS_SET
+	select STACK_GROWS_UP
+	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
+	select LITTLE_ENDIAN
+	select ARCH_HAS_THREAD_LOCAL_STORAGE
+	select TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE
+	select THREAD_LOCAL_STORAGE
+	select INIT_STACKS
+	select STACK_SENTINAL
+	select ATOMIC_OPERATIONS_C
+	select ARCH_HAS_VECTOR_TABLE_RELOCATION
+	select CPU_HAS_ICACHE
+	select ARCH_HAS_CUSTOM_CPU_IDLE
+	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
+	select DYNAMIC_INTERRUPTS
+	select CACHE_MANAGEMENT
+	select TICKLESS_CAPABLE
+	help
+	  dspic architecture
+
 config ARCH_IS_SET
 	bool
 	help
@@ -400,6 +422,11 @@ config STACK_GROWS_UP
 	  Select this option if the architecture has upward growing thread
 	  stacks. This is not common.
 
+config STACK_SENTINAL
+	bool
+	help
+	  It is a debugging and safety feature at the boundaries of the stack.
+
 config NO_UNUSED_STACK_INSPECTION
 	bool
 	help

arch/archs.yml

@@ -29,3 +29,6 @@ archs:
   - name: rx
     path: rx
     full_name: Renesas RX
+  - name: dspic
+    path: dspic
+    full_name: Microchip dsPIC

arch/dspic/CMakeLists.txt

@@ -0,0 +1,8 @@
+if(CONFIG_BIG_ENDIAN)
+    set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-big)
+else()
+    set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-little)
+endif()
+zephyr_include_directories(${XCDSC_TOOLCHAIN_PATH}/support/generic/h/)
+zephyr_include_directories(include)
+add_subdirectory(core)

arch/dspic/Kconfig

@@ -0,0 +1,14 @@
+menu "DSPIC Options"
+	depends on DSPIC
+
+config ARCH
+	string
+	default "dspic"
+
+config NUM_IRQS
+	default 287
+
+config GEN_IRQ_START_VECTOR
+	default 8
+
+endmenu

arch/dspic/core/CMakeLists.txt

@@ -0,0 +1,18 @@
+zephyr_library()
+
+zephyr_library_sources(
+    cpu_idle.c
+    fatal.c
+    irq_manage.c
+    isr_wrapper.c
+    prep_c.c
+    thread.c
+    swap.c
+    tls.c
+    reset0.S
+    init.S
+    vector_table.S
+    reset1.S
+)
+
+zephyr_linker_sources(ROM_START SORT_KEY 0x04 vector_table.ld)

arch/dspic/core/cpu_idle.c

@@ -0,0 +1,27 @@
+/**
+ * Copyright (c) 2025, Microchip Technology Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/irq.h>
+#include <zephyr/tracing/tracing.h>
+#include <zephyr/arch/cpu.h>
+
+#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
+void arch_cpu_idle(void)
+{
+}
+#endif
+
+#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
+void arch_cpu_atomic_idle(unsigned int key)
+{
+	(void)key;
+}
+#endif
+
+FUNC_NORETURN void arch_system_halt(unsigned int reason)
+{
+	(void)reason;
+	CODE_UNREACHABLE;
+}

arch/dspic/core/fatal.c

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2025, Microchip Technology Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+volatile uint32_t reason, address;
+
+#define EXCEPTION_HANDLER __attribute__((interrupt, no_auto_psv, keep))
+
+void EXCEPTION_HANDLER _ReservedTrap7(void);
+void __attribute__((weak)) TRAPS_halt_on_error(void);
+void EXCEPTION_HANDLER _BusErrorTrap(void);
+void EXCEPTION_HANDLER _AddressErrorTrap(void);
+void EXCEPTION_HANDLER _IllegalInstructionTrap(void);
+void EXCEPTION_HANDLER _MathErrorTrap(void);
+void EXCEPTION_HANDLER _StackErrorTrap(void);
+void EXCEPTION_HANDLER _GeneralTrap(void);
+void EXCEPTION_HANDLER _ReservedTrap0(void);
+void EXCEPTION_HANDLER _ReservedTrap7(void);
+
+void __attribute__((weak)) TRAPS_halt_on_error(void)
+{
+}
+
+/** Bus error.**/
+void EXCEPTION_HANDLER _BusErrorTrap(void)
+{
+	__asm__("nop");
+	__asm__("retfie");
+}
+
+/** Address error.**/
+void EXCEPTION_HANDLER _AddressErrorTrap(void)
+{
+	__asm__("nop");
+	__asm__("retfie");
+}
+
+/** Illegal instruction.**/
+void EXCEPTION_HANDLER _IllegalInstructionTrap(void)
+{
+	__asm__("nop");
+	__asm__("retfie");
+}
+
+/** Math error.**/
+void EXCEPTION_HANDLER _MathErrorTrap(void)
+{
+	__asm__("nop");
+	__asm__("retfie");
+}
+
+/** Stack error.**/
+void EXCEPTION_HANDLER _StackErrorTrap(void)
+{
+	__asm__("nop");
+	__asm__("retfie");
+}
+
+/** Generic error.**/
+void EXCEPTION_HANDLER _GeneralTrap(void)
+{
+	__asm__("nop");
+	__asm__("retfie");
+}
+
+/** Reserved Trap0.**/
+void EXCEPTION_HANDLER _ReservedTrap0(void)
+{
+	__asm__("nop");
+	__asm__("retfie");
+}
+
+/** Reserved Trap7.**/
+void EXCEPTION_HANDLER _ReservedTrap7(void)
+{
+	__asm__("nop");
+	__asm__("retfie");
+}

arch/dspic/core/init.S

@@ -0,0 +1,57 @@
+.section .init,code
+.global __custom_data_init
+.global __custom_data_init_extended
+
+.equ __custom_data_init, __custom_data_init_extended
+__custom_data_init_extended:
+
+	.equiv   FMT_CLEAR,0
+	.equiv   FMT_COPY2,1
+	.equiv   FMT_COPY3,2
+	.equiv   FMT_CALL, 3
+	.equiv   FMT_DUO_COPY3,0x1F
+
+#define DINIT     w0
+#define TLSOFFSET w1
+#define TBLOFFSET w9
+#define DSTOFFSET w10
+#define LEN       w11
+#define FORMAT    w12
+
+	mov.l    w0, TBLOFFSET
+	bra      4f
+
+1:
+	add.l    DSTOFFSET,TLSOFFSET,DSTOFFSET
+	mov.l    [TBLOFFSET++], LEN
+	mov.l    [TBLOFFSET++], FORMAT
+
+	cp.b     FORMAT, #FMT_CALL
+	bra nz,  2f
+	call     DSTOFFSET
+	bra      4f
+
+2:
+    cp.b     FORMAT, #FMT_CLEAR
+    bra nz,  2f
+9:
+	sub.l    LEN, #1, LEN
+	repeat   LEN
+	clr.b    [DSTOFFSET++]
+	bra      4f
+
+2:
+	cp.b     FORMAT, #FMT_COPY2
+	bra z,   3f
+
+3:
+	sub.l   LEN, #1, LEN
+	repeat  LEN
+	mov.b   [TBLOFFSET++], [DSTOFFSET++]
+	add.l   TBLOFFSET, #3, TBLOFFSET
+	and1.l  TBLOFFSET, #0x7C, TBLOFFSET
+
+4:
+	sub.l   [TBLOFFSET++], #0, DSTOFFSET
+	bra nz, 1b
+	return

arch/dspic/core/irq_manage.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025, Microchip Technology Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <kswap.h>
+
+void z_irq_spurious(const void *unused)
+{
+	(void)unused;
+}
+
+void arch_irq_enable(unsigned int irq)
+{
+	(void)irq;
+}
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	(void)irq;
+	return 0;
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+	(void)irq;
+}

arch/dspic/core/isr_wrapper.c

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025, Microchip Technology Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/irq.h>
+#include <zephyr/pm/pm.h>
+#include <zephyr/sw_isr_table.h>
+#include <kernel_arch_func.h>
+
+/* dsPIC33A interrtup exit routine. Will check if a context
+ * switch is required. If so, z_dspic_do_swap() will be called
+ * to affect the context switch
+ */
+void __attribute__((naked)) z_dspic_exc_exit(void)
+{
+}
+
+void __attribute__((interrupt, naked)) _COMMONInterrupt(void)
+{
+}