Release: v4.0

Highlights:
- UART interrupt support
- Program memory optimisation
- Support for ztest and twister
- Context switch refignment
- Kernel and thread test cases
- Samples support
   - UART: Echo bot, native tty, passthrough
   - Blinky
   - Philosophers
   - Hello world
- Pin control driver
- New board support (sdPIC33AK512MPS512)
Fixes:
- Context switch fixes
- System timer fixes
- Build fixes

Signed-off-by: Muhammed Zamroodh <[email protected]>

Author: MuhammedZamroodh

arch/Kconfig

@@ -174,7 +174,6 @@ config DSPIC
 	bool
 	select ARCH_IS_SET
 	select STACK_GROWS_UP
-	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
 	select LITTLE_ENDIAN
 	select ARCH_HAS_THREAD_LOCAL_STORAGE
 	select TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE
@@ -183,11 +182,6 @@ config DSPIC
 	select STACK_SENTINAL
 	select ATOMIC_OPERATIONS_C
 	select ARCH_HAS_VECTOR_TABLE_RELOCATION
-	select CPU_HAS_ICACHE
-	select ARCH_HAS_CUSTOM_CPU_IDLE
-	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
-	select DYNAMIC_INTERRUPTS
-	select CACHE_MANAGEMENT
 	select TICKLESS_CAPABLE
 	help
 	  dspic architecture

arch/dspic/CMakeLists.txt

@@ -3,6 +3,6 @@ if(CONFIG_BIG_ENDIAN)
 else()
     set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-little)
 endif()
-zephyr_include_directories(${XCDSC_TOOLCHAIN_PATH}/support/generic/h/)
+zephyr_include_directories(${DFP_ROOT}/support/generic/h/)
 zephyr_include_directories(include)
 add_subdirectory(core)

arch/dspic/Kconfig

@@ -1,14 +1,30 @@
+# Copyright (c) 2025, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
 menu "DSPIC Options"
 	depends on DSPIC
 
 config ARCH
 	string
 	default "dspic"
 
+config GEN_ISR_TABLES
+	default y
+
+config DYNAMIC_INTERRUPTS
+	default n
+
 config NUM_IRQS
-	default 287
+	default 279
 
 config GEN_IRQ_START_VECTOR
-	default 8
+	default 0
+
+config DSPIC33_IRQ_OFFLOAD_IRQ
+	int "IRQ number for irq_offload()"
+	default 34
+	help
+	  Select the interrupt number used by irq_offload().
+	  This must be a valid, software-triggerable interrupt on the dsPIC33.
 
 endmenu

arch/dspic/core/CMakeLists.txt

@@ -4,7 +4,7 @@ zephyr_library_sources(
     cpu_idle.c
     fatal.c
     irq_manage.c
-    isr_wrapper.c
+    isr_wrapper.S
     prep_c.c
     thread.c
     swap.c
@@ -13,6 +13,7 @@ zephyr_library_sources(
     init.S
     vector_table.S
     reset1.S
+    irq_offload.c
 )
 
-zephyr_linker_sources(ROM_START SORT_KEY 0x04 vector_table.ld)
+zephyr_linker_sources(ROM_START SORT_KEY 0x00 vector_table.ld)

arch/dspic/core/cpu_idle.c

@@ -6,17 +6,24 @@
 #include <zephyr/irq.h>
 #include <zephyr/tracing/tracing.h>
 #include <zephyr/arch/cpu.h>
+#include <xc.h>
 
 #ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
 void arch_cpu_idle(void)
 {
+	__builtin_disable_interrupts();
+	Idle();
+	__builtin_enable_interrupts();
 }
 #endif
 
 #ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
 void arch_cpu_atomic_idle(unsigned int key)
 {
-	(void)key;
+	__builtin_disable_interrupts();
+	Idle();
+	arch_irq_unlock(key);
+	__builtin_enable_interrupts();
 }
 #endif
 

arch/dspic/core/fatal.c

@@ -4,12 +4,23 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#ifndef _ASMLANGUAGE
+#include <xc.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+LOG_MODULE_REGISTER(dspic, 4);
 
 volatile uint32_t reason, address;
 
-#define EXCEPTION_HANDLER __attribute__((interrupt, no_auto_psv, keep))
+#define EXCEPTION_HANDLER __attribute__((interrupt, no_auto_psv, weak, naked))
+#define BUS_ERROR_MASK    0xF
+#define MATH_ERROR_MASK   0x1F
+#define GENERAL_TRAP_MASK 0x8000000Fu
 
-void EXCEPTION_HANDLER _ReservedTrap7(void);
 void __attribute__((weak)) TRAPS_halt_on_error(void);
 void EXCEPTION_HANDLER _BusErrorTrap(void);
 void EXCEPTION_HANDLER _AddressErrorTrap(void);
@@ -20,62 +31,93 @@ void EXCEPTION_HANDLER _GeneralTrap(void);
 void EXCEPTION_HANDLER _ReservedTrap0(void);
 void EXCEPTION_HANDLER _ReservedTrap7(void);
 
+void EXCEPTION_HANDLER _ReservedTrap0(void)
+{
+}
+void EXCEPTION_HANDLER _ReservedTrap7(void)
+{
+}
+
 void __attribute__((weak)) TRAPS_halt_on_error(void)
 {
+	/* stay here forever */
+	while (1) {
+	}
 }
 
 /** Bus error.**/
 void EXCEPTION_HANDLER _BusErrorTrap(void)
 {
-	__asm__("nop");
-	__asm__("retfie");
+	/* Identify bus error via INTCON3, fetch trap address from
+	 * PCTRAP, and reset error flags
+	 */
+	reason = INTCON3 & BUS_ERROR_MASK;
+	address = PCTRAP;
+	LOG_ERR("ERROR !!! Exception reason = %d, address = 0x%x\n", reason, address);
+	INTCON3 &= ~(BUS_ERROR_MASK);
+	PCTRAP = 0;
+	TRAPS_halt_on_error();
 }
 
 /** Address error.**/
 void EXCEPTION_HANDLER _AddressErrorTrap(void)
 {
-	__asm__("nop");
-	__asm__("retfie");
+	/* fetch trap address from PCTRAP
+	 * and reset error flags
+	 */
+	address = PCTRAP;
+	LOG_ERR("ERROR !!! Exception reason = %s, address = 0x%x\n", "Address Error", address);
+	INTCON1bits.ADDRERR = 0;
+	PCTRAP = 0;
+	TRAPS_halt_on_error();
 }
 
 /** Illegal instruction.**/
 void EXCEPTION_HANDLER _IllegalInstructionTrap(void)
 {
-	__asm__("nop");
-	__asm__("retfie");
+	address = PCTRAP;
+	LOG_ERR("ERROR !!! Exception reason = %s, address = 0x%x\n", "Illegal Instruction",
+		address);
+	INTCON1bits.BADOPERR = 0;
+	PCTRAP = 0;
+	TRAPS_halt_on_error();
 }
 
 /** Math error.**/
 void EXCEPTION_HANDLER _MathErrorTrap(void)
 {
-	__asm__("nop");
-	__asm__("retfie");
+	/* Identify math error via INTCON4, fetch trap address from
+	 * PCTRAP, and reset error flags
+	 */
+	reason = INTCON4 & MATH_ERROR_MASK;
+	address = PCTRAP;
+	LOG_ERR("ERROR !!! Exception reason = %d, address = 0x%x\n", reason, address);
+	INTCON4 &= ~(MATH_ERROR_MASK);
+	PCTRAP = 0;
+	TRAPS_halt_on_error();
 }
 
 /** Stack error.**/
 void EXCEPTION_HANDLER _StackErrorTrap(void)
 {
-	__asm__("nop");
-	__asm__("retfie");
+	INTCON1bits.STKERR = 0;
+	PCTRAP = 0;
+	TRAPS_halt_on_error();
 }
 
 /** Generic error.**/
 void EXCEPTION_HANDLER _GeneralTrap(void)
 {
-	__asm__("nop");
-	__asm__("retfie");
+	reason = INTCON5 & GENERAL_TRAP_MASK;
+	address = PCTRAP;
+	LOG_ERR("ERROR !!! Exception reason = %d, address = 0x%x\n", reason, address);
+	INTCON5 &= ~(GENERAL_TRAP_MASK);
+	PCTRAP = 0;
+	TRAPS_halt_on_error();
 }
 
-/** Reserved Trap0.**/
-void EXCEPTION_HANDLER _ReservedTrap0(void)
-{
-	__asm__("nop");
-	__asm__("retfie");
+#ifdef __cplusplus
 }
+#endif
 
-/** Reserved Trap7.**/
-void EXCEPTION_HANDLER _ReservedTrap7(void)
-{
-	__asm__("nop");
-	__asm__("retfie");
-}
+#endif /* _ASMLANGUAGE */

arch/dspic/core/init.S

@@ -1,3 +1,8 @@
+/*
+ * Copyright (c) 2025, Microchip Technology Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 .section .init,code
 .global __custom_data_init
 .global __custom_data_init_extended

arch/dspic/core/irq_manage.c

@@ -6,23 +6,85 @@
 #include <zephyr/kernel.h>
 #include <kswap.h>
 
+#ifndef _ASMLANGUAGE
+#include <xc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 void z_irq_spurious(const void *unused)
 {
-	(void)unused;
+	ARG_UNUSED(unused);
+	while (1) {
+	}
 }
 
 void arch_irq_enable(unsigned int irq)
 {
-	(void)irq;
+	volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
+					       &IEC5, &IEC6, &IEC7, &IEC8};
+
+	unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
+	unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
+
+	/* Enable the interrupt by setting it's bit in interrupt enable register*/
+	*int_enable_reg[reg_index] |= (uint32_t)(1u << bit_pos);
 }
 
 int arch_irq_is_enabled(unsigned int irq)
 {
-	(void)irq;
-	return 0;
+	volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
+					       &IEC5, &IEC6, &IEC7, &IEC8};
+
+	unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
+	unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
+
+	return ((*int_enable_reg[reg_index] >> bit_pos) & 0x1u);
 }
 
 void arch_irq_disable(unsigned int irq)
 {
-	(void)irq;
+	volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4,
+					       &IEC5, &IEC6, &IEC7, &IEC8};
+
+	unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
+	unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
+
+	/* Disable the interrupt by clearing it's bit in interrupt enable register*/
+	*int_enable_reg[reg_index] &= (uint32_t)(~(1u << bit_pos));
+}
+
+bool arch_dspic_irq_isset(unsigned int irq)
+{
+	volatile uint32_t *int_ifs_reg[] = {&IFS0, &IFS1, &IFS2, &IFS3, &IFS4,
+					    &IFS5, &IFS6, &IFS7, &IFS8};
+	volatile int ret_ifs = false;
+	unsigned int reg_index = irq / (sizeof(uint32_t) << 3);
+	unsigned int bit_pos = irq % (sizeof(uint32_t) << 3);
+
+	if ((bool)(void *)(*int_ifs_reg[reg_index] & (uint32_t)(1U << bit_pos))) {
+		ret_ifs = true;
+	}
+	return ret_ifs;
 }
+
+
+
+void z_dspic_enter_irq(int irq)
+{
+	volatile uint32_t *int_ifs_reg[] = {&IFS0, &IFS1, &IFS2, &IFS3, &IFS4,
+					    &IFS5, &IFS6, &IFS7, &IFS8};
+
+	unsigned int reg_index = (unsigned int)irq / (sizeof(uint32_t) << 3);
+	unsigned int bit_pos = (unsigned int)irq % (sizeof(uint32_t) << 3);
+
+	/* Enable the interrupt by setting it's bit in interrupt enable register*/
+	*int_ifs_reg[reg_index] |= (uint32_t)(1u << bit_pos);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASMLANGUAGE */

arch/dspic/core/irq_offload.c

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2025, Microchip Technology Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/kernel_structs.h>
+#include <kernel_internal.h>
+#include <zephyr/irq.h>
+#include <zephyr/irq_offload.h>
+#include <xc.h>
+
+static irq_offload_routine_t _offload_routine;
+static const void *offload_param;
+
+void z_irq_do_offload(void)
+{
+	irq_offload_routine_t tmp;
+
+	if (_offload_routine != NULL) {
+
+		tmp = _offload_routine;
+		_offload_routine = NULL;
+
+		tmp((const void *)offload_param);
+	}
+}
+
+void handler(void)
+{
+	z_irq_do_offload();
+}
+
+void arch_irq_offload_init(void)
+{
+	IRQ_CONNECT(CONFIG_DSPIC33_IRQ_OFFLOAD_IRQ, 1, handler, NULL, 0);
+}
+
+void arch_irq_offload(irq_offload_routine_t routine, const void *parameter)
+{
+	uint32_t key = irq_lock();
+
+	_offload_routine = routine;
+	offload_param = parameter;
+	irq_enable(CONFIG_DSPIC33_IRQ_OFFLOAD_IRQ);
+	z_dspic_enter_irq(CONFIG_DSPIC33_IRQ_OFFLOAD_IRQ);
+	irq_unlock(key);
+}