diff --git a/arch/Kconfig b/arch/Kconfig index 5a51595281a8e..37579c139b100 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -182,9 +182,9 @@ config DSPIC select STACK_SENTINAL select ATOMIC_OPERATIONS_C select ARCH_HAS_VECTOR_TABLE_RELOCATION - select CPU_HAS_ICACHE - select CACHE_MANAGEMENT + select ARCH_HAS_STACK_PROTECTION select TICKLESS_CAPABLE + select ARCH_HAS_CUSTOM_BUSY_WAIT help dspic architecture diff --git a/arch/dspic/CMakeLists.txt b/arch/dspic/CMakeLists.txt index fc07eabc00031..f8fdb8e045490 100644 --- a/arch/dspic/CMakeLists.txt +++ b/arch/dspic/CMakeLists.txt @@ -3,6 +3,6 @@ if(CONFIG_BIG_ENDIAN) else() set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-little) endif() -zephyr_include_directories(${XCDSC_TOOLCHAIN_PATH}/support/generic/h/) +zephyr_include_directories(${DFP_ROOT}/support/generic/h/) zephyr_include_directories(include) add_subdirectory(core) diff --git a/arch/dspic/Kconfig b/arch/dspic/Kconfig index 45ebe011c0ff7..478e9ab303eaf 100644 --- a/arch/dspic/Kconfig +++ b/arch/dspic/Kconfig @@ -14,10 +14,24 @@ config GEN_ISR_TABLES config DYNAMIC_INTERRUPTS default n -config NUM_IRQS - default 279 - config GEN_IRQ_START_VECTOR default 0 +config DSPIC33_IRQ_OFFLOAD_IRQ + int "IRQ number for irq_offload()" + default 34 + help + Select the interrupt number used by irq_offload(). + This must be a valid, software-triggerable interrupt on the dsPIC33. + +config DSPIC_STACK_PROTECTION + bool + default y if HW_STACK_PROTECTION + select THREAD_STACK_INFO + help + Enable stack overflow detection + Will cause a fatal exception on stack overflow + +config TEST_EXTRA_STACK_SIZE + default 512 endmenu diff --git a/arch/dspic/core/CMakeLists.txt b/arch/dspic/core/CMakeLists.txt index ecc7a0ea64868..2e9dba116d1ee 100644 --- a/arch/dspic/core/CMakeLists.txt +++ b/arch/dspic/core/CMakeLists.txt @@ -4,7 +4,7 @@ zephyr_library_sources( cpu_idle.c fatal.c irq_manage.c - isr_wrapper.c + isr_wrapper.S prep_c.c thread.c swap.c @@ -13,6 +13,7 @@ zephyr_library_sources( init.S vector_table.S reset1.S + irq_offload.c ) zephyr_linker_sources(ROM_START SORT_KEY 0x00 vector_table.ld) diff --git a/arch/dspic/core/fatal.c b/arch/dspic/core/fatal.c index c9b9e75185af6..f6fd1bf240f44 100644 --- a/arch/dspic/core/fatal.c +++ b/arch/dspic/core/fatal.c @@ -16,7 +16,7 @@ LOG_MODULE_REGISTER(dspic, 4); volatile uint32_t reason, address; -#define EXCEPTION_HANDLER __attribute__((interrupt, no_auto_psv, weak)) +#define EXCEPTION_HANDLER __attribute__((interrupt, no_auto_psv, weak, naked)) #define BUS_ERROR_MASK 0xF #define MATH_ERROR_MASK 0x1F #define GENERAL_TRAP_MASK 0x8000000Fu diff --git a/arch/dspic/core/irq_manage.c b/arch/dspic/core/irq_manage.c index 51f9eb1328060..b06f3f66d6b7c 100644 --- a/arch/dspic/core/irq_manage.c +++ b/arch/dspic/core/irq_manage.c @@ -18,46 +18,61 @@ void z_irq_spurious(const void *unused) ARG_UNUSED(unused); while (1) { } - return; } void arch_irq_enable(unsigned int irq) { - volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4, - &IEC5, &IEC6, &IEC7, &IEC8}; + volatile uint32_t *int_enable_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), ie_offset); unsigned int reg_index = irq / (sizeof(uint32_t) << 3); unsigned int bit_pos = irq % (sizeof(uint32_t) << 3); - /* Enable the interrupt by setting it's bit in interrupt enable register*/ - *int_enable_reg[reg_index] |= (uint32_t)(1u << bit_pos); - - return; + int_enable_reg[reg_index] |= (uint32_t)(1u << bit_pos); } int arch_irq_is_enabled(unsigned int irq) { - volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4, - &IEC5, &IEC6, &IEC7, &IEC8}; + volatile uint32_t *int_enable_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), ie_offset); unsigned int reg_index = irq / (sizeof(uint32_t) << 3); unsigned int bit_pos = irq % (sizeof(uint32_t) << 3); - return ((*int_enable_reg[reg_index] >> bit_pos) & 0x1u); + return ((int_enable_reg[reg_index] >> bit_pos) & 0x1u); } void arch_irq_disable(unsigned int irq) { - volatile uint32_t *int_enable_reg[] = {&IEC0, &IEC1, &IEC2, &IEC3, &IEC4, - &IEC5, &IEC6, &IEC7, &IEC8}; + volatile uint32_t *int_enable_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), ie_offset); unsigned int reg_index = irq / (sizeof(uint32_t) << 3); unsigned int bit_pos = irq % (sizeof(uint32_t) << 3); /* Disable the interrupt by clearing it's bit in interrupt enable register*/ - *int_enable_reg[reg_index] &= (uint32_t)(~(1u << bit_pos)); + int_enable_reg[reg_index] &= (uint32_t)(~(1u << bit_pos)); +} + +bool arch_dspic_irq_isset(unsigned int irq) +{ + volatile uint32_t *int_ifs_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), if_offset); + volatile int ret_ifs = false; + unsigned int reg_index = irq / (sizeof(uint32_t) << 3); + unsigned int bit_pos = irq % (sizeof(uint32_t) << 3); - return; + if ( (int_ifs_reg[reg_index] & (1u << bit_pos)) != 0u ) { + ret_ifs = true; + } + return ret_ifs; +} + +void z_dspic_enter_irq(int irq) +{ + volatile uint32_t *int_ifs_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), if_offset); + + unsigned int reg_index = (unsigned int)irq / (sizeof(uint32_t) << 3); + unsigned int bit_pos = (unsigned int)irq % (sizeof(uint32_t) << 3); + + /* Enable the interrupt by setting it's bit in interrupt enable register*/ + int_ifs_reg[reg_index] |= (uint32_t)(1u << bit_pos); } #ifdef __cplusplus diff --git a/arch/dspic/core/irq_offload.c b/arch/dspic/core/irq_offload.c new file mode 100644 index 0000000000000..b20c7eb21c9cb --- /dev/null +++ b/arch/dspic/core/irq_offload.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +static irq_offload_routine_t _offload_routine; +static const void *offload_param; + +void z_irq_do_offload(void) +{ + irq_offload_routine_t tmp; + + if (_offload_routine != NULL) { + + tmp = _offload_routine; + _offload_routine = NULL; + + tmp((const void *)offload_param); + } +} + +void handler(void) +{ + z_irq_do_offload(); +} + +void arch_irq_offload_init(void) +{ + IRQ_CONNECT(CONFIG_DSPIC33_IRQ_OFFLOAD_IRQ, 1, handler, NULL, 0); +} + +void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) +{ + uint32_t key = irq_lock(); + + _offload_routine = routine; + offload_param = parameter; + irq_enable(CONFIG_DSPIC33_IRQ_OFFLOAD_IRQ); + z_dspic_enter_irq(CONFIG_DSPIC33_IRQ_OFFLOAD_IRQ); + irq_unlock(key); +} diff --git a/arch/dspic/core/isr_wrapper.S b/arch/dspic/core/isr_wrapper.S new file mode 100644 index 0000000000000..0c278ec848d60 --- /dev/null +++ b/arch/dspic/core/isr_wrapper.S @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#define OFFSET DT_PROP(DT_NODELABEL(intc0), if_offset) + +#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) +#define RAM_END 0x00013FFC +#elif defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106) +#define RAM_END 0x00007FFC +#endif + + +.equ IF_OFFSET, OFFSET + + .section .text,code + .section .isr.text._COMMONInterrupt,keep,code,keep + .align 4 + .global __COMMONInterrupt ; export + .type __COMMONInterrupt,@function +__COMMONInterrupt: + .section .isr.text._COMMONInterrupt,keep,code,keep + lnk #0x4 + mov.l w8, [w15++] + mov.sl #__kernel,w8 + add.l [w8],#1,[w8] + mov.w _INTTREGbits,w0 + and.l #(0x1ff&0xFFFF),w0 + sub.l w0,#9,w0 + mov.sl #__sw_isr_table,w1 + sl.l w0,#3,w0 + add.l w0,w1,w2 + mov.l [w2+4],w1 + mov.l [w2],w0 + + + call w1 + mov.w _INTTREGbits,w0 + and.l #(0x1ff&0xFFFF),w0 + sub.l w0,#9,w0 + call _arch_dspic_irq_clear + + + sub.l [w8],#1,w0 + mov.l w0,[w8] + cp.l w0,#0 + bra nz,.L2 + mov.sl #__kernel+20,w1 + mov.l [w1],w1 + mov.sl #__kernel+8,w0 + mov.l [w0],w0 + cp.l w1,w0 + bra z,.L2 + cp0.b _z_sys_post_kernel + bra z,.L2 + mov.l [--w15], w8 + ulnk + CTXTSWP #0x0 + mov.l w0, [w15++] + mov.l #RAM_END, w0 + mov.l w0, SPLIM + mov.l sr, w0 + and #0xe0, w0 + bra nz, 1f + mov.l [--w15], w0 + ulnk + mov.l w2, [w15++] + mov.l w1, [w15++] + mov.l w0, [w15++] + mov.l #_swap_working_set, w0 + mov.l [--w15], [w0++] + mov.l [--w15], [w0++] + mov.l [--w15], [w0] + mov.l [--w15], w1 + mov.l sr, [w15++] + mov.l w1, [w15++] + mov.l [w0--], w2 + mov.l [w0--], w1 + mov.l [w0], w0 + mov.l w0, [w15++] + 1: + mov.l [--w15], w0 + push RCOUNT + push.l fsr + push.l fcr + mov.l w0, [w15++] + mov.l w1, [w15++] + mov.l w2, [w15++] + mov.l w3, [w15++] + mov.l w4, [w15++] + mov.l w5, [w15++] + mov.l w6, [w15++] + mov.l w7, [w15++] + push.l f0 + push.l f1 + push.l f2 + push.l f3 + push.l f4 + push.l f5 + push.l f6 + push.l f7 + lnk #0x4 + + mov.l #__kernel, w0 + mov.l #___cpu_t_current_OFFSET, w1 + add w0, w1, w1 + mov.l [w1], w2 + mov.l #___thread_t_callee_saved_OFFSET, w1 + add w2, w1, w1 + + mov.l w8, [w1++] + mov.l w9, [w1++] + mov.l w10, [w1++] + mov.l w11, [w1++] + mov.l w12, [w1++] + mov.l w13, [w1++] + mov.l w14, [w1++] + mov.l f8, [w1++] + mov.l f9, [w1++] + mov.l f10, [w1++] + mov.l f11, [w1++] + mov.l f12, [w1++] + mov.l f13, [w1++] + mov.l f14, [w1++] + mov.l f15, [w1++] + mov.l f16, [w1++] + mov.l f17, [w1++] + mov.l f18, [w1++] + mov.l f19, [w1++] + mov.l f20, [w1++] + mov.l f21, [w1++] + mov.l f22, [w1++] + mov.l f23, [w1++] + mov.l f24, [w1++] + mov.l f25, [w1++] + mov.l f26, [w1++] + mov.l f27, [w1++] + mov.l f28, [w1++] + mov.l f29, [w1++] + mov.l f30, [w1++] + mov.l f31, [w1++] + mov.l #RCOUNT, w2 + mov.l [w2], [w1++] + mov.l #CORCON, w2 + mov.l [w2], [w1++] + mov.l #MODCON, w2 + mov.l [w2], [w1++] + mov.l #XMODSRT, w2 + mov.l [w2], [w1++] + mov.l #XMODEND, w2 + mov.l [w2], [w1++] + mov.l #YMODSRT, w2 + mov.l [w2], [w1++] + mov.l #YMODEND, w2 + mov.l [w2], [w1++] + mov.l #XBREV, w2 + mov.l [w2], [w1++] + slac.l A, [W1++] + sac.l A, [W1++] + suac.l A, [W1++] + slac.l B, [W1++] + sac.l B, [W1++] + suac.l B, [W1++] + mov.l w15, [w1++] + mov.l w14, [w1++] + mov.l #SPLIM, w2 + mov.l [w2], [w1++] + + mov.sl #__kernel+20,w0 + mov.l [w0],w0 + mov.sl #__kernel,w1 + mov.l w0,[w1 + ___cpu_t_current_OFFSET] + mov.l [w0 + ___thread_t_tls_OFFSET],w0 + rcall __set_tls + + mov.l #__kernel, w0 + mov.l #___cpu_t_current_OFFSET, w1 + add w0, w1, w1 + mov.l [w1], w2 + mov.l #___thread_t_callee_saved_OFFSET, w1 + add w2, w1, w1 + + mov.l [w1++], w8 + mov.l [w1++], w9 + mov.l [w1++], w10 + mov.l [w1++], w11 + mov.l [w1++], w12 + mov.l [w1++], w13 + mov.l [w1++], w14 + mov.l [w1++], f8 + mov.l [w1++], f9 + mov.l [w1++], f10 + mov.l [w1++], f11 + mov.l [w1++], f12 + mov.l [w1++], f13 + mov.l [w1++], f14 + mov.l [w1++], f15 + mov.l [w1++], f16 + mov.l [w1++], f17 + mov.l [w1++], f18 + mov.l [w1++], f19 + mov.l [w1++], f20 + mov.l [w1++], f21 + mov.l [w1++], f22 + mov.l [w1++], f23 + mov.l [w1++], f24 + mov.l [w1++], f25 + mov.l [w1++], f26 + mov.l [w1++], f27 + mov.l [w1++], f28 + mov.l [w1++], f29 + mov.l [w1++], f30 + mov.l [w1++], f31 + mov.l #RCOUNT, w2 + mov.l [w1++], [w2] + mov.l #CORCON, w2 + mov.l [w1++], [w2] + mov.l #MODCON, w2 + mov.l [w1++], [w2] + mov.l #XMODSRT, w2 + mov.l [w1++], [w2] + mov.l #XMODEND, w2 + mov.l [w1++], [w2] + mov.l #YMODSRT, w2 + mov.l [w1++], [w2] + mov.l #YMODEND, w2 + mov.l [w1++], [w2] + mov.l #XBREV, w2 + mov.l [w1++], [w2] + clr A + clr B + llac.l [w1++], A + lac.l [w1++], A + luac.l [w1++], A + llac.l [w1++], B + lac.l [w1++], B + luac.l [w1++], B + mov.l [w1++], w15 + mov.l [w1++], w14 + mov.l #SPLIM, w2 + mov.l [w1++], [w2] + + ulnk + pop.l f7 + pop.l f6 + pop.l f5 + pop.l f4 + pop.l f3 + pop.l f2 + pop.l f1 + pop.l f0 + mov.l [--w15], w7 + mov.l [--w15], w6 + mov.l [--w15], w5 + mov.l [--w15], w4 + mov.l [--w15], w3 + mov.l [--w15], w2 + mov.l [--w15], w1 + mov.l [--w15], w0 + pop.l fcr + pop.l fsr + pop RCOUNT + mov.l w0, [w15++] + mov.l sr, w0 + and #0xe0, w0 + mov.l [--w15], w0 + bra nz, 1f + mov.l w2, [w15++] + mov.l w1, [w15++] + mov.l w0, [w15++] + mov.l #_swap_working_set, w0 + mov.l [--w15], [w0++] + mov.l [--w15], [w0++] + mov.l [--w15], [w0] + mov.l [--w15], w1 + mov.l [--w15], w2 + mov.l w2, sr + mov.l w1, [w15++] + mov.l [w0--], w2 + mov.l [w0--], w1 + mov.l [w0], w0 + lnk #0x4 + 1: + mov.l w2, [w15++] + mov.l w1, [w15++] + mov.l w0, [w15++] + mov.sl #__kernel, w0 + mov.l [w0 + ___cpu_t_current_OFFSET], w1 + mov.l #___thread_t_arch_OFFSET, w2 + add.l w2, w1, w1 + mov.l [w1 + ___thread_arch_t_swapped_from_thread_OFFSET], w0 + mov.l #0, w2 + cp.l w2, w0 + mov.l [--w15], w0 + bra z, 1f + mov.l [w1 + ___thread_arch_t_swap_return_value_OFFSET], w0 + mov.l w2, [w1 + ___thread_arch_t_swapped_from_thread_OFFSET] + 1: + mov.l [--w15], w1 + mov.l [--w15], w2 + nop + retfie + + + +.L2: + mov.l [--w15], w8 + ulnk +.L1: + retfie + + + .section .text._arch_dspic_irq_clear,code + .align 4 + .global _arch_dspic_irq_clear ; export + .type _arch_dspic_irq_clear,@function +_arch_dspic_irq_clear: + + lnk #0 + lsr.l w0,#5,w1 + sl.l w1,#2,w1 + add.l #IF_OFFSET,w1 + and.l w0,#(0x1f&0x7F),w2 + movs.l #0x1,w0 + sl.l w0,w2,w0 + com.l w0,w0 + and.l w0,[w1],[w1] + ulnk + return diff --git a/arch/dspic/core/isr_wrapper.c b/arch/dspic/core/isr_wrapper.c deleted file mode 100644 index 6a083bc538f2b..0000000000000 --- a/arch/dspic/core/isr_wrapper.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2025, Microchip Technology Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -/* dsPIC33A interrtup exit routine. Will check if a context - * switch is required. If so, z_dspic_do_swap() will be called - * to affect the context switch - */ -static inline __attribute__((always_inline)) void z_dspic_exc_exit(void) -{ -#ifdef CONFIG_PREEMPT_ENABLED - if ((_current_cpu->nested == 0) && (_kernel.ready_q.cache != _current) && - !k_is_pre_kernel()) { - z_dspic_do_swap(); - } - -#endif /* CONFIG_PREEMPT_ENABLED */ -#ifdef CONFIG_STACK_SENTINEL - z_check_stack_sentinel(); -#endif /* CONFIG_STACK_SENTINEL */ - return; -} - -void __attribute__((interrupt)) _isr_wrapper(void) -{ -#ifdef CONFIG_TRACING_ISR - sys_trace_isr_enter(); -#endif /* CONFIG_TRACING_ISR */ - - _current_cpu->nested++; - int32_t irq_number = INTTREGbits.VECNUM - 9; - const struct _isr_table_entry *entry = &_sw_isr_table[irq_number]; - (entry->isr)(entry->arg); - _current_cpu->nested--; - -#ifdef CONFIG_TRACING_ISR - sys_trace_isr_exit(); -#endif /* CONFIG_TRACING_ISR */ - - z_dspic_exc_exit(); -} diff --git a/arch/dspic/core/offsets/offsets.c b/arch/dspic/core/offsets/offsets.c index c88caaf2ce939..08d68715feb95 100644 --- a/arch/dspic/core/offsets/offsets.c +++ b/arch/dspic/core/offsets/offsets.c @@ -7,4 +7,7 @@ #include #include +GEN_OFFSET_SYM(_thread_arch_t, swap_return_value); +GEN_OFFSET_SYM(_thread_arch_t, swapped_from_thread); + GEN_ABS_SYM_END diff --git a/arch/dspic/core/reset0.S b/arch/dspic/core/reset0.S index b0126d5183f2e..2b32c3edb25ae 100644 --- a/arch/dspic/core/reset0.S +++ b/arch/dspic/core/reset0.S @@ -20,6 +20,7 @@ __start: ;; Initialize stack pointer and limit mov.l #__SP_init, w15 ; Stack pointer (W15) mov.l #__SPLIM_init, w14 ; Stack limit (W14) + mov.l w14, _SPLIM ;; Data initialization mov.l #__dinit_tbloffset, w0 diff --git a/arch/dspic/core/swap.c b/arch/dspic/core/swap.c index 32f329c76df33..49be36e8c28b7 100644 --- a/arch/dspic/core/swap.c +++ b/arch/dspic/core/swap.c @@ -11,15 +11,20 @@ #include #include "kswap.h" +int swap_working_set[NUM_TEMP_REGS]; + int arch_swap(unsigned int key) { #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING z_thread_mark_switched_out(); #endif + register int result __asm__("w0"); /* store off key and return value */ _current->arch.cpu_level = key; _current->arch.swap_return_value = -EAGAIN; + _current->arch.swapped_from_thread = 1; + result = _current->arch.swap_return_value; /*Check if swap is needed*/ if (_kernel.ready_q.cache != _current) { @@ -37,8 +42,17 @@ int arch_swap(unsigned int key) * Make sure the return value is not being intrepreted * wrongly */ - irq_unlock(key); - register int result __asm__("w0"); + __asm__ volatile( + "mov.l w1, [w15++]\n\t" + "mov.l w2, [w15++]\n\t" + ); + _current->arch.swapped_from_thread = 0; + result = _current->arch.swap_return_value; + irq_unlock(_current->arch.cpu_level); + __asm__ volatile( + "mov.l [--w15], w2\n\t" + "mov.l [--w15], w1\n\t" + ); return result; /* Context switch is performed here. Returning implies the diff --git a/arch/dspic/core/thread.c b/arch/dspic/core/thread.c index 2ab6d2861b5d1..3fc48320be7ea 100644 --- a/arch/dspic/core/thread.c +++ b/arch/dspic/core/thread.c @@ -4,9 +4,9 @@ */ #include +#include #include -#define RAM_END 0x00007FFC #define DSPIC_STATUS_DEFAULT 0 void z_thread_entry(k_thread_entry_t thread, void *arg1, void *arg2, void *arg3); @@ -23,7 +23,13 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *sta /* Setting all register to zero*/ (void)memset(init_frame, 0, sizeof(struct arch_esf)); - /* Setup initial stack frame*/ + /* Setup initial stack frame + * During the initial thread entry the w0 serves the function of thread + * entry function pointer, but the general usage of w0 as per the C ABI + * is to pass back the return data. Here set return value as entry pointer + * value + */ + arch_thread_return_value_set(thread, (unsigned int)entry); init_frame->W0 = (uint32_t)entry; init_frame->W1 = (uint32_t)(void *)p1; init_frame->W2 = (uint32_t)(void *)p2; @@ -51,6 +57,13 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *sta */ thread->callee_saved.stack = (uint32_t)(void *)init_frame + (sizeof(struct arch_esf)); thread->callee_saved.frame = (uint32_t)thread->callee_saved.stack; - /*TODO: Need to handle splim properly*/ - thread->callee_saved.splim = RAM_END; + thread->callee_saved.splim = (uint32_t)(thread->stack_info.start + thread->stack_info.size); + /*Set the initial key for irq unlock*/ + thread->arch.cpu_level = 1; +} + +int arch_coprocessors_disable(struct k_thread *thread) +{ + (void)thread; + return -ENOTSUP; } diff --git a/arch/dspic/include/kernel_arch_func.h b/arch/dspic/include/kernel_arch_func.h index 28bcd17a875ce..b1b4a38bd1af2 100644 --- a/arch/dspic/include/kernel_arch_func.h +++ b/arch/dspic/include/kernel_arch_func.h @@ -24,7 +24,11 @@ #ifdef __cplusplus extern "C" { #endif - +#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) +#define IFS_COUNT 12 +#elif defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106) +#define IFS_COUNT 9 +#endif extern uint32_t vector_start; /* dsPIC33A interrupt functionality initialization */ @@ -34,15 +38,8 @@ static ALWAYS_INLINE void z_dspic_interrupt_init(void) * clear all the interrupts, set the interrupt flag status * registers to zero. */ - IFS0 = 0x0; - IFS1 = 0x0; - IFS2 = 0x0; - IFS3 = 0x0; - IFS4 = 0x0; - IFS5 = 0x0; - IFS6 = 0x0; - IFS7 = 0x0; - IFS8 = 0x0; + volatile uint32_t *int_enable_reg = (uint32_t *)DT_PROP(DT_NODELABEL(intc0), if_offset); + (void)memset((void *)int_enable_reg, 0, (unsigned long)IFS_COUNT * sizeof(int)); /* enable nested interrupts */ INTCON1bits.NSTDIS = 0; /* enable global interrupts */ @@ -82,8 +79,7 @@ static ALWAYS_INLINE void arch_kernel_init(void) static ALWAYS_INLINE void arch_thread_return_value_set(struct k_thread *thread, unsigned int value) { - (void)thread; - (void)value; + thread->arch.swap_return_value = value; } int arch_swap(unsigned int key); diff --git a/arch/dspic/include/kernel_arch_swap.h b/arch/dspic/include/kernel_arch_swap.h index cd2a1953297e9..8a44a4e7e28e2 100644 --- a/arch/dspic/include/kernel_arch_swap.h +++ b/arch/dspic/include/kernel_arch_swap.h @@ -20,6 +20,7 @@ #include #include #include +#include #include #ifdef __cplusplus @@ -28,12 +29,24 @@ extern "C" { #include "kswap.h" +#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) +#define RAM_END "0x00013FFC" +#elif defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106) +#define RAM_END "0x00007FFC" +#endif + + +#define NUM_TEMP_REGS 3 +extern int swap_working_set[NUM_TEMP_REGS]; + static inline __attribute__((always_inline)) void z_dspic_save_context(void) { /*Adjust stack for co-operative swap*/ __asm__ volatile( /*Check if in interrupt context*/ "mov.l w0, [w15++]\n\t" + "mov.l #"RAM_END", w0\n\t" + "mov.l w0, SPLIM\n\t" "mov.l sr, w0\n\t" "and #0xe0, w0\n\t" "bra nz, 1f\n\t" @@ -42,6 +55,25 @@ static inline __attribute__((always_inline)) void z_dspic_save_context(void) "mov.l [--w15], w0\n\t" /*This unlink is needed to match esf*/ "ulnk\n\t" + /*Backup the working reg W0-W2*/ + "mov.l w2, [w15++]\n\t" + "mov.l w1, [w15++]\n\t" + "mov.l w0, [w15++]\n\t" + "mov.l #_swap_working_set, w0\n\t" + "mov.l [--w15], [w0++]\n\t" + "mov.l [--w15], [w0++]\n\t" + "mov.l [--w15], [w0]\n\t" + /*Format SR and LR as its from interrupt*/ + "mov.l [--w15], w1\n\t" + "mov.l sr, [w15++]\n\t" + "mov.l w1, [w15++]\n\t" + "mov.l [w0--], w2\n\t" + "mov.l [w0--], w1\n\t" + "mov.l [w0], w0\n\t" + "mov.l w0, [w15++]\n\t" + + "1:\n\t" + "mov.l [--w15], w0\n\t" "push RCOUNT\n\t" "push.l fsr\n\t" "push.l fcr\n\t" @@ -53,7 +85,6 @@ static inline __attribute__((always_inline)) void z_dspic_save_context(void) "mov.l w5, [w15++]\n\t" "mov.l w6, [w15++]\n\t" "mov.l w7, [w15++]\n\t" - "mov.l w8, [w15++]\n\t" "push.l f0\n\t" "push.l f1\n\t" "push.l f2\n\t" @@ -62,24 +93,16 @@ static inline __attribute__((always_inline)) void z_dspic_save_context(void) "push.l f5\n\t" "push.l f6\n\t" "push.l f7\n\t" - "lnk #0x0\n\t" - /*in isr lnk is done after esf push*/ - "mov.l w0, [w15++]\n\t" - - /*In interrupt context*/ - "1:\n\t" - "mov.l [--w15], w0\n\t"); + "lnk #0x4\n\t"); + /*in isr lnk is done after esf push*/ /* Get the current thread callee_saved context - * TODO: - * Need to change constant 0x8, 0x28 with offset symbols - * ___cpu_t_current_OFFSET, ___thread_t_callee_saved_OFFSET */ __asm__ volatile("mov.l #__kernel, w0\n\t" - "mov.l #0x8, w1\n\t" + "mov.l #___cpu_t_current_OFFSET, w1\n\t" "add w0, w1, w1\n\t" "mov.l [w1], w2\n\t" - "mov.l #0x28, w1\n\t" + "mov.l #___thread_t_callee_saved_OFFSET, w1\n\t" "add w2, w1, w1\n\t"); /*Save all callee saved registers*/ @@ -133,8 +156,6 @@ static inline __attribute__((always_inline)) void z_dspic_save_context(void) "mov.l #XBREV, w2\n\t" "mov.l [w2], [w1++]\n\t" - "clr A\n\t" - "clr B\n\t" "slac.l A, [W1++]\n\t" "sac.l A, [W1++]\n\t" "suac.l A, [W1++]\n\t" @@ -151,15 +172,12 @@ static inline __attribute__((always_inline)) void z_dspic_save_context(void) static inline __attribute__((always_inline)) void z_dspic_restore_context(void) { /* Get the current thread callee_saved context - * TODO: - * Need to change constant 0x8, 0x28 with offset symbols - * ___cpu_t_current_OFFSET, ___thread_t_callee_saved_OFFSET */ __asm__ volatile("mov.l #__kernel, w0\n\t" - "mov.l #0x8, w1\n\t" + "mov.l #___cpu_t_current_OFFSET, w1\n\t" "add w0, w1, w1\n\t" "mov.l [w1], w2\n\t" - "mov.l #0x28, w1\n\t" + "mov.l #___thread_t_callee_saved_OFFSET, w1\n\t" "add w2, w1, w1\n\t"); /*Restore all registers*/ @@ -215,12 +233,12 @@ static inline __attribute__((always_inline)) void z_dspic_restore_context(void) "clr A\n\t" "clr B\n\t" - "slac.l A, [W1++]\n\t" - "sac.l A, [W1++]\n\t" - "suac.l A, [W1++]\n\t" - "slac.l B, [W1++]\n\t" - "sac.l B, [W1++]\n\t" - "suac.l B, [W1++]\n\t" + "llac.l [w1++], A\n\t" + "lac.l [w1++], A\n\t" + "luac.l [w1++], A\n\t" + "llac.l [w1++], B\n\t" + "lac.l [w1++], B\n\t" + "luac.l [w1++], B\n\t" "mov.l [w1++], w15\n\t" "mov.l [w1++], w14\n\t" @@ -229,15 +247,6 @@ static inline __attribute__((always_inline)) void z_dspic_restore_context(void) /*pop exception/swap saved stack frame*/ __asm__ volatile( - /* Check context and only pop the - * esf if in thread context - */ - "mov.l w0, [w15++]\n\t" - "mov.l sr, w0\n\t" - "and #0xe0, w0\n\t" - "mov.l [--w15], w0\n\t" - "bra nz, 1f\n\t" - /*in isr the unlink is done before esf pop*/ "ulnk\n\t" /*Thread context*/ @@ -249,7 +258,6 @@ static inline __attribute__((always_inline)) void z_dspic_restore_context(void) "pop.l f2\n\t" "pop.l f1\n\t" "pop.l f0\n\t" - "mov.l [--w15], w8\n\t" "mov.l [--w15], w7\n\t" "mov.l [--w15], w6\n\t" "mov.l [--w15], w5\n\t" @@ -261,7 +269,34 @@ static inline __attribute__((always_inline)) void z_dspic_restore_context(void) "pop.l fcr\n\t" "pop.l fsr\n\t" "pop RCOUNT\n\t" - "lnk #0x0\n\t" + + /* Check context and only pop the + * esf if in thread context + */ + "mov.l w0, [w15++]\n\t" + "mov.l sr, w0\n\t" + "and #0xe0, w0\n\t" + "mov.l [--w15], w0\n\t" + "bra nz, 1f\n\t" + + /*Backup the working reg W0-W2*/ + "mov.l w2, [w15++]\n\t" + "mov.l w1, [w15++]\n\t" + "mov.l w0, [w15++]\n\t" + "mov.l #_swap_working_set, w0\n\t" + "mov.l [--w15], [w0++]\n\t" + "mov.l [--w15], [w0++]\n\t" + "mov.l [--w15], [w0]\n\t" + /*Format SR and LR as its from interrupt*/ + "mov.l [--w15], w1\n\t" + "mov.l [--w15], w2\n\t" + "mov.l w2, sr\n\t" + "mov.l w1, [w15++]\n\t" + "mov.l [w0--], w2\n\t" + "mov.l [w0--], w1\n\t" + "mov.l [w0], w0\n\t" + + "lnk #0x4\n\t" /*Interrupt context*/ "1:\n\t" @@ -271,11 +306,28 @@ static inline __attribute__((always_inline)) void z_dspic_restore_context(void) /* routine which swaps the context. Needs to be written in assembly */ static inline __attribute__((always_inline)) void z_dspic_do_swap(void) { + /* Switch to context 0 before starting context save and restore + * This Arch has 7 context and each has banked register sets for w0-w8 + * So in interrupt we are in ctx 1 and need to go to ctx 0 for tasks + */ + __asm__ volatile("CTXTSWP #0x0"); + z_dspic_save_context(); /*Switch to next task in queue*/ z_current_thread_set(_kernel.ready_q.cache); + /* It is expected to save current thread's pointer on z_tls_current + * variable because k_current_get() call will get the current thread's + * pointer from this variable if the CONFIG_CURRENT_THREAD_USE_TLS + * is enabled. In ztest k_thread_abort() was trying to abort the + * current thread. + */ +#ifdef CONFIG_CURRENT_THREAD_USE_TLS + /* Thread-local cache of current thread ID, set in z_thread_entry() */ + _set_tls((void *)_current->tls); +#endif + z_dspic_restore_context(); } diff --git a/boards/microchip/dspic33/dspic33a_curiosity/Kconfig.dspic33a_curiosity b/boards/microchip/dspic33/dspic33a_curiosity/Kconfig.dspic33a_curiosity index f0e2ba4c20ae4..2fe2d582a1f38 100644 --- a/boards/microchip/dspic33/dspic33a_curiosity/Kconfig.dspic33a_curiosity +++ b/boards/microchip/dspic33/dspic33a_curiosity/Kconfig.dspic33a_curiosity @@ -2,4 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_DSPIC33A_CURIOSITY + select SOC_P33AK512MPS512 if BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512 select SOC_P33AK128MC106 if BOARD_DSPIC33A_CURIOSITY_P33AK128MC106 diff --git a/boards/microchip/dspic33/dspic33a_curiosity/board.cmake b/boards/microchip/dspic33/dspic33a_curiosity/board.cmake index 2138e0440d0bd..fcf825924f8a1 100644 --- a/boards/microchip/dspic33/dspic33a_curiosity/board.cmake +++ b/boards/microchip/dspic33/dspic33a_curiosity/board.cmake @@ -11,6 +11,11 @@ if(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106) board_runner_args(ipecmd "--device=33AK128MC106" "--flash-tool=PKOB4") endif() +if(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) + message(STATUS "device selected") + board_runner_args(ipecmd "--device=33AK512MPS512" "--flash-tool=PKOB4") +endif() + board_finalize_runner_args(ipecmd) set_property(GLOBAL PROPERTY BOARD_SUPPORTS_DEBUGGER TRUE) diff --git a/boards/microchip/dspic33/dspic33a_curiosity/board.yml b/boards/microchip/dspic33/dspic33a_curiosity/board.yml index 561db73fdf4a9..412a13838177c 100644 --- a/boards/microchip/dspic33/dspic33a_curiosity/board.yml +++ b/boards/microchip/dspic33/dspic33a_curiosity/board.yml @@ -5,3 +5,4 @@ board: socs: - name: p33ak128mc106 - name: p33ak256mc506 + - name: p33ak512mps512 diff --git a/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106.dts b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106.dts index 1ae8e10b0a118..ff347435c1628 100644 --- a/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106.dts +++ b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "p33ak128mc106.dtsi" +#include / { model = "Microchip dsPIC33A Curiosity Platform Development Board"; @@ -13,12 +14,62 @@ chosen { zephyr,flash = &flash0; zephyr,sram = &sram0; - zephyr,serial = &uart1; - zephyr,console = &uart1; + zephyr,serial = &uart0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + uart,passthrough = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 3 GPIO_ACTIVE_LOW>; + label = "P28 LED0"; + }; + led1: led_1 { + gpios = <&gpioc 4 GPIO_ACTIVE_LOW>; + label = "P30 LED1"; + }; + led2: led_2 { + gpios = <&gpioc 5 GPIO_ACTIVE_LOW>; + label = "P32 LED2"; + }; + led3: led_3 { + gpios = <&gpioc 6 GPIO_ACTIVE_LOW>; + label = "P34 LED3"; + }; + led4: led_4 { + gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; + label = "P36 LED4"; + }; + led5: led_5 { + gpios = <&gpioc 8 GPIO_ACTIVE_LOW>; + label = "P50 LED5"; + }; + led6: led_6 { + gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; + label = "P52 LED6"; + }; + led7: led_7 { + gpios = <&gpioc 10 GPIO_ACTIVE_LOW>; + label = "P54 LED7"; + }; }; aliases { - uart-0 = &uart1; + uart-0 = &uart0; + uart-1 = &uart1; + uart-2 = &uart2; + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + led4 = &led4; + led5 = &led5; + led6 = &led6; + led7 = &led7; + }; }; @@ -33,6 +84,14 @@ status = "okay"; }; +&uart0 { + status = "okay"; +}; + &uart1 { status = "okay"; }; + +&uart2 { + status = "okay"; +}; diff --git a/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106.yaml b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106.yaml index 153574ec0de35..f42e7658c50e5 100644 --- a/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106.yaml +++ b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106.yaml @@ -9,6 +9,7 @@ flash: 128 supported: - uart - timer + - gpio testing: default: true vendor: microchip diff --git a/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106_defconfig b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106_defconfig index cbfee96cec289..7569aed1abf86 100644 --- a/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106_defconfig +++ b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak128mc106_defconfig @@ -6,6 +6,7 @@ CONFIG_LOG_MODE_MINIMAL=y CONFIG_PRINTK=y CONFIG_CONSOLE=y CONFIG_STDOUT_CONSOLE=n +CONFIG_UART_INTERRUPT_DRIVEN=y # For LOG_MODE_MINIMAL using UART CONFIG_UART_CONSOLE=y @@ -21,13 +22,13 @@ CONFIG_SERIAL=y # CONFIG_SERIAL=y # Enables support for GPIO drivers on the target platform. -# CONFIG_GPIO=y +CONFIG_GPIO=y # Defines the system hardware clock frequency as 8 MHz. CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 # Configures the system tick rate to 1000 ticks per second (1 ms tick interval). -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=10000 # Specifies a single-core configuration for the SoC. CONFIG_MP_MAX_NUM_CPUS=1 @@ -36,3 +37,5 @@ CONFIG_MP_MAX_NUM_CPUS=1 # because of an extra prepended underscore on symbols generated, # For this reason keeping it disabled CONFIG_CHECK_INIT_PRIORITIES=n + +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak512mps512.dts b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak512mps512.dts new file mode 100644 index 0000000000000..143b68997098b --- /dev/null +++ b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak512mps512.dts @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "p33ak512mps512.dtsi" +#include + +/ { + model = "Microchip dsPIC33A Curiosity Platform Development Board"; + compatible = "microchip,dspic33a-criosity-p33ak512mps512"; + + chosen { + zephyr,flash = &flash0; + zephyr,sram = &sram0; + zephyr,serial = &uart0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + uart,passthrough = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 8 GPIO_ACTIVE_LOW>; + label = "P28 LED0"; + }; + led1: led_1 { + gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; + label = "P30 LED1"; + }; + led2: led_2 { + gpios = <&gpioc 10 GPIO_ACTIVE_LOW>; + label = "P32 LED2"; + }; + led3: led_3 { + gpios = <&gpioc 11 GPIO_ACTIVE_LOW>; + label = "P34 LED3"; + }; + led4: led_4 { + gpios = <&gpioc 12 GPIO_ACTIVE_LOW>; + label = "P36 LED4"; + }; + led5: led_5 { + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + label = "P50 LED5"; + }; + led6: led_6 { + gpios = <&gpioc 14 GPIO_ACTIVE_LOW>; + label = "P52 LED6"; + }; + led7: led_7 { + gpios = <&gpioc 15 GPIO_ACTIVE_LOW>; + label = "P54 LED7"; + }; + }; + + aliases { + uart-0 = &uart0; + uart-1 = &uart1; + uart-2 = &uart2; + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + led4 = &led4; + led5 = &led5; + led6 = &led6; + led7 = &led7; + }; +}; + +&cpu0 { + clock-frequency = <8000000>; + status = "okay"; + cpu-power-states = <&idle>; +}; + +&timer1 { + clock-frequency = <8000000>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak512mps512.yaml b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak512mps512.yaml new file mode 100644 index 0000000000000..b74779f1a2cff --- /dev/null +++ b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak512mps512.yaml @@ -0,0 +1,15 @@ +identifier: dspic33a_curiosity/p33ak512mps512 +name: EV74H48A EVB DSPIC33AK512MPS512 +type: mcu +arch: dspic +toolchain: + - xcdsc +ram: 64 +flash: 512 +supported: + - uart + - timer + - gpio +testing: + default: true +vendor: microchip diff --git a/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak512mps512_defconfig b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak512mps512_defconfig new file mode 100644 index 0000000000000..7569aed1abf86 --- /dev/null +++ b/boards/microchip/dspic33/dspic33a_curiosity/dspic33a_curiosity_p33ak512mps512_defconfig @@ -0,0 +1,41 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_LOG=y +CONFIG_LOG_MODE_MINIMAL=y +CONFIG_PRINTK=y +CONFIG_CONSOLE=y +CONFIG_STDOUT_CONSOLE=n +CONFIG_UART_INTERRUPT_DRIVEN=y + +# For LOG_MODE_MINIMAL using UART +CONFIG_UART_CONSOLE=y +CONFIG_LOG_PRINTK=n +CONFIG_EARLY_CONSOLE=y +CONFIG_SERIAL=y + +# for LOG_MODE_IMMEDIATE using UART +# Uncomment below if using LOG_MODE_IMMEDIATE instead +# CONFIG_UART_CONSOLE=y +# CONFIG_LOG_ALWAYS_RUNTIME=y +# CONFIG_EARLY_CONSOLE=y +# CONFIG_SERIAL=y + +# Enables support for GPIO drivers on the target platform. +CONFIG_GPIO=y + +# Defines the system hardware clock frequency as 8 MHz. +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 + +# Configures the system tick rate to 1000 ticks per second (1 ms tick interval). +CONFIG_SYS_CLOCK_TICKS_PER_SEC=10000 + +# Specifies a single-core configuration for the SoC. +CONFIG_MP_MAX_NUM_CPUS=1 + +# For XC-DSC toolchain the default check init script of zephyr will fail +# because of an extra prepended underscore on symbols generated, +# For this reason keeping it disabled +CONFIG_CHECK_INIT_PRIORITIES=n + +CONFIG_HW_STACK_PROTECTION=y diff --git a/cmake/bintools/xcdsc/target.cmake b/cmake/bintools/xcdsc/target.cmake index 70f4029a1408e..778666990f044 100644 --- a/cmake/bintools/xcdsc/target.cmake +++ b/cmake/bintools/xcdsc/target.cmake @@ -4,7 +4,7 @@ find_program(CMAKE_OBJDUMP NAMES ${XCDSC_BIN_PREFIX}objdump PATHS ${TOOLCHAIN_HO find_program(CMAKE_READELF NAMES ${XCDSC_BIN_PREFIX}readelf PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) find_program(CMAKE_STRIP NAMES ${XCDSC_BIN_PREFIX}strip PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) # Archive Rules Setup -SET(CMAKE_C_ARCHIVE_CREATE " -q ") -SET(CMAKE_C_ARCHIVE_FINISH " -q ") +SET(CMAKE_C_ARCHIVE_CREATE " -q -mdfp=\"${DFP_ROOT}/xc16\"") +SET(CMAKE_C_ARCHIVE_FINISH " -q -mdfp=\"${DFP_ROOT}/xc16\"") # Include bin tool properties include(${ZEPHYR_BASE}/cmake/bintools/xcdsc/target_bintools.cmake) diff --git a/cmake/bintools/xcdsc/target_bintools.cmake b/cmake/bintools/xcdsc/target_bintools.cmake index c1f4ac2047fb7..956e8c3737de8 100644 --- a/cmake/bintools/xcdsc/target_bintools.cmake +++ b/cmake/bintools/xcdsc/target_bintools.cmake @@ -1,5 +1,5 @@ # Usage of the objcopy utility (aliased as elfconvert) for converting ELF binaries into other formats,such as hex, binary, etc. -set_property(TARGET bintools PROPERTY elfconvert_command ${CMAKE_OBJCOPY}) +set_property(TARGET bintools PROPERTY elfconvert_command ${CMAKE_OBJCOPY} -mdfp="${DFP_ROOT}/xc16") # List of format the tool supports for converting, for example, # GNU tools uses objectcopy, which supports the following: ihex, srec, binary set_property(TARGET bintools PROPERTY elfconvert_formats ihex srec binary) diff --git a/cmake/compiler/xcdsc/compiler_flags.cmake b/cmake/compiler/xcdsc/compiler_flags.cmake index 976a396460632..52475bc591880 100644 --- a/cmake/compiler/xcdsc/compiler_flags.cmake +++ b/cmake/compiler/xcdsc/compiler_flags.cmake @@ -19,10 +19,13 @@ set_compiler_property(PROPERTY linker_script -Wl,-T) set_compiler_property(PROPERTY save_temps -save-temps=obj) # Smart I/O conversion for format strings (safe printf optimizations) list(APPEND TOOLCHAIN_C_FLAGS -msmart-io=1) + # Disable SFR access warnings list(APPEND TOOLCHAIN_C_FLAGS -msfr-warn=off) # Disable instruction scheduling (for stability) list(APPEND TOOLCHAIN_C_FLAGS -fno-schedule-insns -fno-schedule-insns2) list(APPEND TOOLCHAIN_C_FLAGS -fno-omit-frame-pointer) +# list(APPEND TOOLCHAIN_C_FLAGS -mdfp="${DFP_ROOT}/xc16") +# list(APPEND TOOLCHAIN_ASM_FLAGS -mdfp="${DFP_ROOT}/xc16") # assembler compiler flags for imacros. The specific header must be appended by user. -set_property(TARGET asm PROPERTY imacros -imacros) \ No newline at end of file +set_property(TARGET asm PROPERTY imacros -imacros) diff --git a/cmake/compiler/xcdsc/generic.cmake b/cmake/compiler/xcdsc/generic.cmake index 7b5dd556de348..043f88a5fd6bd 100644 --- a/cmake/compiler/xcdsc/generic.cmake +++ b/cmake/compiler/xcdsc/generic.cmake @@ -1,8 +1,198 @@ set(CMAKE_SYSTEM_NAME Generic) set(CMAKE_SYSTEM_PROCESSOR ${ARCH}) +# Find Microchip dsPIC33 DFP (MC/MP) for specified architectures by locating c30_device.info, +# preferring HOME packs over system installs, and extracting a clean DFP root +# (.../dsPIC33XX-YY_DFP/), regardless of deeper subfolders (e.g., xc16/bin/...). +# +# Usage: +# find_dspic33_dfp( +# OUT_INFO # output: full path to c30_device.info +# OUT_ROOT # output: DFP root (.../dsPIC33XX-YY_DFP/) +# [ARCHES ...] # default: AK CD CH +# [FAMILIES ...] # default: MC MP +# [ROOTS ...] # optional; HOME is always searched first +# [HINT_VERSION ] # optional preferred version (e.g., 1.1.109) +# ) +function(find_dspic33_dfp) + set(options) + set(oneValueArgs OUT_INFO OUT_ROOT HINT_VERSION) + set(multiValueArgs ARCHES FAMILIES ROOTS) + cmake_parse_arguments(FD "${options}" "${oneValueArgs}" "${multiValueArgs}" ${ARGN}) + + if(NOT FD_OUT_INFO OR NOT FD_OUT_ROOT) + message(FATAL_ERROR "find_dspic33_dfp: You must pass OUT_INFO and OUT_ROOT variable names.") + endif() + + # --- Defaults --- + if(NOT FD_ARCHES) + set(FD_ARCHES AK CD CH) + endif() + if(NOT FD_FAMILIES) + set(FD_FAMILIES MC MP) + endif() + + # Home path (works on Win/Linux) + set(_home "$ENV{HOME}") + if(WIN32 AND NOT _home) + set(_home "$ENV{USERPROFILE}") + file(TO_CMAKE_PATH "${_home}" _home) + endif() + + # Root search list: HOME first (highest priority), then system roots + set(_default_roots + "${_home}/.mchp_packs" + "/opt/microchip" "/opt/microchip/mplabx" + "C:/Program Files/Microchip" "C:/Program Files (x86)/Microchip" + ) + set(_search_roots "${_default_roots}") + if(FD_ROOTS) + # If caller passes ROOTS, append them after HOME so HOME still wins by default + list(APPEND _search_roots ${FD_ROOTS}) + endif() + + # Build case-insensitive regex for pack dir: dspic33[-_]_dfp + set(_alts "") + foreach(_a IN LISTS FD_ARCHES) + string(TOLOWER "${_a}" _al) + foreach(_f IN LISTS FD_FAMILIES) + string(TOLOWER "${_f}" _fl) + list(APPEND _alts "dspic33${_al}[-_]${_fl}_dfp") + endforeach() + endforeach() + string(REPLACE ";" "|" _alts_regex "${_alts}") + set(_pack_regex "(${_alts_regex})") + + # Collect candidates, tagging each with a priority rank (0 = HOME, 1 = system/others) + # We'll sort by (rank ASC, version/path NATURAL DESC) + set(_ranked_candidates) # entries like: "0|/full/path/to/c30_device.info" + foreach(_root IN LISTS _search_roots) + if(NOT _root OR NOT EXISTS "${_root}") + continue() + endif() + # Determine rank: 0 for home packs, 1 otherwise + set(_rank 1) + if(_root MATCHES "^${_home}(/|\\\\)\\.mchp_packs") + set(_rank 0) + endif() + + file(GLOB_RECURSE _found "${_root}/**/c30_device.info") + foreach(_p IN LISTS _found) + string(TOLOWER "${_p}" _pl) + if(_pl MATCHES "${_pack_regex}") + list(APPEND _ranked_candidates "${_rank}|${_p}") + endif() + endforeach() + endforeach() + + if(NOT _ranked_candidates) + message(FATAL_ERROR + "find_dspic33_dfp: No c30_device.info found for architectures {${FD_ARCHES}} " + "and families {${FD_FAMILIES}} under roots: ${_search_roots}") + endif() + + # Optional: version hint filter + if(FD_HINT_VERSION) + set(_hinted) + foreach(_rp IN LISTS _ranked_candidates) + string(REPLACE "|" ";" _parts "${_rp}") + list(GET _parts 1 _path) + if(_path MATCHES "/${FD_HINT_VERSION}(/|\\\\)") + list(APPEND _hinted "${_rp}") + endif() + endforeach() + if(_hinted) + set(_ranked_candidates "${_hinted}") + endif() + endif() + + # ---- Prefer rank 0; else fall back to rank 1 (Windows-safe) ---- + # Split into path-only buckets first + set(_r0_paths) + set(_r1_paths) + foreach(_entry IN LISTS _ranked_candidates) + string(REPLACE "|" ";" _parts "${_entry}") + list(GET _parts 0 _rk) + list(GET _parts 1 _pth) + if(_rk EQUAL 0) + list(APPEND _r0_paths "${_pth}") + else() + list(APPEND _r1_paths "${_pth}") + endif() + endforeach() + + # Sort each bucket naturally (DESC → newest-looking first) and pick + if(_r0_paths) + list(SORT _r0_paths COMPARE NATURAL ORDER DESCENDING) + list(GET _r0_paths 0 _best_path) + elseif(_r1_paths) + list(SORT _r1_paths COMPARE NATURAL ORDER DESCENDING) + list(GET _r1_paths 0 _best_path) + else() + message(FATAL_ERROR "find_dspic33_dfp: No ranked candidates after filtering.") + endif() + + # --- DFP root extraction --- + # Find "...///" inside the path and cut there. + string(TOLOWER "${_best_path}" _best_lc) + string(REGEX MATCH "(.*[/\\\\](dspic33[a-z0-9]+[-_][a-z0-9]+_dfp)[/\\\\]([^/\\\\]+))" _m "${_best_lc}") + if(_m) + string(REGEX REPLACE "^(.*[/\\\\](dspic33[a-z0-9]+[-_][a-z0-9]+_dfp)[/\\\\]([^/\\\\]+)).*$" "\\1" _dfp_root_lc "${_best_lc}") + string(LENGTH "${_dfp_root_lc}" _keep_len) + string(SUBSTRING "${_best_path}" 0 ${_keep_len} DFP_ROOT) + else() + # Fallback: strip known tails to version dir + set(_tmp "${_best_path}") + string(REGEX REPLACE "([/\\\\])xc16([/\\\\].*)?$" "" _tmp "${_tmp}") + string(REGEX REPLACE "([/\\\\])c30_device.info$" "" _tmp "${_tmp}") + set(DFP_ROOT "${_tmp}") + endif() + + # --- OUT_INFO should be the DIRECTORY containing c30_device.info (e.g., .../xc16/bin) --- + get_filename_component(_info_dir "${_best_path}" DIRECTORY) + + # Outputs + set(${FD_OUT_INFO} "${_info_dir}" PARENT_SCOPE) # directory only, no filename + set(${FD_OUT_ROOT} "${DFP_ROOT}" PARENT_SCOPE) +endfunction() + +if ("${BOARD_QUALIFIERS}" MATCHES "/p33ak128mc106" AND + "${BOARD}" MATCHES "dspic33a_curiosity") + set(TARGET_CPU "33AK128MC106") + find_dspic33_dfp( + OUT_INFO C30_DEVICE_INFO + OUT_ROOT DFP_ROOT + ARCHES AK + FAMILIES MC + ) +elseif("${BOARD_QUALIFIERS}" MATCHES "/p33ak512mps512" AND + "${BOARD}" MATCHES "dspic33a_curiosity") + set(TARGET_CPU "33AK512MPS512") + find_dspic33_dfp( + OUT_INFO C30_DEVICE_INFO + OUT_ROOT DFP_ROOT + ARCHES AK + FAMILIES MP + ) +endif() +message(STATUS "DFP file in ${C30_DEVICE_INFO}") +message(STATUS "DFP path ${DFP_ROOT}") + +set(ENV{C30_DEVICE_INFO} "${C30_DEVICE_INFO}") +set(ENV{DFP_ROOT} "${DFP_ROOT}") +set(ENV{TARGET_CPU} "${TARGET_CPU}") + +set(CMAKE_C_FLAGS "-D__XC_DSC__ -mdfp=\"${DFP_ROOT}/xc16\"" CACHE STRING "" FORCE) +set(CMAKE_ASM_FLAGS "-mdfp=\"${DFP_ROOT}/xc16\"" CACHE STRING "" FORCE) + +# Append to DTS preprocessor flags with DFP path +if(DEFINED DTS_EXTRA_CPPFLAGS AND NOT "${DTS_EXTRA_CPPFLAGS}" STREQUAL "") + list(APPEND DTS_EXTRA_CPPFLAGS "-mdfp=\"${DFP_ROOT}/xc16\"") +else() + set(DTS_EXTRA_CPPFLAGS "-mdfp=\"${DFP_ROOT}/xc16\"") +endif() # Find and validate the xc-dsc-gcc compiler binary find_program(CMAKE_C_COMPILER xc-dsc-gcc PATHS ${XCDSC_TOOLCHAIN_PATH}/bin/ NO_DEFAULT_PATH REQUIRED ) -set(CMAKE_C_FLAGS -D__XC_DSC__) + # Get compiler version execute_process( COMMAND ${CMAKE_C_COMPILER} --version diff --git a/cmake/compiler/xcdsc/target.cmake b/cmake/compiler/xcdsc/target.cmake index fbc7abedbaf9e..01921b9d22591 100644 --- a/cmake/compiler/xcdsc/target.cmake +++ b/cmake/compiler/xcdsc/target.cmake @@ -5,8 +5,7 @@ find_program(CMAKE_CXX_COMPILER xc-dsc-gcc PATHS ${XCDSC_TOOLCHAIN_PATH}/bin/ NO # Set assembler explicitly find_program(CMAKE_ASM_COMPILER xc-dsc-gcc PATHS ${XCDSC_TOOLCHAIN_PATH}/bin/ NO_DEFAULT_PATH ) # Target CPU (must match user platform) -set(TARGET_CPU "33AK128MC106") -list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${TARGET_CPU}) +list(APPEND TOOLCHAIN_C_FLAGS "-mcpu=${TARGET_CPU}") # Picolibc and standard includes(if supported in toolchain) list(APPEND TOOLCHAIN_C_FLAGS -I${XCDSC_TOOLCHAIN_PATH}/include/picolibc diff --git a/cmake/linker/xcdsc/linker_flags.cmake b/cmake/linker/xcdsc/linker_flags.cmake index cb99a4775b360..a3af58c352cc0 100644 --- a/cmake/linker/xcdsc/linker_flags.cmake +++ b/cmake/linker/xcdsc/linker_flags.cmake @@ -1,29 +1,31 @@ # The fundamental linker flags always applied to every Zephyr build for XC-DSC check_set_linker_property( - TARGET linker PROPERTY base ${LINKERFLAGPREFIX},--check-sections - # Check to not check section addresses for overlaps. - ${LINKERFLAGPREFIX},--data-init - # initialize all data sections.Check to support initialized data. - ${LINKERFLAGPREFIX},--pack-data - # pack initialized data into the smallest possible blocks - ${LINKERFLAGPREFIX},--handles - # enable special support for dsPIC interrupt/exception handlers - ${LINKERFLAGPREFIX},--no-isr - # disable default interrupt routine - ${LINKERFLAGPREFIX},--no-ivt - # do not generate ivt or aivt - # Check to create an interrupt function for unused vectors. - ${LINKERFLAGPREFIX},--no-gc-sections - # preserve all sections (do not garbage-collect unused code/data) - ${LINKERFLAGPREFIX},--fill-upper=0 - # zero-fill any gaps above defined sections - ${LINKERFLAGPREFIX},--no-force-link - # do not force-link all library objects - ${LINKERFLAGPREFIX},--smart-io - # enable Smart-IO format‐string optimizations - ${LINKERFLAGPREFIX}, -L${XCDSC_TOOLCHAIN_PATH}/lib - # Set picolib lib path from xc-dsc toolchain to link - ${LINKERFLAGPREFIX}, -lc-pico-elf - # link picolib from xc-dsc toolchain + TARGET linker PROPERTY base ${LINKERFLAGPREFIX},--check-sections + # Check to not check section addresses for overlaps. + ${LINKERFLAGPREFIX},--data-init + # initialize all data sections.Check to support initialized data. + ${LINKERFLAGPREFIX},--pack-data + # pack initialized data into the smallest possible blocks + ${LINKERFLAGPREFIX},--handles + # enable special support for dsPIC interrupt/exception handlers + ${LINKERFLAGPREFIX},--no-isr + # disable default interrupt routine + ${LINKERFLAGPREFIX},--no-ivt + # do not generate ivt or aivt + # Check to create an interrupt function for unused vectors. + ${LINKERFLAGPREFIX},--gc-sections + # preserve all sections (do not garbage-collect unused code/data) + ${LINKERFLAGPREFIX},--fill-upper=0 + # zero-fill any gaps above defined sections + ${LINKERFLAGPREFIX},--no-force-link + # do not force-link all library objects + ${LINKERFLAGPREFIX},--smart-io + # enable Smart-IO format‐string optimizations + ${LINKERFLAGPREFIX}, -L${XCDSC_TOOLCHAIN_PATH}/lib + # Set picolib lib path from xc-dsc toolchain to link + ${LINKERFLAGPREFIX}, -lc-pico-elf + # link picolib from xc-dsc toolchain + ${LINKERFLAGPREFIX}, -mdfp="${DFP_ROOT}/xc16" + ) - ) +set_property(TARGET linker PROPERTY undefined ${LINKERFLAGPREFIX},--undefined=) diff --git a/cmake/linker/xcdsc/target.cmake b/cmake/linker/xcdsc/target.cmake index 0f152caabaaec..38e6ff8b7c3bc 100644 --- a/cmake/linker/xcdsc/target.cmake +++ b/cmake/linker/xcdsc/target.cmake @@ -24,6 +24,7 @@ macro(configure_linker_script linker_script_gen linker_pass_define) -D_LINKER -D_ASM_LANGUAGE -D__XCDSC_LINKER_CMD__ + -mdfp="${DFP_ROOT}/xc16" -imacros ${AUTOCONF_H} -I${ZEPHYR_BASE}/include -imacros${ZEPHYR_BASE}/include/zephyr/linker/sections.h @@ -65,6 +66,7 @@ cmake_parse_arguments( ${TOPT} ${TOOLCHAIN_LD_LINK_ELF_LINKER_SCRIPT} ${TOOLCHAIN_LD_LINK_ELF_LIBRARIES_POST_SCRIPT} + $ ${LINKERFLAGPREFIX},-Map=${TOOLCHAIN_LD_LINK_ELF_OUTPUT_MAP} ${LINKERFLAGPREFIX},--start-group c99-pic30-elf @@ -80,7 +82,6 @@ cmake_parse_arguments( endfunction(toolchain_ld_link_elf) # Finalize Link Execution Behaviour macro(toolchain_linker_finalize) - get_property(zephyr_std_libs TARGET linker PROPERTY lib_include_dir) get_property(link_order TARGET linker PROPERTY link_order_library) foreach(lib ${link_order}) get_property(link_flag TARGET linker PROPERTY ${lib}_library) diff --git a/cmake/toolchain/xcdsc/target.cmake b/cmake/toolchain/xcdsc/target.cmake index 59b4e22882b19..aa7bc1df72334 100644 --- a/cmake/toolchain/xcdsc/target.cmake +++ b/cmake/toolchain/xcdsc/target.cmake @@ -1 +1 @@ -set (ARCH dspic) \ No newline at end of file +set (ARCH dspic) diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 034f99db96dd4..37e838c58454c 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -24,6 +24,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_CC32XX gpio_cc32xx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CMSDK_AHB gpio_cmsdk_ahb.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CY8C95XX gpio_cy8c95xx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_DAVINCI gpio_davinci.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_DSPIC gpio_mchp_dspic33_g1.c) zephyr_library_sources_ifdef(CONFIG_GPIO_DW gpio_dw.c) zephyr_library_sources_ifdef(CONFIG_GPIO_EFINIX_SAPPHIRE gpio_efinix_sapphire.c) zephyr_library_sources_ifdef(CONFIG_GPIO_EMUL gpio_emul.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index bac63dfcf5a38..5f74173129bc2 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -142,6 +142,7 @@ source "drivers/gpio/Kconfig.max22017" source "drivers/gpio/Kconfig.max2219x" source "drivers/gpio/Kconfig.max32" source "drivers/gpio/Kconfig.mchp" +source "drivers/gpio/Kconfig.mchp_dspic" source "drivers/gpio/Kconfig.mchp_mss" source "drivers/gpio/Kconfig.mcp23xxx" source "drivers/gpio/Kconfig.mcux" diff --git a/drivers/gpio/Kconfig.mchp_dspic b/drivers/gpio/Kconfig.mchp_dspic new file mode 100644 index 0000000000000..d36a3461852ea --- /dev/null +++ b/drivers/gpio/Kconfig.mchp_dspic @@ -0,0 +1,9 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +#Enable GPIO driver for dsPIC33A +config GPIO_DSPIC + bool "dsPIC33A GPIO driver" + default y + help + Enable support for the dsPIC33A GPIO driver. diff --git a/drivers/gpio/gpio_mchp_dspic33_g1.c b/drivers/gpio/gpio_mchp_dspic33_g1.c new file mode 100644 index 0000000000000..1f84bad14dda2 --- /dev/null +++ b/drivers/gpio/gpio_mchp_dspic33_g1.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT microchip_dspic_gpio + +#include +#include +#include +#include + +/* Offsets from PORTx base */ +#define TRIS_OFFSET ((uintptr_t)0x08u) +#define LAT_OFFSET ((uintptr_t)0x04u) +#define PORT_OFFSET ((uintptr_t)0x00u) +#define CNSTAT_OFFSET ((uintptr_t)0x0Cu) +/* For pins config need this mask to identify how many + *pins are available for the port + */ +#define PIN_CNT_MASK 0xFFFFFFFF + +struct gpio_dspic_cfg { + struct gpio_driver_config common; + uintptr_t base; +}; + +static int dspic_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +{ + const struct gpio_dspic_cfg *cfg = dev->config; + + /* TRIS offset */ + volatile uint16_t *tris = (void *)(cfg->base + TRIS_OFFSET); + + /* LAT offset */ + volatile uint16_t *lat = (void *)(cfg->base + LAT_OFFSET); + + /* Set initial level before direction */ + if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { + *lat |= BIT(pin); + } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) { + *lat &= ~BIT(pin); + } else { + + /* Else statement added to clear MISRA warning */ + } + + /* Configure direction: TRIS bit = 0 for output, 1 for input */ + if ((flags & GPIO_OUTPUT) != 0) { + *tris &= ~BIT(pin); + } else { + *tris |= BIT(pin); + } + + return 0; +} + +static int dspic_port_toggle_bits(const struct device *dev, gpio_port_pins_t pin) +{ + const struct gpio_dspic_cfg *cfg = dev->config; + volatile uint16_t *lat = (void *)(cfg->base + LAT_OFFSET); + + /* Toggling the GPIO pin */ + *lat ^= pin; + + return 0; +} + +static int dspic_port_get_raw(const struct device *dev, gpio_port_value_t *value) +{ + const struct gpio_dspic_cfg *cfg = dev->config; + volatile const uint16_t *port = (void *)(cfg->base + PORT_OFFSET); + + /* Fetch all values in port */ + *value = *port; + return 0; +} + +static int dspic_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_dspic_cfg *cfg = dev->config; + volatile uint16_t *lat = (void *)(cfg->base + LAT_OFFSET); + + /* Set bits in LAT register */ + *lat |= pins; + return 0; +} + +static int dspic_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_dspic_cfg *cfg = dev->config; + volatile uint16_t *lat = (void *)(cfg->base + LAT_OFFSET); + + /* Clear bits in LAT register */ + *lat &= ~pins; + return 0; +} + +static uint32_t dspic_get_pending_int(const struct device *dev) +{ + const struct gpio_dspic_cfg *cfg = dev->config; + volatile const uint16_t *cnstat = (void *)(cfg->base + CNSTAT_OFFSET); + + /* CNSTATx has the latched change status for each pin */ + return *cnstat; +} + +static int dspic_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, + gpio_port_value_t value) +{ + const struct gpio_dspic_cfg *cfg = dev->config; + volatile uint16_t *lat = (void *)(cfg->base + LAT_OFFSET); + uint16_t tmp = *lat; + + tmp = (tmp & ~mask) | (value & mask); + *lat = tmp; + + return 0; +} + +static const struct gpio_driver_api gpio_dspic_api = { + .pin_configure = dspic_pin_configure, + .port_toggle_bits = dspic_port_toggle_bits, + .port_get_raw = dspic_port_get_raw, + .port_set_bits_raw = dspic_port_set_bits_raw, + .port_clear_bits_raw = dspic_port_clear_bits_raw, + .get_pending_int = dspic_get_pending_int, + .port_set_masked_raw = dspic_set_masked_raw, +}; + +/* In the below config port_pin_mask is now hardcoded as 0xFFFFFFFF which + * actually require the helper macros to get the correct mask based on the + * no of pins supported for a specific port in dspic. + */ +/* Create instances from DT */ +#define GPIO_DSPIC_INIT(inst) \ + static const struct gpio_dspic_cfg gpio_dspic_cfg_##inst = { \ + .common = \ + { \ + .port_pin_mask = PIN_CNT_MASK, \ + }, \ + .base = DT_INST_REG_ADDR(inst), \ + }; \ + DEVICE_DT_INST_DEFINE(inst, NULL, NULL, NULL, &gpio_dspic_cfg_##inst, POST_KERNEL, \ + CONFIG_GPIO_INIT_PRIORITY, &gpio_dspic_api); + +DT_INST_FOREACH_STATUS_OKAY(GPIO_DSPIC_INIT) diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index ea46edf46dc5f..640d98b612f0a 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -58,6 +58,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_REALTEK_RTS5912 pinctrl_realtek_rts5 zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x_afio.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_00X_AFIO pinctrl_wch_00x_afio.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SF32LB52X pinctrl_sf32lb52x.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_DSPIC33 pinctrl_mchp_dspic33_g1.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 9050f3ef5c998..2ad452999dc15 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -88,6 +88,7 @@ source "drivers/pinctrl/Kconfig.realtek_rts5912" source "drivers/pinctrl/Kconfig.wch_20x_30x_afio" source "drivers/pinctrl/Kconfig.wch_00x_afio" source "drivers/pinctrl/Kconfig.sf32lb52x" +source "drivers/pinctrl/Kconfig.dspic33" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.dspic33 b/drivers/pinctrl/Kconfig.dspic33 new file mode 100644 index 0000000000000..06951815dc51e --- /dev/null +++ b/drivers/pinctrl/Kconfig.dspic33 @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_MCHP_DSPIC33 + bool "Pin controller driver for Microchip dsPIC33 MCUs" + default y + depends on DT_HAS_MICROCHIP_DSPIC33_PINCTRL_ENABLED + help + Enable the pin controller driver for Microchip dsPIC33 MCUs. diff --git a/drivers/pinctrl/pinctrl_mchp_dspic33_g1.c b/drivers/pinctrl/pinctrl_mchp_dspic33_g1.c new file mode 100644 index 0000000000000..e57676d30df7c --- /dev/null +++ b/drivers/pinctrl/pinctrl_mchp_dspic33_g1.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +#define DT_DRV_COMPAT microchip_dspic33_pinctrl + + +#define MCHP_DSPIC_GET_PORT_ADDR_OR_NONE(nodelabel) \ + IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \ + (DT_REG_ADDR(DT_NODELABEL(nodelabel)))) + +static int pinctrl_configure_pin(pinctrl_soc_pin_t soc_pin) +{ + volatile uint32_t port; + volatile uint32_t pin; + volatile uint32_t func; + int ret = 0; + + /* GPIO port addresses */ + static const uint32_t gpios[] = { + MCHP_DSPIC_GET_PORT_ADDR_OR_NONE(gpioa), + MCHP_DSPIC_GET_PORT_ADDR_OR_NONE(gpiob), + MCHP_DSPIC_GET_PORT_ADDR_OR_NONE(gpioc), + MCHP_DSPIC_GET_PORT_ADDR_OR_NONE(gpiod), +#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) + MCHP_DSPIC_GET_PORT_ADDR_OR_NONE(gpioe), + MCHP_DSPIC_GET_PORT_ADDR_OR_NONE(gpiof), + MCHP_DSPIC_GET_PORT_ADDR_OR_NONE(gpiog), + MCHP_DSPIC_GET_PORT_ADDR_OR_NONE(gpioh), +#endif + }; + + port = DSPIC33_PINMUX_PORT(soc_pin.pinmux); + pin = DSPIC33_PINMUX_PIN(soc_pin.pinmux); + func = DSPIC33_PINMUX_FUNC(soc_pin.pinmux); + + if (gpios[port] != 0U) { + + if ((func & 0xFF00U) == 0U) { + /* Output Remappable functionality pins */ + volatile uint32_t reg_shift = + ((pin < 4U) ? (0U) : (pin / 4U)); + volatile uint32_t reg_index = pin % 4U; + volatile uint32_t RPORx_BASE = gpios[0] + OFFSET_RPOR; + + func = (func << (reg_index * 8u)); + volatile uint32_t *RPORx = + (void *)(RPORx_BASE + (port * 0x10U) + (reg_shift * 4U)); + *RPORx |= func; + + /* Setting latch bit */ + volatile uint32_t *latch = (void *)(gpios[port] + OFFSET_LATCH); + *latch |= (1U << pin); + + /* Setting TRIS bit*/ + volatile uint32_t *tris = (void *)(gpios[port] + OFFSET_TRIS); + *tris &= ~(1U << pin); + + /* setting ANSEl bit */ +#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106) + if ((port == PORT_A) || (port == PORT_B)) { + volatile uint32_t *ansel = + (void *)(gpios[0] + OFFSET_ANSEL + (port * 0x24U)); + *ansel &= ~(1U << pin); + } +#elif defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) + volatile uint32_t *ansel = + (void *)(gpios[0] + OFFSET_ANSEL + (port * 0x24U)); + *ansel &= ~(1U << pin); +#endif + } else { + /* Input Remappable functionality pins */ + volatile int pin_rpin = (port * 0x10U) + pin + 1U; + volatile uint8_t *RPINx = (void *)(DSPIC33_PINMUX_FUNC(soc_pin.pinmux)); + *RPINx |= pin_rpin; + + /* setting ANSEl bit */ +#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106) + if ((port == PORT_A) || (port == PORT_B)) { + volatile uint32_t *ansel = + (void *)(gpios[0] + OFFSET_ANSEL + (port * 0x24U)); + *ansel &= ~(1U << pin); + } +#elif defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) + volatile uint32_t *ansel = + (void *)(gpios[0] + OFFSET_ANSEL + (port * 0x24U)); + *ansel &= ~(1U << pin); +#endif + } + } else { + ret = -EINVAL; + } + + return 0; +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + ARG_UNUSED(reg); + + int ret = 0; + + for (uint8_t i = 0U; i < pin_cnt; i++) { + ret = pinctrl_configure_pin(pins[i]); + } + + return ret; +} diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index eff991b3b29cc..7bf6c5d378728 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -32,7 +32,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_CC23X0 uart_cc23x0.c) zephyr_library_sources_ifdef(CONFIG_UART_CC32XX uart_cc32xx.c) zephyr_library_sources_ifdef(CONFIG_UART_CDNS uart_cdns.c) zephyr_library_sources_ifdef(CONFIG_UART_CMSDK_APB uart_cmsdk_apb.c) -zephyr_library_sources_ifdef(CONFIG_UART_DSPIC uart_dspic.c) +zephyr_library_sources_ifdef(CONFIG_UART_DSPIC uart_mchp_dspic33_g1.c) zephyr_library_sources_ifdef(CONFIG_UART_EFINIX_SAPPIHIRE uart_efinix_sapphire.c) zephyr_library_sources_ifdef(CONFIG_UART_EMUL uart_emul.c) zephyr_library_sources_ifdef(CONFIG_UART_ENE_KB106X uart_ene_kb106x.c) diff --git a/drivers/serial/Kconfig.dspic_uart b/drivers/serial/Kconfig.dspic_uart index bf582fb128c66..f97564d98aa9f 100644 --- a/drivers/serial/Kconfig.dspic_uart +++ b/drivers/serial/Kconfig.dspic_uart @@ -1,10 +1,11 @@ # Copyright (c) 2025, Microchip Technology Inc. # SPDX-License-Identifier: Apache-2.0 - config UART_DSPIC bool "dsPIC33A UART driver" default y select SERIAL_HAS_DRIVER + select SERIAL_SUPPORT_INTERRUPT + select PINCTRL help Enable support for the dsPIC33A UART driver. diff --git a/drivers/serial/uart_dspic.c b/drivers/serial/uart_dspic.c deleted file mode 100644 index c8f1542012669..0000000000000 --- a/drivers/serial/uart_dspic.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2025, Microchip Technology Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -#ifndef _ASMLANGUAGE -#include -#endif - -#define DT_DRV_COMPAT microchip_dspic33_uart - -#define OFFSET_MODE 0x00U -#define OFFSET_STA 0x04U -#define OFFSET_TXREG 0x10U -#define OFFSET_BRG 0x08U -#define OFFSET_RXREG 0x0CU -#define BIT_UTXEN 0x00000020U -#define BIT_URXEN 0x00000010U -#define BIT_UARTEN 0x00008000U -#define BIT_TXBF 0x00100000U -#define BIT_RXBE 0x00020000U -#define FRACTIONAL_BRG 0x8000000U - -#define CALCULATE_BRG(baudrate) \ - ((ceil(((double)(sys_clock_hw_cycles_per_sec())) / ((double)(2U * (baudrate)))))) -const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(uart1)); -static struct k_spinlock lock; - -struct uart_dspic_config { - uint32_t base; - uint32_t baudrate; -}; - -static void uart_dspic_poll_out(const struct device *dev, unsigned char c) -{ - k_spinlock_key_t key; - const struct uart_dspic_config *cfg = dev->config; - volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); - volatile uint32_t *UxTXREG = (void *)(cfg->base + OFFSET_TXREG); - - /* Wait until there is space in the TX FIFO */ - while ((bool)(void *)((*UxSTA) & BIT_TXBF)) { - ; - } - key = k_spin_lock(&lock); - *UxTXREG = c; - k_spin_unlock(&lock, key); -} - -static int uart_dspic_poll_in(const struct device *dev, unsigned char *c) -{ - k_spinlock_key_t key; - const struct uart_dspic_config *cfg = dev->config; - volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); - volatile uint32_t *UxRXREG = (void *)(cfg->base + OFFSET_RXREG); - int ret_val; - - key = k_spin_lock(&lock); - /* If receiver buffer is empty, return -1 */ - if ((*UxSTA & BIT_RXBE) != 0U) { - ret_val = -EPERM; - } - - else { - *c = *UxRXREG & 0xFF; - ret_val = 0; - } - - k_spin_unlock(&lock, key); - return ret_val; -} - -static int uart_dspic_init(const struct device *dev) -{ - LATB = 0x0040UL; - TRISB = 0x0FBFUL; - ANSELA = 0x0FFFUL; - ANSELB = 0x033FUL; - - /* Assign U1TX to RP23 and U1RX to RP24*/ - _RP23R = 9; - _U1RXR = 24; - const struct uart_dspic_config *cfg = dev->config; - volatile uint32_t *UxCON = (void *)(cfg->base + OFFSET_MODE); - - /* Setting the baudrate */ - *UxCON = FRACTIONAL_BRG; - volatile uint32_t *UxBRG = (void *)(cfg->base + OFFSET_BRG); - *UxBRG = (uint32_t)CALCULATE_BRG(cfg->baudrate); - - /* Enable UART */ - *UxCON |= BIT_UARTEN | BIT_UTXEN | BIT_URXEN; - - return 0; -} - -static const struct uart_driver_api uart_dspic_api = { - .poll_out = uart_dspic_poll_out, - .poll_in = uart_dspic_poll_in, -}; - -#define UART_DSPIC_INIT(inst) \ - static const struct uart_dspic_config uart_dspic_config_##inst = { \ - .base = DT_REG_ADDR(DT_INST(inst, microchip_dspic33_uart)), \ - .baudrate = DT_PROP(DT_INST(inst, microchip_dspic33_uart), current_speed), \ - }; \ - DEVICE_DT_INST_DEFINE(inst, uart_dspic_init, NULL, NULL, &uart_dspic_config_##inst, \ - PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &uart_dspic_api); - -DT_INST_FOREACH_STATUS_OKAY(UART_DSPIC_INIT) diff --git a/drivers/serial/uart_mchp_dspic33_g1.c b/drivers/serial/uart_mchp_dspic33_g1.c new file mode 100644 index 0000000000000..861a4bf1de927 --- /dev/null +++ b/drivers/serial/uart_mchp_dspic33_g1.c @@ -0,0 +1,425 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef _ASMLANGUAGE +#include +#endif + +#define DT_DRV_COMPAT microchip_dspic33_uart + +/* UART Register Offsets */ +#define UART_MODE (0x00U) /* Offset for UART Mode register */ +#define OFFSET_STA (0x04U) /* Offset for UART Status register */ +#define OFFSET_BRG (0x08U) /* Offset for Baud Rate Generator register */ +#define OFFSET_RXREG (0x0CU) /* Offset for UART Receive register */ +#define OFFSET_TXREG (0x10U) /* Offset for UART Transmit register */ + +/* UART Control Bits */ +#define BIT_UTXEN (0x00000020U) /* UART Transmit Enable bit mask */ +#define BIT_URXEN (0x00000010U) /* UART Receive Enable bit mask */ +#define BIT_UARTEN (0x00008000U) /* UART Module Enable bit mask */ +#define BIT_TXBF (0x00100000U) /* UART Transmit Buffer Full status */ +#define BIT_TXBE (0x00200000U) /* UART TX buffer empty status bit mask */ +#define BIT_RXBF (0x00010000U) /* UART RX buffer full bit */ +#define BIT_RXBE (0x00020000U) /* UART Receive Buffer Empty status */ +#define ERR_IRQ_ENABLE (0x00007F00U) /* UART Error interrupts enable mask */ +#define ERR_IRQ_CLEAR (0x00000017U) /* UART Error interrupts flag clear mask */ +#define FRACTIONAL_BRG (0x08000000U) /* Fractional Baud Rate Generator enable */ + +/* Interrupt Level Select Bits */ +#define BIT_UxTXWM (0x00000000U) /* UART TX interrupt level select bit */ +#define BIT_UxRXWM (0x00000000U) /* UART RX interrupt level select bit */ + +/* Generic Masks */ +#define BIT_MASK_RCVR (0xFFU) /* Mask for receiver buffer */ + +static struct k_spinlock lock; + +struct uart_dspic_config { + uint32_t base; + uint32_t baudrate; +#ifdef CONFIG_PINCTRL + const struct pinctrl_dev_config *pcfg; +#endif +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + void (*irq_config_func)(const struct device *dev); + /* IRQ number */ + unsigned int rx_irq_num; + unsigned int tx_irq_num; + unsigned int err_irq_num; +#endif +}; + +static inline uint32_t CALCULATE_BRG(uint32_t baudrate) +{ + double sys_clk = (double)sys_clock_hw_cycles_per_sec(); + double divisor = (2.0 * (double)baudrate); + + /* Round up (ceil) as per formula */ + uint32_t brg = (uint32_t)ceil(sys_clk / divisor); + + return brg; +} + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN +struct uart_dspic_data { + uart_irq_callback_user_data_t callback; + void *user_data; +}; + +static void uart_dspic_isr(const struct device *dev) +{ + struct uart_dspic_data *data = dev->data; + const struct uart_dspic_config *cfg = dev->config; + volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); + + /* RX interrupt flag set check */ + if ((bool)arch_dspic_irq_isset(cfg->rx_irq_num)) { + if ((bool)data->callback) { + data->callback(dev, data->user_data); + } + } + + /* TX interrupt flag set check */ + if ((bool)arch_dspic_irq_isset(cfg->tx_irq_num)) { + if ((bool)data->callback) { + data->callback(dev, data->user_data); + } + } + + /* ERR interrupt flag set check */ + if ((bool)arch_dspic_irq_isset(cfg->err_irq_num)) { + + /* Clear error interrupt flag in uart status register */ + *UxSTA &= ~ERR_IRQ_CLEAR; + if ((bool)data->callback) { + data->callback(dev, data->user_data); + } + } +} + +static void uart_dspic_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb, + void *user_data) +{ + k_spinlock_key_t key; + struct uart_dspic_data *data = dev->data; + + /* Registering the callback function and user data */ + key = k_spin_lock(&lock); + data->callback = cb; + data->user_data = user_data; + k_spin_unlock(&lock, key); +} + +static void uart_dspic_irq_tx_enable(const struct device *dev) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + + key = k_spin_lock(&lock); + /* Enabling the UART transmit interrupt */ + irq_enable(cfg->tx_irq_num); + k_spin_unlock(&lock, key); +} + +static void uart_dspic_irq_tx_disable(const struct device *dev) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + + key = k_spin_lock(&lock); + /* Disabling the UART transmit interrupt */ + irq_disable(cfg->tx_irq_num); + k_spin_unlock(&lock, key); +} + +static void uart_dspic_irq_rx_enable(const struct device *dev) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + + key = k_spin_lock(&lock); + /* Enabling the UART receiver interrupt */ + irq_enable(cfg->rx_irq_num); + k_spin_unlock(&lock, key); +} + +static void uart_dspic_irq_rx_disable(const struct device *dev) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + + key = k_spin_lock(&lock); + /* Disabling the UART receiver interrupt */ + irq_disable(cfg->rx_irq_num); + k_spin_unlock(&lock, key); +} + +static void uart_dspic_irq_err_enable(const struct device *dev) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + + key = k_spin_lock(&lock); + /* Enabling the UART Error interrupt */ + irq_enable(cfg->err_irq_num); + k_spin_unlock(&lock, key); +} + +static void uart_dspic_irq_err_disable(const struct device *dev) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + + key = k_spin_lock(&lock); + /* Disabling the UART Error interrupt */ + irq_disable(cfg->err_irq_num); + k_spin_unlock(&lock, key); +} + +static int uart_dspic_irq_tx_ready(const struct device *dev) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); + int ret; + + key = k_spin_lock(&lock); + /* Transmit buffer empty check */ + ret = (*UxSTA & BIT_TXBE) ? 1 : 0; + k_spin_unlock(&lock, key); + + return ret; +} + +static int uart_dspic_irq_rx_ready(const struct device *dev) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); + int ret; + + key = k_spin_lock(&lock); + /* Receiver buffer not full check */ + ret = (*UxSTA & BIT_RXBF) ? 0 : 1; + k_spin_unlock(&lock, key); + + return ret; +} + +static int uart_dspic_irq_is_pending(const struct device *dev) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + int ret; + + /* Interrupt pending check */ + key = k_spin_lock(&lock); + ret = arch_dspic_irq_isset(cfg->rx_irq_num) | arch_dspic_irq_isset(cfg->tx_irq_num) | + arch_dspic_irq_isset(cfg->err_irq_num); + k_spin_unlock(&lock, key); + + return ret; +} + +static int uart_dspic_irq_update(const struct device *dev) +{ + (void)dev; + return 1; +} + +static int uart_dspic_fifo_read(const struct device *dev, uint8_t *rx_data, const int size) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); + volatile uint32_t *UxRXREG = (void *)(cfg->base + OFFSET_RXREG); + int num_read = 0; + + /* Transmitting data of size bytes */ + while ((num_read < size) && (!(*UxSTA & BIT_RXBE))) { + key = k_spin_lock(&lock); + rx_data[num_read] = *UxRXREG & BIT_MASK_RCVR; + num_read++; + k_spin_unlock(&lock, key); + } + + return num_read; +} + +static int uart_dspic_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); + volatile uint32_t *UxTXREG = (void *)(cfg->base + OFFSET_TXREG); + int num_sent = 0; + + /* Receiving data of size bytes */ + while ((num_sent < size) && (!(*UxSTA & BIT_TXBF))) { + key = k_spin_lock(&lock); + *UxTXREG = tx_data[num_sent]; + num_sent++; + k_spin_unlock(&lock, key); + } + + return num_sent; +} +#endif + +static void uart_dspic_poll_out(const struct device *dev, unsigned char c) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); + volatile uint32_t *UxTXREG = (void *)(cfg->base + OFFSET_TXREG); + + /* Wait until there is space in the TX FIFO */ + while ((bool)(void *)((*UxSTA) & BIT_TXBF)) { + ; + } + key = k_spin_lock(&lock); + *UxTXREG = c; + k_spin_unlock(&lock, key); +} + +static int uart_dspic_poll_in(const struct device *dev, unsigned char *c) +{ + k_spinlock_key_t key; + const struct uart_dspic_config *cfg = dev->config; + volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); + volatile uint32_t *UxRXREG = (void *)(cfg->base + OFFSET_RXREG); + int ret_val; + + key = k_spin_lock(&lock); + /* If receiver buffer is empty, return -1 */ + if ((*UxSTA & BIT_RXBE) != 0U) { + ret_val = -EPERM; + } + + else { + *c = *UxRXREG & 0xFF; + ret_val = 0; + } + + k_spin_unlock(&lock, key); + return ret_val; +} + +static int uart_dspic_init(const struct device *dev) +{ + const struct uart_dspic_config *cfg = dev->config; + volatile uint32_t *UxCON = (void *)(cfg->base); + volatile uint32_t *UxBRG = (void *)(cfg->base + OFFSET_BRG); + volatile uint32_t *UxSTA = (void *)(cfg->base + OFFSET_STA); + int ret = 0; + + ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (ret == 0) { + /* Setting the UART mode */ + *UxCON |= UART_MODE; + + /* Setting the baudrate */ + *UxCON |= FRACTIONAL_BRG; + *UxBRG |= CALCULATE_BRG(cfg->baudrate); + + /* Enable UART */ + *UxCON |= BIT_UARTEN; + *UxCON |= BIT_UTXEN; + *UxCON |= BIT_URXEN; + + /* Selecting the transmit and receive interrupt level bit */ + *UxSTA |= BIT_UxTXWM; + *UxSTA |= BIT_UxRXWM; + + /* Enabling the Error interrupts */ + *UxSTA |= ERR_IRQ_ENABLE; + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + if (cfg->irq_config_func != NULL) { + cfg->irq_config_func(dev); + } +#endif + } + + return ret; +} + +static const struct uart_driver_api uart_dspic_api = { + .poll_out = uart_dspic_poll_out, + .poll_in = uart_dspic_poll_in, + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + .fifo_fill = uart_dspic_fifo_fill, + .fifo_read = uart_dspic_fifo_read, + .irq_rx_enable = uart_dspic_irq_rx_enable, + .irq_rx_disable = uart_dspic_irq_rx_disable, + .irq_tx_enable = uart_dspic_irq_tx_enable, + .irq_tx_disable = uart_dspic_irq_tx_disable, + .irq_err_enable = uart_dspic_irq_err_enable, + .irq_err_disable = uart_dspic_irq_err_disable, + .irq_callback_set = uart_dspic_irq_callback_set, + .irq_tx_ready = uart_dspic_irq_tx_ready, + .irq_rx_ready = uart_dspic_irq_rx_ready, + .irq_is_pending = uart_dspic_irq_is_pending, + .irq_update = uart_dspic_irq_update, +#endif +}; + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN +#define UART_DSPIC_IRQ_HANDLER_DECLARE(inst) \ + static void uart_dspic_irq_config_##inst(const struct device *dev); + +#define UART_DSPIC_IRQ_HANDLER_DEFINE(inst) \ + static void uart_dspic_irq_config_##inst(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, 0, irq), \ + DT_INST_IRQ_BY_IDX(inst, 0, priority), uart_dspic_isr, \ + DEVICE_DT_INST_GET(inst), 0); \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, 1, irq), \ + DT_INST_IRQ_BY_IDX(inst, 1, priority), uart_dspic_isr, \ + DEVICE_DT_INST_GET(inst), 0); \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, 2, irq), \ + DT_INST_IRQ_BY_IDX(inst, 2, priority), uart_dspic_isr, \ + DEVICE_DT_INST_GET(inst), 0); \ + irq_enable(DT_INST_IRQ_BY_IDX(inst, 0, irq)); \ + irq_enable(DT_INST_IRQ_BY_IDX(inst, 1, irq)); \ + irq_enable(DT_INST_IRQ_BY_IDX(inst, 2, irq)); \ + } + +#define UART_DSPIC_IRQ_CONFIG_FUNC(inst) .irq_config_func = uart_dspic_irq_config_##inst, +#else +#define UART_DSPIC_IRQ_HANDLER_DECLARE(inst) +#define UART_DSPIC_IRQ_HANDLER_DEFINE(inst) +#define UART_DSPIC_IRQ_CONFIG_FUNC(inst) +#endif + +#define UART_DSPIC_INIT(inst) \ + UART_DSPIC_IRQ_HANDLER_DECLARE(inst) \ + PINCTRL_DT_INST_DEFINE(inst); \ + static const struct uart_dspic_config uart_dspic_config_##inst = { \ + .base = DT_INST_REG_ADDR(inst), \ + .baudrate = DT_INST_PROP(inst, current_speed), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ + UART_DSPIC_IRQ_CONFIG_FUNC(inst).rx_irq_num = DT_INST_IRQ_BY_IDX(inst, 0, irq), \ + .tx_irq_num = DT_INST_IRQ_BY_IDX(inst, 1, irq), \ + .err_irq_num = DT_INST_IRQ_BY_IDX(inst, 2, irq), \ + }; \ + static struct uart_dspic_data uart_dspic_data_##inst; \ + DEVICE_DT_INST_DEFINE(inst, uart_dspic_init, NULL, &uart_dspic_data_##inst, \ + &uart_dspic_config_##inst, PRE_KERNEL_1, \ + CONFIG_SERIAL_INIT_PRIORITY, &uart_dspic_api); \ + UART_DSPIC_IRQ_HANDLER_DEFINE(inst) + +DT_INST_FOREACH_STATUS_OKAY(UART_DSPIC_INIT) diff --git a/drivers/timer/mchp_dspic33_timer.c b/drivers/timer/mchp_dspic33_timer.c index ec0470fe206d2..873d3c6f782db 100644 --- a/drivers/timer/mchp_dspic33_timer.c +++ b/drivers/timer/mchp_dspic33_timer.c @@ -12,17 +12,26 @@ #include #include #include +#include #include #include #define TIMER1_CYCLES_PER_TICK \ - ((sys_clock_hw_cycles_per_sec()) / \ - (2 * DT_INST_PROP(0, prescalar) * CONFIG_SYS_CLOCK_TICKS_PER_SEC)) + ((sys_clock_hw_cycles_per_sec() + \ + ((2U * DT_INST_PROP(0, prescalar) * CONFIG_SYS_CLOCK_TICKS_PER_SEC) / 2U)) / \ + (2U * DT_INST_PROP(0, prescalar) * CONFIG_SYS_CLOCK_TICKS_PER_SEC)) -#define MAX_TIMER_CLOCK_CYCLES 0xFFFFFFFFu +#define MAX_TIMER_CLOCK_CYCLES 0xFFFFFFFFU static struct k_spinlock lock; +static uint64_t total_cycles; +static uint64_t prev_announced_cycle; +static uint32_t un_announced_cycles; -uint8_t map_prescaler_to_bits(uint32_t val) +#if defined(CONFIG_TEST) +const int32_t z_sys_timer_irq_for_test = DT_INST_IRQN(0); +#endif + +static uint8_t map_prescaler_to_bits(uint32_t val) { uint8_t ret_val; @@ -36,7 +45,7 @@ uint8_t map_prescaler_to_bits(uint32_t val) case 64: ret_val = 0b10; break; - case 128: + case 256: ret_val = 0b11; break; default: @@ -52,6 +61,8 @@ static void configure_timer1(void) /* clear timer control and timer count register */ T1CONbits.ON = 0; + + /* Select standard peripheral clock */ T1CONbits.TCS = 0; T1CONbits.TCKPS = map_prescaler_to_bits(DT_INST_PROP(0, prescalar)); TMR1 = 0; @@ -70,7 +81,15 @@ static void configure_timer1(void) */ uint32_t sys_clock_cycle_get_32(void) { - return TMR1; + uint32_t cycles; + k_spinlock_key_t key; + + key = k_spin_lock(&lock); + cycles = (uint32_t)total_cycles + (PR1 * (uint32_t)arch_dspic_irq_isset(DT_INST_IRQN(0))) + + TMR1; + k_spin_unlock(&lock, key); + + return cycles * 2U * DT_INST_PROP(0, prescalar); } uint32_t sys_clock_elapsed(void) @@ -90,9 +109,9 @@ uint32_t sys_clock_elapsed(void) * Call is made, the ticks elapsed is current timer1 count divided by * Number of cycles per tick */ - ticks_elapsed = (uint32_t)TMR1 < (uint32_t)TIMER1_CYCLES_PER_TICK - ? 0 - : (uint32_t)TMR1 / (uint32_t)TIMER1_CYCLES_PER_TICK; + ticks_elapsed = ((uint32_t)(total_cycles - prev_announced_cycle) + + (uint32_t)(TMR1 + ((uint32_t)TIMER1_CYCLES_PER_TICK / 10U))) / + ((uint32_t)TIMER1_CYCLES_PER_TICK); k_spin_unlock(&lock, key); } while (0); @@ -101,7 +120,7 @@ uint32_t sys_clock_elapsed(void) void sys_clock_set_timeout(int32_t ticks, bool idle) { - uint32_t next_count; + volatile uint32_t next_count; k_spinlock_key_t key; ARG_UNUSED(idle); @@ -109,7 +128,7 @@ void sys_clock_set_timeout(int32_t ticks, bool idle) do { if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) { - /* If it is not in tickles mode, no need to change the + /* if it is not in tickles mode, no need to change the * Timeout interval, it will periodically interrupt * At every tick */ @@ -121,6 +140,8 @@ void sys_clock_set_timeout(int32_t ticks, bool idle) ? MAX_TIMER_CLOCK_CYCLES : (uint32_t)(ticks * TIMER1_CYCLES_PER_TICK); key = k_spin_lock(&lock); + total_cycles = total_cycles + (uint64_t)TMR1; + un_announced_cycles = un_announced_cycles + TMR1; /* clear the timer1 counter register and set the period register to the * New timeout value. This should be done with TIMER1 disabled @@ -131,7 +152,6 @@ void sys_clock_set_timeout(int32_t ticks, bool idle) T1CONbits.ON = 1; k_spin_unlock(&lock, key); } while (0); - } /* Timer1 ISR */ @@ -147,11 +167,10 @@ static void timer1_isr(const void *arg) * Of cycles per tick. For tickles, the period would have been set * To the next event time. */ - elapsed_ticks = (uint32_t)PR1 / (uint32_t)TIMER1_CYCLES_PER_TICK; + elapsed_ticks = (uint32_t)(un_announced_cycles + PR1) / (uint32_t)TIMER1_CYCLES_PER_TICK; key = k_spin_lock(&lock); - /* Clear the timer interrupt flag status bit*/ - IFS1bits.T1IF = 0; + total_cycles = total_cycles + (uint64_t)PR1; if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) { /* If not in tickles mode set the interrupt to happen at the next @@ -164,9 +183,33 @@ static void timer1_isr(const void *arg) } k_spin_unlock(&lock, key); - /* notify the kernel about the tick */ - sys_clock_announce(elapsed_ticks); + /* + * The hardware timer (TMR1/PR1) has a limited range. If PR1 hits its maximum + * value (MAX_TIMER_CLOCK_CYCLES), we must stop and restart the timer with this + * max period to prevent overflow/wraparound issues. + * + * Otherwise, if PR1 is within range, we reset un_announced_cycles and call + * sys_clock_announce(elapsed_ticks) to inform the kernel about the elapsed + * system ticks. This keeps the Zephyr kernel’s time accounting accurate. + */ + if (PR1 != MAX_TIMER_CLOCK_CYCLES) { + T1CONbits.ON = 0; + un_announced_cycles = 0; + prev_announced_cycle = total_cycles; + sys_clock_announce(elapsed_ticks); + } +} + +#ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT +void arch_busy_wait(uint32_t usec_to_wait) +{ + uint32_t cycles_to_wait = sys_clock_hw_cycles_per_sec() / USEC_PER_SEC * usec_to_wait; + + while (cycles_to_wait-- > 0) { + __asm__ volatile("nop\n\t"); + } } +#endif /* Initialize the system clock driver */ int sys_clock_driver_init(void) diff --git a/dts/bindings/gpio/microchip,dspic-gpio.yaml b/dts/bindings/gpio/microchip,dspic-gpio.yaml new file mode 100644 index 0000000000000..e8919718fa603 --- /dev/null +++ b/dts/bindings/gpio/microchip,dspic-gpio.yaml @@ -0,0 +1,51 @@ +# microchip,dspic-gpio.yaml + +description: | + Group of GPIO-controlled LEDs. + + Each LED is defined in a child node of the gpio-leds node. + + Here is an example which defines three LEDs in the node /leds: + + / { + leds { + compatible = "gpio-leds"; + led_0 { + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + led_1 { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + }; + led_2 { + gpios = <&gpio1 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + }; + }; + }; + + Above: + + - led_0 is pin 1 on gpio0. The LED is on when the pin is low, + and off when the pin is high. + - led_1 is pin 2 on gpio0. The LED is on when the pin is high, + and off when it is low. + - led_2 is pin 15 on gpio1. The LED is on when the pin is low, + and the pin's internal pull-up resistor should be enabled. + +compatible: "microchip,dspic-gpio" + +include: [gpio-controller.yaml] + +properties: + reg: + type: array + required: true + + gpio-controller: {} + + "#gpio-cells": + type: int + const: 2 + +gpio-cells: + - pin + - flags diff --git a/dts/bindings/interrupt-controller/microchip,dspic33-intc.yaml b/dts/bindings/interrupt-controller/microchip,dspic33-intc.yaml index 8db2f9f30ef8f..fe8394e31932b 100644 --- a/dts/bindings/interrupt-controller/microchip,dspic33-intc.yaml +++ b/dts/bindings/interrupt-controller/microchip,dspic33-intc.yaml @@ -14,6 +14,17 @@ properties: "#interrupt-cells": const: 2 + ie-offset: + type: int + required: true + description: Offset (bytes) of the interrupt-enable register block within the controller's base. + + if-offset: + type: int + required: true + description: Offset (bytes) of the interrupt-flag/status register block within the controller's base. + interrupt-cells: - irq - priority + diff --git a/dts/bindings/pinctrl/microchip,dspic33-pinctrl.yaml b/dts/bindings/pinctrl/microchip,dspic33-pinctrl.yaml new file mode 100644 index 0000000000000..0c251ed0a0804 --- /dev/null +++ b/dts/bindings/pinctrl/microchip,dspic33-pinctrl.yaml @@ -0,0 +1,26 @@ +description: | + Microchip dsPIC33 pin controller + +compatible: "microchip,dspic33-pinctrl" + +include: base.yaml + +properties: + reg: + required: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +child-binding: + description: Pin configuration node + properties: + pinmux: + description: | + Pin multiplexing configuration for this group. + Multiple pins (like TX/RX) can be grouped inside one node. + required: true + type: int diff --git a/dts/bindings/serial/microchip,dspic33-uart.yaml b/dts/bindings/serial/microchip,dspic33-uart.yaml index be59014316e1c..6d220e9a050c2 100644 --- a/dts/bindings/serial/microchip,dspic33-uart.yaml +++ b/dts/bindings/serial/microchip,dspic33-uart.yaml @@ -1,19 +1,49 @@ -# microchip,dspic33-uart.yaml +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 description: Microchip dsPIC33 UART controller compatible: "microchip,dspic33-uart" -include: uart-controller.yaml +include: [uart-controller.yaml, pinctrl-device.yaml] properties: reg: required: true + type: array + description: Register address and size for the UART peripheral clock-frequency: type: int required: true + description: Clock frequency for the UART peripheral + + interrupts: + required: true + type: array + description: Interrupt specifiers for RX, TX, and error interrupts + + interrupt-names: + type: string-array + description: Interrupt names "rx", "tx", "err" + + interrupt-parent: + type: phandle + description: Parent interrupt controller + + current-speed: + required: true + type: int + description: Baud rate for the UART + + pinctrl-0: + required: true + description: Pin control group for default state + + pinctrl-names: + required: true + description: Pin control state names status: type: string - required: true + description: Device status diff --git a/dts/dspic/p33ak128mc106.dtsi b/dts/dspic/p33ak128mc106.dtsi index ad37b0c94029d..6f7a5a8bb5f30 100644 --- a/dts/dspic/p33ak128mc106.dtsi +++ b/dts/dspic/p33ak128mc106.dtsi @@ -3,6 +3,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "zephyr/dt-bindings/pinctrl/mchp-p33ak128mc106-pinctrl.h" + / { model = "Microchip dsPIC33A Curiosity Platform Development Board"; compatible = "microchip,p33ak128mc106"; @@ -51,9 +53,11 @@ label = "SRAM"; }; - intc0: interrupt-controller@0 { + intc0: interrupt-controller@70 { compatible = "microchip,dspic33-intc"; - reg = <0x0 0x1>; + reg = <0x70 0x1>; + ie-offset = <0xB4>; + if-offset = <0x90>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; @@ -70,12 +74,108 @@ status = "okay"; }; - uart1: uart@1700 { + uart0: uart@1700 { + compatible = "microchip,dspic33-uart"; + reg = <0x1700 0x40>; + interrupts = <89 1>, <90 1>, <91 1>; + interrupt-names = "rx", "tx", "err"; + interrupt-parent = <&intc0>; + clock-frequency = <4000000>; + current-speed = <115200>; + pinctrl-0 = <&uart0_tx_default &uart0_rx_default>; + pinctrl-names = "default"; + status = "okay"; + }; + + uart1: uart@1740 { + compatible = "microchip,dspic33-uart"; + reg = <0x1740 0x40>; + interrupts = <93 1>, <94 1>, <95 1>; + interrupt-names = "rx", "tx", "err"; + interrupt-parent = <&intc0>; + clock-frequency = <4000000>; + current-speed = <115200>; + pinctrl-0 = <&uart1_tx_default &uart1_rx_default>; + pinctrl-names = "default"; + status = "okay"; + }; + + uart2: uart@1780 { compatible = "microchip,dspic33-uart"; - reg = <0x1700 0x28>; + reg = <0x1780 0x40>; + interrupts = <97 1>, <98 1>, <99 1>; + interrupt-names = "rx", "tx", "err"; + interrupt-parent = <&intc0>; clock-frequency = <4000000>; current-speed = <115200>; + pinctrl-0 = <&uart2_tx_default &uart2_rx_default>; + pinctrl-names = "default"; status = "okay"; }; + + pinctrl: pin-controller@200 { + compatible = "microchip,dspic33-pinctrl"; + reg = <0x0200 0x37D0>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + gpioa: gpio@200 { + compatible = "microchip,dspic-gpio"; + reg = <0x0200 0x20>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpiob: gpio@214 { + compatible = "microchip,dspic-gpio"; + reg = <0x0214 0x20>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpioc: gpio@228 { + compatible = "microchip,dspic-gpio"; + reg = <0x0228 0x20>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpiod: gpio@23C { + compatible = "microchip,dspic-gpio"; + reg = <0x023C 0x20>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + uart0_tx_default: uart0_tx_default { + pinmux = ; + }; + + uart0_rx_default: uart0_rx_default { + pinmux = ; + }; + + uart1_tx_default: uart1_tx_default { + pinmux = ; + }; + + uart1_rx_default: uart1_rx_default { + pinmux = ; + }; + + uart2_tx_default: uart2_tx_default { + pinmux = ; + }; + + uart2_rx_default: uart2_rx_default { + pinmux = ; + }; + }; + }; }; diff --git a/dts/dspic/p33ak512mps512.dtsi b/dts/dspic/p33ak512mps512.dtsi new file mode 100644 index 0000000000000..4a8443e93b7b8 --- /dev/null +++ b/dts/dspic/p33ak512mps512.dtsi @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "zephyr/dt-bindings/pinctrl/mchp-p33ak512mps512-pinctrl.h" + +/ { + model = "Microchip dsPIC33A Curiosity Platform Development Board"; + compatible = "microchip,p33ak512mps512"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "microchip,dsPIC33A"; + reg = <0>; + clock-frequency = <8000000>; + status = "okay"; + cpu-power-states = <&idle>; + }; + + power-states { + idle: idle { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + min-residency-us = <1000>; + }; + }; + }; + + aliases { + soc = &soc; + }; + + soc: soc { + compatible = "microchip,p33ak512mps512-soc"; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@800000 { + compatible = "zephyr,flash"; + reg = <0x800000 0x80000>; + label = "FLASH"; + }; + + sram0: memory@4000 { + compatible = "zephyr,memory"; + reg = <0x4000 0x10000>; + label = "SRAM"; + }; + + intc0: interrupt-controller@0 { + compatible = "microchip,dspic33-intc"; + reg = <0x0 0x1>; + ie-offset = <0xC0>; + if-offset = <0x90>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + }; + + timer1: timer@1CE0 { + compatible = "microchip,dspic33-timer"; + reg = <0x1CE0 0xC>; + clock-frequency = <4000000>; + prescalar = <8>; + interrupt-parent = <&intc0>; + interrupts = <48 1>; + label = "TIMER_1"; + status = "okay"; + }; + + uart0: uart@1700 { + compatible = "microchip,dspic33-uart"; + reg = <0x1700 0x40>; + interrupts = <98 1>, <99 1>, <100 1>; + interrupt-names = "rx", "tx", "err"; + interrupt-parent = <&intc0>; + clock-frequency = <4000000>; + current-speed = <115200>; + pinctrl-0 = <&uart0_tx_default &uart0_rx_default>; + pinctrl-names = "default"; + status = "okay"; + }; + + uart1: uart@1740 { + compatible = "microchip,dspic33-uart"; + reg = <0x1740 0x40>; + interrupts = <102 1>, <103 1>, <104 1>; + interrupt-names = "rx", "tx", "err"; + interrupt-parent = <&intc0>; + clock-frequency = <4000000>; + current-speed = <115200>; + pinctrl-0 = <&uart1_tx_default &uart1_rx_default>; + pinctrl-names = "default"; + status = "okay"; + }; + + uart2: uart@1780 { + compatible = "microchip,dspic33-uart"; + reg = <0x1780 0x40>; + interrupts = <106 1>, <107 1>, <108 1>; + interrupt-names = "rx", "tx", "err"; + interrupt-parent = <&intc0>; + clock-frequency = <4000000>; + current-speed = <115200>; + pinctrl-0 = <&uart2_tx_default &uart2_rx_default>; + pinctrl-names = "default"; + status = "okay"; + }; + + pinctrl: pin-controller@200 { + compatible = "microchip,dspic33-pinctrl"; + reg = <0x0200 0x37D0>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + + gpioa: gpio@200 { + compatible = "microchip,dspic-gpio"; + reg = <0x200 0x14>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpiob: gpio@214 { + compatible = "microchip,dspic-gpio"; + reg = <0x214 0x14>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpioc: gpio@228 { + compatible = "microchip,dspic-gpio"; + reg = <0x228 0x14>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpiod: gpio@23C { + compatible = "microchip,dspic-gpio"; + reg = <0x23C 0x14>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpioe: gpio@250 { + compatible = "microchip,dspic-gpio"; + reg = <0x250 0x14>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpiof: gpio@264 { + compatible = "microchip,dspic-gpio"; + reg = <0x264 0x14>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpiog: gpio@278 { + compatible = "microchip,dspic-gpio"; + reg = <0x278 0x14>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + gpioh: gpio@28C { + compatible = "microchip,dspic-gpio"; + reg = <0x28C 0x14>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + uart0_tx_default: uart0_tx_default { + pinmux = ; + }; + + uart0_rx_default: uart0_rx_default { + pinmux = ; + }; + + uart1_tx_default: uart1_tx_default { + pinmux = ; + }; + + uart1_rx_default: uart1_rx_default { + pinmux = ; + }; + + uart2_tx_default: uart2_tx_default { + pinmux = ; + }; + + uart2_rx_default: uart2_rx_default { + pinmux = ; + }; + }; + }; +}; diff --git a/include/zephyr/arch/dspic/arch.h b/include/zephyr/arch/dspic/arch.h index 0d01867f5bdc0..fb2ddbd41f6a0 100644 --- a/include/zephyr/arch/dspic/arch.h +++ b/include/zephyr/arch/dspic/arch.h @@ -19,13 +19,13 @@ #define ARCH_STACK_PTR_ALIGN 4 -#define IRQ_KEY_ILR_IRQ_MASK 0x7 - -#define DSPIC_STATUS_DEFAULT 0 +#define STATUS_CTX_MASK 0x00070000 +#define IRQ_KEY_ILR_IRQ_MASK 0x7u #define DSPIC_PRIORITY_BITS 3u #define DSPIC_PRIORITY_WIDTH DSPIC_PRIORITY_BITS + 1u #define DSPIC_IRQ_PER_REG 8u #define DSPIC_PRIORITY_MASK ((1u << DSPIC_PRIORITY_BITS) - 1u) + #ifndef _ASMLANGUAGE #include #ifdef __cplusplus @@ -36,6 +36,8 @@ void arch_irq_enable(unsigned int irq); void arch_irq_disable(unsigned int irq); int arch_irq_is_enabled(unsigned int irq); void z_irq_spurious(const void *unused); +bool arch_dspic_irq_isset(unsigned int irq); +void z_dspic_enter_irq(int irq); /* dsPIC has no MMU, so device_map() is replaced with a direct assignment */ #define device_map(virt, phys, size, flags) *(virt) = (phys) @@ -79,27 +81,31 @@ static ALWAYS_INLINE void z_dspic_irq_priority_set(unsigned int irq, unsigned in static ALWAYS_INLINE void arch_irq_unlock(unsigned int key) { - __builtin_write_DISICTL(key & IRQ_KEY_ILR_IRQ_MASK); - __builtin_enable_interrupts(); + if (key) { + __builtin_enable_interrupts(); + } } static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key) { - return ((key & IRQ_KEY_ILR_IRQ_MASK) == IRQ_KEY_ILR_IRQ_MASK) ? false : true; + return key; } static ALWAYS_INLINE unsigned int arch_irq_lock(void) { volatile unsigned int key; - key = __builtin_write_DISICTL(IRQ_KEY_ILR_IRQ_MASK); + key = INTCON1bits.GIE; __builtin_disable_interrupts(); return key; } static ALWAYS_INLINE bool arch_is_in_isr(void) { - return ((INTTREGbits.VECNUM) ? (true) : (false)); + uint32_t status_reg; + + __asm__ volatile("mov.l sr, %0" : "=r"(status_reg)::); + return ((status_reg & STATUS_CTX_MASK) ? (true) : (false)); } static ALWAYS_INLINE void arch_nop(void) diff --git a/include/zephyr/arch/dspic/exception.h b/include/zephyr/arch/dspic/exception.h index f77c1e76f86c4..c8dd305294e3f 100644 --- a/include/zephyr/arch/dspic/exception.h +++ b/include/zephyr/arch/dspic/exception.h @@ -15,6 +15,7 @@ extern "C" { #endif struct arch_esf { + uint32_t SR; uint32_t PC; /* Program counter*/ uint32_t RCOUNT; /* repeat count register*/ uint32_t FSR; /* Floating point status register */ @@ -27,7 +28,6 @@ struct arch_esf { uint32_t W5; /* working register W5 */ uint32_t W6; /* working register W6 */ uint32_t W7; /* working register W7 */ - uint32_t W8; /* working register W8 */ uint32_t F0; /* Floating point register F0 */ uint32_t F1; /* Floating point register F1 */ uint32_t F2; /* Floating point register F2 */ diff --git a/include/zephyr/arch/dspic/linker.ld b/include/zephyr/arch/dspic/linker.ld index 99c689d432402..d4f42a5ff34cc 100644 --- a/include/zephyr/arch/dspic/linker.ld +++ b/include/zephyr/arch/dspic/linker.ld @@ -16,10 +16,10 @@ #include /* Define memory regions based on the original script */ -#define FLASH_BASE_ADDRESS 0x800000 -#define FLASH_SIZE 128 -#define SRAM_BASE_ADDRESS 0x4000 -#define SRAM_SIZE 16 +#define FLASH_BASE_ADDRESS CONFIG_FLASH_BASE_ADDRESS +#define FLASH_SIZE CONFIG_FLASH_SIZE +#define SRAM_BASE_ADDRESS CONFIG_SRAM_BASE_ADDRESS +#define SRAM_SIZE CONFIG_SRAM_SIZE /* Define Zephyr's standard memory region names */ #define ROMABLE_REGION program @@ -37,6 +37,12 @@ MEMORY /* Used by and documented in include/linker/intlist.ld */ IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K } +/* + * After adding gc-section option compiler was discarding __start symbol + * adding ENTRY directive avoid it from being discarded. + */ +ENTRY(__start) + SECTIONS { /* Start of the ROM-based sections */ @@ -166,2830 +172,4 @@ SECTIONS } -/* -** ============== Equates for SFR Addresses ============= -*/ -PC = 0x0; -_PC = 0x0; -_PCbits = 0x0; - SPLIM = 0x4; -_SPLIM = 0x4; -_SPLIMbits = 0x4; - RCOUNT = 0x8; -_RCOUNT = 0x8; - DISIIPL = 0xC; -_DISIIPL = 0xC; -_DISIIPLbits = 0xC; - CORCON = 0x10; -_CORCON = 0x10; -_CORCONbits = 0x10; - MODCON = 0x14; -_MODCON = 0x14; -_MODCONbits = 0x14; - XMODSRT = 0x18; -_XMODSRT = 0x18; -_XMODSRTbits = 0x18; - XMODEND = 0x1C; -_XMODEND = 0x1C; -_XMODENDbits = 0x1C; - YMODSRT = 0x20; -_YMODSRT = 0x20; -_YMODSRTbits = 0x20; - YMODEND = 0x24; -_YMODEND = 0x24; -_YMODENDbits = 0x24; - XBREV = 0x28; -_XBREV = 0x28; -_XBREVbits = 0x28; - PCTRAP = 0x2C; -_PCTRAP = 0x2C; -_PCTRAPbits = 0x2C; - FEX = 0x30; -_FEX = 0x30; - FEX2 = 0x34; -_FEX2 = 0x34; - PCHOLD = 0x38; -_PCHOLD = 0x38; -_PCHOLDbits = 0x38; - VFA = 0x3C; -_VFA = 0x3C; -_VFAbits = 0x3C; - INTCON1 = 0x70; -_INTCON1 = 0x70; -_INTCON1bits = 0x70; - INTCON2 = 0x74; -_INTCON2 = 0x74; -_INTCON2bits = 0x74; - INTCON3 = 0x78; -_INTCON3 = 0x78; -_INTCON3bits = 0x78; - INTCON4 = 0x7C; -_INTCON4 = 0x7C; -_INTCON4bits = 0x7C; - INTCON5 = 0x80; -_INTCON5 = 0x80; -_INTCON5bits = 0x80; - INTTREG = 0x84; -_INTTREG = 0x84; -_INTTREGbits = 0x84; - IVTBASE = 0x88; -_IVTBASE = 0x88; - IVTCREG = 0x8C; -_IVTCREG = 0x8C; -_IVTCREGbits = 0x8C; - IFS0 = 0x90; -_IFS0 = 0x90; -_IFS0bits = 0x90; - IFS1 = 0x94; -_IFS1 = 0x94; -_IFS1bits = 0x94; - IFS2 = 0x98; -_IFS2 = 0x98; -_IFS2bits = 0x98; - IFS3 = 0x9C; -_IFS3 = 0x9C; -_IFS3bits = 0x9C; - IFS4 = 0xA0; -_IFS4 = 0xA0; -_IFS4bits = 0xA0; - IFS5 = 0xA4; -_IFS5 = 0xA4; -_IFS5bits = 0xA4; - IFS6 = 0xA8; -_IFS6 = 0xA8; -_IFS6bits = 0xA8; - IFS7 = 0xAC; -_IFS7 = 0xAC; -_IFS7bits = 0xAC; - IFS8 = 0xB0; -_IFS8 = 0xB0; -_IFS8bits = 0xB0; - IEC0 = 0xB4; -_IEC0 = 0xB4; -_IEC0bits = 0xB4; - IEC1 = 0xB8; -_IEC1 = 0xB8; -_IEC1bits = 0xB8; - IEC2 = 0xBC; -_IEC2 = 0xBC; -_IEC2bits = 0xBC; - IEC3 = 0xC0; -_IEC3 = 0xC0; -_IEC3bits = 0xC0; - IEC4 = 0xC4; -_IEC4 = 0xC4; -_IEC4bits = 0xC4; - IEC5 = 0xC8; -_IEC5 = 0xC8; -_IEC5bits = 0xC8; - IEC6 = 0xCC; -_IEC6 = 0xCC; -_IEC6bits = 0xCC; - IEC7 = 0xD0; -_IEC7 = 0xD0; -_IEC7bits = 0xD0; - IEC8 = 0xD4; -_IEC8 = 0xD4; -_IEC8bits = 0xD4; - IPC0 = 0xD8; -_IPC0 = 0xD8; -_IPC0bits = 0xD8; - IPC1 = 0xDC; -_IPC1 = 0xDC; -_IPC1bits = 0xDC; - IPC2 = 0xE0; -_IPC2 = 0xE0; -_IPC2bits = 0xE0; - IPC3 = 0xE4; -_IPC3 = 0xE4; -_IPC3bits = 0xE4; - IPC4 = 0xE8; -_IPC4 = 0xE8; -_IPC4bits = 0xE8; - IPC5 = 0xEC; -_IPC5 = 0xEC; -_IPC5bits = 0xEC; - IPC6 = 0xF0; -_IPC6 = 0xF0; -_IPC6bits = 0xF0; - IPC7 = 0xF4; -_IPC7 = 0xF4; -_IPC7bits = 0xF4; - IPC8 = 0xF8; -_IPC8 = 0xF8; -_IPC8bits = 0xF8; - IPC9 = 0xFC; -_IPC9 = 0xFC; -_IPC9bits = 0xFC; - IPC10 = 0x100; -_IPC10 = 0x100; -_IPC10bits = 0x100; - IPC11 = 0x104; -_IPC11 = 0x104; -_IPC11bits = 0x104; - IPC12 = 0x108; -_IPC12 = 0x108; -_IPC12bits = 0x108; - IPC13 = 0x10C; -_IPC13 = 0x10C; -_IPC13bits = 0x10C; - IPC14 = 0x110; -_IPC14 = 0x110; -_IPC14bits = 0x110; - IPC15 = 0x114; -_IPC15 = 0x114; -_IPC15bits = 0x114; - IPC16 = 0x118; -_IPC16 = 0x118; -_IPC16bits = 0x118; - IPC17 = 0x11C; -_IPC17 = 0x11C; -_IPC17bits = 0x11C; - IPC18 = 0x120; -_IPC18 = 0x120; -_IPC18bits = 0x120; - IPC19 = 0x124; -_IPC19 = 0x124; -_IPC19bits = 0x124; - IPC20 = 0x128; -_IPC20 = 0x128; -_IPC20bits = 0x128; - IPC21 = 0x12C; -_IPC21 = 0x12C; -_IPC21bits = 0x12C; - IPC22 = 0x130; -_IPC22 = 0x130; -_IPC22bits = 0x130; - IPC23 = 0x134; -_IPC23 = 0x134; -_IPC23bits = 0x134; - IPC24 = 0x138; -_IPC24 = 0x138; -_IPC24bits = 0x138; - IPC25 = 0x13C; -_IPC25 = 0x13C; -_IPC25bits = 0x13C; - IPC26 = 0x140; -_IPC26 = 0x140; -_IPC26bits = 0x140; - IPC27 = 0x144; -_IPC27 = 0x144; -_IPC27bits = 0x144; - IPC28 = 0x148; -_IPC28 = 0x148; -_IPC28bits = 0x148; - IPC29 = 0x14C; -_IPC29 = 0x14C; -_IPC29bits = 0x14C; - IPC35 = 0x160; -_IPC35 = 0x160; -_IPC35bits = 0x160; - PORTA = 0x200; -_PORTA = 0x200; -_PORTAbits = 0x200; - LATA = 0x204; -_LATA = 0x204; -_LATAbits = 0x204; - TRISA = 0x208; -_TRISA = 0x208; -_TRISAbits = 0x208; - CNSTATA = 0x20C; -_CNSTATA = 0x20C; -_CNSTATAbits = 0x20C; - CNFA = 0x210; -_CNFA = 0x210; -_CNFAbits = 0x210; - PORTB = 0x214; -_PORTB = 0x214; -_PORTBbits = 0x214; - LATB = 0x218; -_LATB = 0x218; -_LATBbits = 0x218; - TRISB = 0x21C; -_TRISB = 0x21C; -_TRISBbits = 0x21C; - CNSTATB = 0x220; -_CNSTATB = 0x220; -_CNSTATBbits = 0x220; - CNFB = 0x224; -_CNFB = 0x224; -_CNFBbits = 0x224; - PORTC = 0x228; -_PORTC = 0x228; -_PORTCbits = 0x228; - LATC = 0x22C; -_LATC = 0x22C; -_LATCbits = 0x22C; - TRISC = 0x230; -_TRISC = 0x230; -_TRISCbits = 0x230; - CNSTATC = 0x234; -_CNSTATC = 0x234; -_CNSTATCbits = 0x234; - CNFC = 0x238; -_CNFC = 0x238; -_CNFCbits = 0x238; - PORTD = 0x23C; -_PORTD = 0x23C; -_PORTDbits = 0x23C; - LATD = 0x240; -_LATD = 0x240; -_LATDbits = 0x240; - TRISD = 0x244; -_TRISD = 0x244; -_TRISDbits = 0x244; - CNSTATD = 0x248; -_CNSTATD = 0x248; -_CNSTATDbits = 0x248; - CNFD = 0x24C; -_CNFD = 0x24C; -_CNFDbits = 0x24C; - CRCCON = 0x2C8; -_CRCCON = 0x2C8; -_CRCCONbits = 0x2C8; - CRCXOR = 0x2CC; -_CRCXOR = 0x2CC; -_CRCXORbits = 0x2CC; - CRCDAT = 0x2D0; -_CRCDAT = 0x2D0; - CRCWDAT = 0x2D4; -_CRCWDAT = 0x2D4; - UCPROT = 0x2E0; -_UCPROT = 0x2E0; -_UCPROTbits = 0x2E0; - IRTCTRL = 0x2E4; -_IRTCTRL = 0x2E4; -_IRTCTRLbits = 0x2E4; - IRTSTAT = 0x2E8; -_IRTSTAT = 0x2E8; - PR0CTRL = 0x300; -_PR0CTRL = 0x300; -_PR0CTRLbits = 0x300; - PR0ST = 0x304; -_PR0ST = 0x304; -_PR0STbits = 0x304; - PR0END = 0x308; -_PR0END = 0x308; -_PR0ENDbits = 0x308; - PR0LOCK = 0x30C; -_PR0LOCK = 0x30C; -_PR0LOCKbits = 0x30C; - PR1CTRL = 0x310; -_PR1CTRL = 0x310; -_PR1CTRLbits = 0x310; - PR1ST = 0x314; -_PR1ST = 0x314; -_PR1STbits = 0x314; - PR1END = 0x318; -_PR1END = 0x318; -_PR1ENDbits = 0x318; - PR1LOCK = 0x31C; -_PR1LOCK = 0x31C; -_PR1LOCKbits = 0x31C; - PR2CTRL = 0x320; -_PR2CTRL = 0x320; -_PR2CTRLbits = 0x320; - PR2ST = 0x324; -_PR2ST = 0x324; -_PR2STbits = 0x324; - PR2END = 0x328; -_PR2END = 0x328; -_PR2ENDbits = 0x328; - PR2LOCK = 0x32C; -_PR2LOCK = 0x32C; -_PR2LOCKbits = 0x32C; - PR3CTRL = 0x330; -_PR3CTRL = 0x330; -_PR3CTRLbits = 0x330; - PR3ST = 0x334; -_PR3ST = 0x334; -_PR3STbits = 0x334; - PR3END = 0x338; -_PR3END = 0x338; -_PR3ENDbits = 0x338; - PR3LOCK = 0x33C; -_PR3LOCK = 0x33C; -_PR3LOCKbits = 0x33C; - PR4CTRL = 0x340; -_PR4CTRL = 0x340; -_PR4CTRLbits = 0x340; - PR4ST = 0x344; -_PR4ST = 0x344; -_PR4STbits = 0x344; - PR4END = 0x348; -_PR4END = 0x348; -_PR4ENDbits = 0x348; - PR4LOCK = 0x34C; -_PR4LOCK = 0x34C; -_PR4LOCKbits = 0x34C; - PR5CTRL = 0x350; -_PR5CTRL = 0x350; -_PR5CTRLbits = 0x350; - PR5ST = 0x354; -_PR5ST = 0x354; -_PR5STbits = 0x354; - PR5END = 0x358; -_PR5END = 0x358; -_PR5ENDbits = 0x358; - PR5LOCK = 0x35C; -_PR5LOCK = 0x35C; -_PR5LOCKbits = 0x35C; - PR6CTRL = 0x360; -_PR6CTRL = 0x360; -_PR6CTRLbits = 0x360; - PR6ST = 0x364; -_PR6ST = 0x364; -_PR6STbits = 0x364; - PR6END = 0x368; -_PR6END = 0x368; -_PR6ENDbits = 0x368; - PR6LOCK = 0x36C; -_PR6LOCK = 0x36C; -_PR6LOCKbits = 0x36C; - PR7CTRL = 0x370; -_PR7CTRL = 0x370; -_PR7CTRLbits = 0x370; - PR7ST = 0x374; -_PR7ST = 0x374; -_PR7STbits = 0x374; - PR7END = 0x378; -_PR7END = 0x378; -_PR7ENDbits = 0x378; - PR7LOCK = 0x37C; -_PR7LOCK = 0x37C; -_PR7LOCKbits = 0x37C; - BMXINITPR = 0x770; -_BMXINITPR = 0x770; -_BMXINITPRbits = 0x770; - BMXIRAML = 0x774; -_BMXIRAML = 0x774; - BMXIRAMH = 0x778; -_BMXIRAMH = 0x778; - BMXXDATERR = 0x77C; -_BMXXDATERR = 0x77C; -_BMXXDATERRbits = 0x77C; - BMXYDATERR = 0x780; -_BMXYDATERR = 0x780; -_BMXYDATERRbits = 0x780; - BMXDMAERR = 0x784; -_BMXDMAERR = 0x784; -_BMXDMAERRbits = 0x784; - BMXNVMERR = 0x788; -_BMXNVMERR = 0x788; -_BMXNVMERRbits = 0x788; - BMXICDERR = 0x78C; -_BMXICDERR = 0x78C; -_BMXICDERRbits = 0x78C; - AD1CON = 0x800; -_AD1CON = 0x800; -_AD1CONbits = 0x800; - AD1DATAOVR = 0x804; -_AD1DATAOVR = 0x804; - AD1STAT = 0x808; -_AD1STAT = 0x808; -_AD1STATbits = 0x808; - AD1CMPSTAT = 0x80C; -_AD1CMPSTAT = 0x80C; -_AD1CMPSTATbits = 0x80C; - AD1SWTRG = 0x810; -_AD1SWTRG = 0x810; -_AD1SWTRGbits = 0x810; - AD1CH0CON = 0x814; -_AD1CH0CON = 0x814; -_AD1CH0CONbits = 0x814; - AD1CH0DATA = 0x818; -_AD1CH0DATA = 0x818; - AD1CH0CNT = 0x81C; -_AD1CH0CNT = 0x81C; -_AD1CH0CNTbits = 0x81C; - AD1CH0CMPLO = 0x820; -_AD1CH0CMPLO = 0x820; - AD1CH0CMPHI = 0x824; -_AD1CH0CMPHI = 0x824; - AD1CH0ACC = 0x828; -_AD1CH0ACC = 0x828; - AD1CH1CON = 0x82C; -_AD1CH1CON = 0x82C; -_AD1CH1CONbits = 0x82C; - AD1CH1DATA = 0x830; -_AD1CH1DATA = 0x830; - AD1CH1CNT = 0x834; -_AD1CH1CNT = 0x834; -_AD1CH1CNTbits = 0x834; - AD1CH1CMPLO = 0x838; -_AD1CH1CMPLO = 0x838; - AD1CH1CMPHI = 0x83C; -_AD1CH1CMPHI = 0x83C; - AD1CH1ACC = 0x840; -_AD1CH1ACC = 0x840; - AD1CH2CON = 0x844; -_AD1CH2CON = 0x844; -_AD1CH2CONbits = 0x844; - AD1CH2DATA = 0x848; -_AD1CH2DATA = 0x848; - AD1CH2CNT = 0x84C; -_AD1CH2CNT = 0x84C; -_AD1CH2CNTbits = 0x84C; - AD1CH2CMPLO = 0x850; -_AD1CH2CMPLO = 0x850; - AD1CH2CMPHI = 0x854; -_AD1CH2CMPHI = 0x854; - AD1CH2ACC = 0x858; -_AD1CH2ACC = 0x858; - AD1CH3CON = 0x85C; -_AD1CH3CON = 0x85C; -_AD1CH3CONbits = 0x85C; - AD1CH3DATA = 0x860; -_AD1CH3DATA = 0x860; - AD1CH3CNT = 0x864; -_AD1CH3CNT = 0x864; -_AD1CH3CNTbits = 0x864; - AD1CH3CMPLO = 0x868; -_AD1CH3CMPLO = 0x868; - AD1CH3CMPHI = 0x86C; -_AD1CH3CMPHI = 0x86C; - AD1CH3ACC = 0x870; -_AD1CH3ACC = 0x870; - AD1CH4CON = 0x874; -_AD1CH4CON = 0x874; -_AD1CH4CONbits = 0x874; - AD1CH4DATA = 0x878; -_AD1CH4DATA = 0x878; - AD1CH4CNT = 0x87C; -_AD1CH4CNT = 0x87C; -_AD1CH4CNTbits = 0x87C; - AD1CH4CMPLO = 0x880; -_AD1CH4CMPLO = 0x880; - AD1CH4CMPHI = 0x884; -_AD1CH4CMPHI = 0x884; - AD1CH4ACC = 0x888; -_AD1CH4ACC = 0x888; - AD1CH5CON = 0x88C; -_AD1CH5CON = 0x88C; -_AD1CH5CONbits = 0x88C; - AD1CH5DATA = 0x890; -_AD1CH5DATA = 0x890; - AD1CH5CNT = 0x894; -_AD1CH5CNT = 0x894; -_AD1CH5CNTbits = 0x894; - AD1CH5CMPLO = 0x898; -_AD1CH5CMPLO = 0x898; - AD1CH5CMPHI = 0x89C; -_AD1CH5CMPHI = 0x89C; - AD1CH5ACC = 0x8A0; -_AD1CH5ACC = 0x8A0; - AD1CH6CON = 0x8A4; -_AD1CH6CON = 0x8A4; -_AD1CH6CONbits = 0x8A4; - AD1CH6DATA = 0x8A8; -_AD1CH6DATA = 0x8A8; - AD1CH6CNT = 0x8AC; -_AD1CH6CNT = 0x8AC; -_AD1CH6CNTbits = 0x8AC; - AD1CH6CMPLO = 0x8B0; -_AD1CH6CMPLO = 0x8B0; - AD1CH6CMPHI = 0x8B4; -_AD1CH6CMPHI = 0x8B4; - AD1CH6ACC = 0x8B8; -_AD1CH6ACC = 0x8B8; - AD1CH7CON = 0x8BC; -_AD1CH7CON = 0x8BC; -_AD1CH7CONbits = 0x8BC; - AD1CH7DATA = 0x8C0; -_AD1CH7DATA = 0x8C0; - AD1CH7CNT = 0x8C4; -_AD1CH7CNT = 0x8C4; -_AD1CH7CNTbits = 0x8C4; - AD1CH7CMPLO = 0x8C8; -_AD1CH7CMPLO = 0x8C8; - AD1CH7CMPHI = 0x8CC; -_AD1CH7CMPHI = 0x8CC; - AD1CH7ACC = 0x8D0; -_AD1CH7ACC = 0x8D0; - AD1CH8CON = 0x8D4; -_AD1CH8CON = 0x8D4; -_AD1CH8CONbits = 0x8D4; - AD1CH8DATA = 0x8D8; -_AD1CH8DATA = 0x8D8; - AD1CH8CNT = 0x8DC; -_AD1CH8CNT = 0x8DC; -_AD1CH8CNTbits = 0x8DC; - AD1CH8CMPLO = 0x8E0; -_AD1CH8CMPLO = 0x8E0; - AD1CH8CMPHI = 0x8E4; -_AD1CH8CMPHI = 0x8E4; - AD1CH8ACC = 0x8E8; -_AD1CH8ACC = 0x8E8; - AD1CH9CON = 0x8EC; -_AD1CH9CON = 0x8EC; -_AD1CH9CONbits = 0x8EC; - AD1CH9DATA = 0x8F0; -_AD1CH9DATA = 0x8F0; - AD1CH9CNT = 0x8F4; -_AD1CH9CNT = 0x8F4; -_AD1CH9CNTbits = 0x8F4; - AD1CH9CMPLO = 0x8F8; -_AD1CH9CMPLO = 0x8F8; - AD1CH9CMPHI = 0x8FC; -_AD1CH9CMPHI = 0x8FC; - AD1CH9ACC = 0x900; -_AD1CH9ACC = 0x900; - AD1CH10CON = 0x904; -_AD1CH10CON = 0x904; -_AD1CH10CONbits = 0x904; - AD1CH10DATA = 0x908; -_AD1CH10DATA = 0x908; - AD1CH10CNT = 0x90C; -_AD1CH10CNT = 0x90C; -_AD1CH10CNTbits = 0x90C; - AD1CH10CMPLO = 0x910; -_AD1CH10CMPLO = 0x910; - AD1CH10CMPHI = 0x914; -_AD1CH10CMPHI = 0x914; - AD1CH10ACC = 0x918; -_AD1CH10ACC = 0x918; - AD1CH11CON = 0x91C; -_AD1CH11CON = 0x91C; -_AD1CH11CONbits = 0x91C; - AD1CH11DATA = 0x920; -_AD1CH11DATA = 0x920; - AD1CH11CNT = 0x924; -_AD1CH11CNT = 0x924; -_AD1CH11CNTbits = 0x924; - AD1CH11CMPLO = 0x928; -_AD1CH11CMPLO = 0x928; - AD1CH11CMPHI = 0x92C; -_AD1CH11CMPHI = 0x92C; - AD1CH11ACC = 0x930; -_AD1CH11ACC = 0x930; - AD1CH12CON = 0x934; -_AD1CH12CON = 0x934; -_AD1CH12CONbits = 0x934; - AD1CH12DATA = 0x938; -_AD1CH12DATA = 0x938; - AD1CH12CNT = 0x93C; -_AD1CH12CNT = 0x93C; -_AD1CH12CNTbits = 0x93C; - AD1CH12CMPLO = 0x940; -_AD1CH12CMPLO = 0x940; - AD1CH12CMPHI = 0x944; -_AD1CH12CMPHI = 0x944; - AD1CH12ACC = 0x948; -_AD1CH12ACC = 0x948; - AD1CH13CON = 0x94C; -_AD1CH13CON = 0x94C; -_AD1CH13CONbits = 0x94C; - AD1CH13DATA = 0x950; -_AD1CH13DATA = 0x950; - AD1CH13CNT = 0x954; -_AD1CH13CNT = 0x954; -_AD1CH13CNTbits = 0x954; - AD1CH13CMPLO = 0x958; -_AD1CH13CMPLO = 0x958; - AD1CH13CMPHI = 0x95C; -_AD1CH13CMPHI = 0x95C; - AD1CH13ACC = 0x960; -_AD1CH13ACC = 0x960; - AD1CH14CON = 0x964; -_AD1CH14CON = 0x964; -_AD1CH14CONbits = 0x964; - AD1CH14DATA = 0x968; -_AD1CH14DATA = 0x968; - AD1CH14CNT = 0x96C; -_AD1CH14CNT = 0x96C; -_AD1CH14CNTbits = 0x96C; - AD1CH14CMPLO = 0x970; -_AD1CH14CMPLO = 0x970; - AD1CH14CMPHI = 0x974; -_AD1CH14CMPHI = 0x974; - AD1CH14ACC = 0x978; -_AD1CH14ACC = 0x978; - AD1CH15CON = 0x97C; -_AD1CH15CON = 0x97C; -_AD1CH15CONbits = 0x97C; - AD1CH15DATA = 0x980; -_AD1CH15DATA = 0x980; - AD1CH15CNT = 0x984; -_AD1CH15CNT = 0x984; -_AD1CH15CNTbits = 0x984; - AD1CH15CMPLO = 0x988; -_AD1CH15CMPLO = 0x988; - AD1CH15CMPHI = 0x98C; -_AD1CH15CMPHI = 0x98C; - AD1CH15ACC = 0x990; -_AD1CH15ACC = 0x990; - AD1CH16CON = 0x994; -_AD1CH16CON = 0x994; -_AD1CH16CONbits = 0x994; - AD1CH16DATA = 0x998; -_AD1CH16DATA = 0x998; - AD1CH16CNT = 0x99C; -_AD1CH16CNT = 0x99C; -_AD1CH16CNTbits = 0x99C; - AD1CH16CMPLO = 0x9A0; -_AD1CH16CMPLO = 0x9A0; - AD1CH16CMPHI = 0x9A4; -_AD1CH16CMPHI = 0x9A4; - AD1CH16ACC = 0x9A8; -_AD1CH16ACC = 0x9A8; - AD1CH17CON = 0x9AC; -_AD1CH17CON = 0x9AC; -_AD1CH17CONbits = 0x9AC; - AD1CH17DATA = 0x9B0; -_AD1CH17DATA = 0x9B0; - AD1CH17CNT = 0x9B4; -_AD1CH17CNT = 0x9B4; -_AD1CH17CNTbits = 0x9B4; - AD1CH17CMPLO = 0x9B8; -_AD1CH17CMPLO = 0x9B8; - AD1CH17CMPHI = 0x9BC; -_AD1CH17CMPHI = 0x9BC; - AD1CH17ACC = 0x9C0; -_AD1CH17ACC = 0x9C0; - AD1CH18CON = 0x9C4; -_AD1CH18CON = 0x9C4; -_AD1CH18CONbits = 0x9C4; - AD1CH18DATA = 0x9C8; -_AD1CH18DATA = 0x9C8; - AD1CH18CNT = 0x9CC; -_AD1CH18CNT = 0x9CC; -_AD1CH18CNTbits = 0x9CC; - AD1CH18CMPLO = 0x9D0; -_AD1CH18CMPLO = 0x9D0; - AD1CH18CMPHI = 0x9D4; -_AD1CH18CMPHI = 0x9D4; - AD1CH18ACC = 0x9D8; -_AD1CH18ACC = 0x9D8; - AD1CH19CON = 0x9DC; -_AD1CH19CON = 0x9DC; -_AD1CH19CONbits = 0x9DC; - AD1CH19DATA = 0x9E0; -_AD1CH19DATA = 0x9E0; - AD1CH19CNT = 0x9E4; -_AD1CH19CNT = 0x9E4; -_AD1CH19CNTbits = 0x9E4; - AD1CH19CMPLO = 0x9E8; -_AD1CH19CMPLO = 0x9E8; - AD1CH19CMPHI = 0x9EC; -_AD1CH19CMPHI = 0x9EC; - AD1CH19ACC = 0x9F0; -_AD1CH19ACC = 0x9F0; - AD2CON = 0xA00; -_AD2CON = 0xA00; -_AD2CONbits = 0xA00; - AD2DATAOVR = 0xA04; -_AD2DATAOVR = 0xA04; - AD2STAT = 0xA08; -_AD2STAT = 0xA08; -_AD2STATbits = 0xA08; - AD2CMPSTAT = 0xA0C; -_AD2CMPSTAT = 0xA0C; -_AD2CMPSTATbits = 0xA0C; - AD2SWTRG = 0xA10; -_AD2SWTRG = 0xA10; -_AD2SWTRGbits = 0xA10; - AD2CH0CON = 0xA14; -_AD2CH0CON = 0xA14; -_AD2CH0CONbits = 0xA14; - AD2CH0DATA = 0xA18; -_AD2CH0DATA = 0xA18; - AD2CH0CNT = 0xA1C; -_AD2CH0CNT = 0xA1C; -_AD2CH0CNTbits = 0xA1C; - AD2CH0CMPLO = 0xA20; -_AD2CH0CMPLO = 0xA20; - AD2CH0CMPHI = 0xA24; -_AD2CH0CMPHI = 0xA24; - AD2CH0ACC = 0xA28; -_AD2CH0ACC = 0xA28; - AD2CH1CON = 0xA2C; -_AD2CH1CON = 0xA2C; -_AD2CH1CONbits = 0xA2C; - AD2CH1DATA = 0xA30; -_AD2CH1DATA = 0xA30; - AD2CH1CNT = 0xA34; -_AD2CH1CNT = 0xA34; -_AD2CH1CNTbits = 0xA34; - AD2CH1CMPLO = 0xA38; -_AD2CH1CMPLO = 0xA38; - AD2CH1CMPHI = 0xA3C; -_AD2CH1CMPHI = 0xA3C; - AD2CH1ACC = 0xA40; -_AD2CH1ACC = 0xA40; - AD2CH2CON = 0xA44; -_AD2CH2CON = 0xA44; -_AD2CH2CONbits = 0xA44; - AD2CH2DATA = 0xA48; -_AD2CH2DATA = 0xA48; - AD2CH2CNT = 0xA4C; -_AD2CH2CNT = 0xA4C; -_AD2CH2CNTbits = 0xA4C; - AD2CH2CMPLO = 0xA50; -_AD2CH2CMPLO = 0xA50; - AD2CH2CMPHI = 0xA54; -_AD2CH2CMPHI = 0xA54; - AD2CH2ACC = 0xA58; -_AD2CH2ACC = 0xA58; - AD2CH3CON = 0xA5C; -_AD2CH3CON = 0xA5C; -_AD2CH3CONbits = 0xA5C; - AD2CH3DATA = 0xA60; -_AD2CH3DATA = 0xA60; - AD2CH3CNT = 0xA64; -_AD2CH3CNT = 0xA64; -_AD2CH3CNTbits = 0xA64; - AD2CH3CMPLO = 0xA68; -_AD2CH3CMPLO = 0xA68; - AD2CH3CMPHI = 0xA6C; -_AD2CH3CMPHI = 0xA6C; - AD2CH3ACC = 0xA70; -_AD2CH3ACC = 0xA70; - AD2CH4CON = 0xA74; -_AD2CH4CON = 0xA74; -_AD2CH4CONbits = 0xA74; - AD2CH4DATA = 0xA78; -_AD2CH4DATA = 0xA78; - AD2CH4CNT = 0xA7C; -_AD2CH4CNT = 0xA7C; -_AD2CH4CNTbits = 0xA7C; - AD2CH4CMPLO = 0xA80; -_AD2CH4CMPLO = 0xA80; - AD2CH4CMPHI = 0xA84; -_AD2CH4CMPHI = 0xA84; - AD2CH4ACC = 0xA88; -_AD2CH4ACC = 0xA88; - AD2CH5CON = 0xA8C; -_AD2CH5CON = 0xA8C; -_AD2CH5CONbits = 0xA8C; - AD2CH5DATA = 0xA90; -_AD2CH5DATA = 0xA90; - AD2CH5CNT = 0xA94; -_AD2CH5CNT = 0xA94; -_AD2CH5CNTbits = 0xA94; - AD2CH5CMPLO = 0xA98; -_AD2CH5CMPLO = 0xA98; - AD2CH5CMPHI = 0xA9C; -_AD2CH5CMPHI = 0xA9C; - AD2CH5ACC = 0xAA0; -_AD2CH5ACC = 0xAA0; - AD2CH6CON = 0xAA4; -_AD2CH6CON = 0xAA4; -_AD2CH6CONbits = 0xAA4; - AD2CH6DATA = 0xAA8; -_AD2CH6DATA = 0xAA8; - AD2CH6CNT = 0xAAC; -_AD2CH6CNT = 0xAAC; -_AD2CH6CNTbits = 0xAAC; - AD2CH6CMPLO = 0xAB0; -_AD2CH6CMPLO = 0xAB0; - AD2CH6CMPHI = 0xAB4; -_AD2CH6CMPHI = 0xAB4; - AD2CH6ACC = 0xAB8; -_AD2CH6ACC = 0xAB8; - AD2CH7CON = 0xABC; -_AD2CH7CON = 0xABC; -_AD2CH7CONbits = 0xABC; - AD2CH7DATA = 0xAC0; -_AD2CH7DATA = 0xAC0; - AD2CH7CNT = 0xAC4; -_AD2CH7CNT = 0xAC4; -_AD2CH7CNTbits = 0xAC4; - AD2CH7CMPLO = 0xAC8; -_AD2CH7CMPLO = 0xAC8; - AD2CH7CMPHI = 0xACC; -_AD2CH7CMPHI = 0xACC; - AD2CH7ACC = 0xAD0; -_AD2CH7ACC = 0xAD0; - AD2CH8CON = 0xAD4; -_AD2CH8CON = 0xAD4; -_AD2CH8CONbits = 0xAD4; - AD2CH8DATA = 0xAD8; -_AD2CH8DATA = 0xAD8; - AD2CH8CNT = 0xADC; -_AD2CH8CNT = 0xADC; -_AD2CH8CNTbits = 0xADC; - AD2CH8CMPLO = 0xAE0; -_AD2CH8CMPLO = 0xAE0; - AD2CH8CMPHI = 0xAE4; -_AD2CH8CMPHI = 0xAE4; - AD2CH8ACC = 0xAE8; -_AD2CH8ACC = 0xAE8; - AD2CH9CON = 0xAEC; -_AD2CH9CON = 0xAEC; -_AD2CH9CONbits = 0xAEC; - AD2CH9DATA = 0xAF0; -_AD2CH9DATA = 0xAF0; - AD2CH9CNT = 0xAF4; -_AD2CH9CNT = 0xAF4; -_AD2CH9CNTbits = 0xAF4; - AD2CH9CMPLO = 0xAF8; -_AD2CH9CMPLO = 0xAF8; - AD2CH9CMPHI = 0xAFC; -_AD2CH9CMPHI = 0xAFC; - AD2CH9ACC = 0xB00; -_AD2CH9ACC = 0xB00; - AD2CH10CON = 0xB04; -_AD2CH10CON = 0xB04; -_AD2CH10CONbits = 0xB04; - AD2CH10DATA = 0xB08; -_AD2CH10DATA = 0xB08; - AD2CH10CNT = 0xB0C; -_AD2CH10CNT = 0xB0C; -_AD2CH10CNTbits = 0xB0C; - AD2CH10CMPLO = 0xB10; -_AD2CH10CMPLO = 0xB10; - AD2CH10CMPHI = 0xB14; -_AD2CH10CMPHI = 0xB14; - AD2CH10ACC = 0xB18; -_AD2CH10ACC = 0xB18; - AD2CH11CON = 0xB1C; -_AD2CH11CON = 0xB1C; -_AD2CH11CONbits = 0xB1C; - AD2CH11DATA = 0xB20; -_AD2CH11DATA = 0xB20; - AD2CH11CNT = 0xB24; -_AD2CH11CNT = 0xB24; -_AD2CH11CNTbits = 0xB24; - AD2CH11CMPLO = 0xB28; -_AD2CH11CMPLO = 0xB28; - AD2CH11CMPHI = 0xB2C; -_AD2CH11CMPHI = 0xB2C; - AD2CH11ACC = 0xB30; -_AD2CH11ACC = 0xB30; - AD2CH12CON = 0xB34; -_AD2CH12CON = 0xB34; -_AD2CH12CONbits = 0xB34; - AD2CH12DATA = 0xB38; -_AD2CH12DATA = 0xB38; - AD2CH12CNT = 0xB3C; -_AD2CH12CNT = 0xB3C; -_AD2CH12CNTbits = 0xB3C; - AD2CH12CMPLO = 0xB40; -_AD2CH12CMPLO = 0xB40; - AD2CH12CMPHI = 0xB44; -_AD2CH12CMPHI = 0xB44; - AD2CH12ACC = 0xB48; -_AD2CH12ACC = 0xB48; - AD2CH13CON = 0xB4C; -_AD2CH13CON = 0xB4C; -_AD2CH13CONbits = 0xB4C; - AD2CH13DATA = 0xB50; -_AD2CH13DATA = 0xB50; - AD2CH13CNT = 0xB54; -_AD2CH13CNT = 0xB54; -_AD2CH13CNTbits = 0xB54; - AD2CH13CMPLO = 0xB58; -_AD2CH13CMPLO = 0xB58; - AD2CH13CMPHI = 0xB5C; -_AD2CH13CMPHI = 0xB5C; - AD2CH13ACC = 0xB60; -_AD2CH13ACC = 0xB60; - AD2CH14CON = 0xB64; -_AD2CH14CON = 0xB64; -_AD2CH14CONbits = 0xB64; - AD2CH14DATA = 0xB68; -_AD2CH14DATA = 0xB68; - AD2CH14CNT = 0xB6C; -_AD2CH14CNT = 0xB6C; -_AD2CH14CNTbits = 0xB6C; - AD2CH14CMPLO = 0xB70; -_AD2CH14CMPLO = 0xB70; - AD2CH14CMPHI = 0xB74; -_AD2CH14CMPHI = 0xB74; - AD2CH14ACC = 0xB78; -_AD2CH14ACC = 0xB78; - AD2CH15CON = 0xB7C; -_AD2CH15CON = 0xB7C; -_AD2CH15CONbits = 0xB7C; - AD2CH15DATA = 0xB80; -_AD2CH15DATA = 0xB80; - AD2CH15CNT = 0xB84; -_AD2CH15CNT = 0xB84; -_AD2CH15CNTbits = 0xB84; - AD2CH15CMPLO = 0xB88; -_AD2CH15CMPLO = 0xB88; - AD2CH15CMPHI = 0xB8C; -_AD2CH15CMPHI = 0xB8C; - AD2CH15ACC = 0xB90; -_AD2CH15ACC = 0xB90; - AD2CH16CON = 0xB94; -_AD2CH16CON = 0xB94; -_AD2CH16CONbits = 0xB94; - AD2CH16DATA = 0xB98; -_AD2CH16DATA = 0xB98; - AD2CH16CNT = 0xB9C; -_AD2CH16CNT = 0xB9C; -_AD2CH16CNTbits = 0xB9C; - AD2CH16CMPLO = 0xBA0; -_AD2CH16CMPLO = 0xBA0; - AD2CH16CMPHI = 0xBA4; -_AD2CH16CMPHI = 0xBA4; - AD2CH16ACC = 0xBA8; -_AD2CH16ACC = 0xBA8; - AD2CH17CON = 0xBAC; -_AD2CH17CON = 0xBAC; -_AD2CH17CONbits = 0xBAC; - AD2CH17DATA = 0xBB0; -_AD2CH17DATA = 0xBB0; - AD2CH17CNT = 0xBB4; -_AD2CH17CNT = 0xBB4; -_AD2CH17CNTbits = 0xBB4; - AD2CH17CMPLO = 0xBB8; -_AD2CH17CMPLO = 0xBB8; - AD2CH17CMPHI = 0xBBC; -_AD2CH17CMPHI = 0xBBC; - AD2CH17ACC = 0xBC0; -_AD2CH17ACC = 0xBC0; - AD2CH18CON = 0xBC4; -_AD2CH18CON = 0xBC4; -_AD2CH18CONbits = 0xBC4; - AD2CH18DATA = 0xBC8; -_AD2CH18DATA = 0xBC8; - AD2CH18CNT = 0xBCC; -_AD2CH18CNT = 0xBCC; -_AD2CH18CNTbits = 0xBCC; - AD2CH18CMPLO = 0xBD0; -_AD2CH18CMPLO = 0xBD0; - AD2CH18CMPHI = 0xBD4; -_AD2CH18CMPHI = 0xBD4; - AD2CH18ACC = 0xBD8; -_AD2CH18ACC = 0xBD8; - AD2CH19CON = 0xBDC; -_AD2CH19CON = 0xBDC; -_AD2CH19CONbits = 0xBDC; - AD2CH19DATA = 0xBE0; -_AD2CH19DATA = 0xBE0; - AD2CH19CNT = 0xBE4; -_AD2CH19CNT = 0xBE4; -_AD2CH19CNTbits = 0xBE4; - AD2CH19CMPLO = 0xBE8; -_AD2CH19CMPLO = 0xBE8; - AD2CH19CMPHI = 0xBEC; -_AD2CH19CMPHI = 0xBEC; - AD2CH19ACC = 0xBF0; -_AD2CH19ACC = 0xBF0; - PCLKCON = 0x1000; -_PCLKCON = 0x1000; -_PCLKCONbits = 0x1000; - FSCL = 0x1004; -_FSCL = 0x1004; -_FSCLbits = 0x1004; - FSMINPER = 0x1008; -_FSMINPER = 0x1008; -_FSMINPERbits = 0x1008; - MPHASE = 0x100C; -_MPHASE = 0x100C; -_MPHASEbits = 0x100C; - MDC = 0x1010; -_MDC = 0x1010; -_MDCbits = 0x1010; - MPER = 0x1014; -_MPER = 0x1014; -_MPERbits = 0x1014; - LFSR = 0x1018; -_LFSR = 0x1018; -_LFSRbits = 0x1018; - CMBTRIG = 0x101C; -_CMBTRIG = 0x101C; -_CMBTRIGbits = 0x101C; - LOGCONA = 0x1020; -_LOGCONA = 0x1020; -_LOGCONAbits = 0x1020; - LOGCONB = 0x1024; -_LOGCONB = 0x1024; -_LOGCONBbits = 0x1024; - LOGCONC = 0x1028; -_LOGCONC = 0x1028; -_LOGCONCbits = 0x1028; - LOGCOND = 0x102C; -_LOGCOND = 0x102C; -_LOGCONDbits = 0x102C; - LOGCONE = 0x1030; -_LOGCONE = 0x1030; -_LOGCONEbits = 0x1030; - LOGCONF = 0x1034; -_LOGCONF = 0x1034; -_LOGCONFbits = 0x1034; - PWMEVTA = 0x1038; -_PWMEVTA = 0x1038; -_PWMEVTAbits = 0x1038; - PWMEVTB = 0x103C; -_PWMEVTB = 0x103C; -_PWMEVTBbits = 0x103C; - PWMEVTC = 0x1040; -_PWMEVTC = 0x1040; -_PWMEVTCbits = 0x1040; - PWMEVTD = 0x1044; -_PWMEVTD = 0x1044; -_PWMEVTDbits = 0x1044; - PWMEVTE = 0x1048; -_PWMEVTE = 0x1048; -_PWMEVTEbits = 0x1048; - PWMEVTF = 0x104C; -_PWMEVTF = 0x104C; -_PWMEVTFbits = 0x104C; - PG1CON = 0x1050; -_PG1CON = 0x1050; -_PG1CONbits = 0x1050; - PG1STAT = 0x1054; -_PG1STAT = 0x1054; -_PG1STATbits = 0x1054; - PG1IOCON = 0x1058; -_PG1IOCON = 0x1058; -_PG1IOCONbits = 0x1058; - PG1EVT = 0x105C; -_PG1EVT = 0x105C; -_PG1EVTbits = 0x105C; - PG1FPCI = 0x1060; -_PG1FPCI = 0x1060; -_PG1FPCIbits = 0x1060; - PG1CLPCI = 0x1064; -_PG1CLPCI = 0x1064; -_PG1CLPCIbits = 0x1064; - PG1FFPCI = 0x1068; -_PG1FFPCI = 0x1068; -_PG1FFPCIbits = 0x1068; - PG1SPCI = 0x106C; -_PG1SPCI = 0x106C; -_PG1SPCIbits = 0x106C; - PG1LEB = 0x1070; -_PG1LEB = 0x1070; -_PG1LEBbits = 0x1070; - PG1PHASE = 0x1074; -_PG1PHASE = 0x1074; -_PG1PHASEbits = 0x1074; - PG1DC = 0x1078; -_PG1DC = 0x1078; -_PG1DCbits = 0x1078; - PG1DCA = 0x107C; -_PG1DCA = 0x107C; -_PG1DCAbits = 0x107C; - PG1PER = 0x1080; -_PG1PER = 0x1080; -_PG1PERbits = 0x1080; - PG1TRIGA = 0x1084; -_PG1TRIGA = 0x1084; -_PG1TRIGAbits = 0x1084; - PG1TRIGB = 0x1088; -_PG1TRIGB = 0x1088; -_PG1TRIGBbits = 0x1088; - PG1TRIGC = 0x108C; -_PG1TRIGC = 0x108C; -_PG1TRIGCbits = 0x108C; - PG1DT = 0x1090; -_PG1DT = 0x1090; -_PG1DTbits = 0x1090; - PG1CAP = 0x1094; -_PG1CAP = 0x1094; -_PG1CAPbits = 0x1094; - PG2CON = 0x1098; -_PG2CON = 0x1098; -_PG2CONbits = 0x1098; - PG2STAT = 0x109C; -_PG2STAT = 0x109C; -_PG2STATbits = 0x109C; - PG2IOCON = 0x10A0; -_PG2IOCON = 0x10A0; -_PG2IOCONbits = 0x10A0; - PG2EVT = 0x10A4; -_PG2EVT = 0x10A4; -_PG2EVTbits = 0x10A4; - PG2FPCI = 0x10A8; -_PG2FPCI = 0x10A8; -_PG2FPCIbits = 0x10A8; - PG2CLPCI = 0x10AC; -_PG2CLPCI = 0x10AC; -_PG2CLPCIbits = 0x10AC; - PG2FFPCI = 0x10B0; -_PG2FFPCI = 0x10B0; -_PG2FFPCIbits = 0x10B0; - PG2SPCI = 0x10B4; -_PG2SPCI = 0x10B4; -_PG2SPCIbits = 0x10B4; - PG2LEB = 0x10B8; -_PG2LEB = 0x10B8; -_PG2LEBbits = 0x10B8; - PG2PHASE = 0x10BC; -_PG2PHASE = 0x10BC; -_PG2PHASEbits = 0x10BC; - PG2DC = 0x10C0; -_PG2DC = 0x10C0; -_PG2DCbits = 0x10C0; - PG2DCA = 0x10C4; -_PG2DCA = 0x10C4; -_PG2DCAbits = 0x10C4; - PG2PER = 0x10C8; -_PG2PER = 0x10C8; -_PG2PERbits = 0x10C8; - PG2TRIGA = 0x10CC; -_PG2TRIGA = 0x10CC; -_PG2TRIGAbits = 0x10CC; - PG2TRIGB = 0x10D0; -_PG2TRIGB = 0x10D0; -_PG2TRIGBbits = 0x10D0; - PG2TRIGC = 0x10D4; -_PG2TRIGC = 0x10D4; -_PG2TRIGCbits = 0x10D4; - PG2DT = 0x10D8; -_PG2DT = 0x10D8; -_PG2DTbits = 0x10D8; - PG2CAP = 0x10DC; -_PG2CAP = 0x10DC; -_PG2CAPbits = 0x10DC; - PG3CON = 0x10E0; -_PG3CON = 0x10E0; -_PG3CONbits = 0x10E0; - PG3STAT = 0x10E4; -_PG3STAT = 0x10E4; -_PG3STATbits = 0x10E4; - PG3IOCON = 0x10E8; -_PG3IOCON = 0x10E8; -_PG3IOCONbits = 0x10E8; - PG3EVT = 0x10EC; -_PG3EVT = 0x10EC; -_PG3EVTbits = 0x10EC; - PG3FPCI = 0x10F0; -_PG3FPCI = 0x10F0; -_PG3FPCIbits = 0x10F0; - PG3CLPCI = 0x10F4; -_PG3CLPCI = 0x10F4; -_PG3CLPCIbits = 0x10F4; - PG3FFPCI = 0x10F8; -_PG3FFPCI = 0x10F8; -_PG3FFPCIbits = 0x10F8; - PG3SPCI = 0x10FC; -_PG3SPCI = 0x10FC; -_PG3SPCIbits = 0x10FC; - PG3LEB = 0x1100; -_PG3LEB = 0x1100; -_PG3LEBbits = 0x1100; - PG3PHASE = 0x1104; -_PG3PHASE = 0x1104; -_PG3PHASEbits = 0x1104; - PG3DC = 0x1108; -_PG3DC = 0x1108; -_PG3DCbits = 0x1108; - PG3DCA = 0x110C; -_PG3DCA = 0x110C; -_PG3DCAbits = 0x110C; - PG3PER = 0x1110; -_PG3PER = 0x1110; -_PG3PERbits = 0x1110; - PG3TRIGA = 0x1114; -_PG3TRIGA = 0x1114; -_PG3TRIGAbits = 0x1114; - PG3TRIGB = 0x1118; -_PG3TRIGB = 0x1118; -_PG3TRIGBbits = 0x1118; - PG3TRIGC = 0x111C; -_PG3TRIGC = 0x111C; -_PG3TRIGCbits = 0x111C; - PG3DT = 0x1120; -_PG3DT = 0x1120; -_PG3DTbits = 0x1120; - PG3CAP = 0x1124; -_PG3CAP = 0x1124; -_PG3CAPbits = 0x1124; - PG4CON = 0x1128; -_PG4CON = 0x1128; -_PG4CONbits = 0x1128; - PG4STAT = 0x112C; -_PG4STAT = 0x112C; -_PG4STATbits = 0x112C; - PG4IOCON = 0x1130; -_PG4IOCON = 0x1130; -_PG4IOCONbits = 0x1130; - PG4EVT = 0x1134; -_PG4EVT = 0x1134; -_PG4EVTbits = 0x1134; - PG4FPCI = 0x1138; -_PG4FPCI = 0x1138; -_PG4FPCIbits = 0x1138; - PG4CLPCI = 0x113C; -_PG4CLPCI = 0x113C; -_PG4CLPCIbits = 0x113C; - PG4FFPCI = 0x1140; -_PG4FFPCI = 0x1140; -_PG4FFPCIbits = 0x1140; - PG4SPCI = 0x1144; -_PG4SPCI = 0x1144; -_PG4SPCIbits = 0x1144; - PG4LEB = 0x1148; -_PG4LEB = 0x1148; -_PG4LEBbits = 0x1148; - PG4PHASE = 0x114C; -_PG4PHASE = 0x114C; -_PG4PHASEbits = 0x114C; - PG4DC = 0x1150; -_PG4DC = 0x1150; -_PG4DCbits = 0x1150; - PG4DCA = 0x1154; -_PG4DCA = 0x1154; -_PG4DCAbits = 0x1154; - PG4PER = 0x1158; -_PG4PER = 0x1158; -_PG4PERbits = 0x1158; - PG4TRIGA = 0x115C; -_PG4TRIGA = 0x115C; -_PG4TRIGAbits = 0x115C; - PG4TRIGB = 0x1160; -_PG4TRIGB = 0x1160; -_PG4TRIGBbits = 0x1160; - PG4TRIGC = 0x1164; -_PG4TRIGC = 0x1164; -_PG4TRIGCbits = 0x1164; - PG4DT = 0x1168; -_PG4DT = 0x1168; -_PG4DTbits = 0x1168; - PG4CAP = 0x116C; -_PG4CAP = 0x116C; -_PG4CAPbits = 0x116C; - U1CON = 0x1700; -_U1CON = 0x1700; -_U1CONbits = 0x1700; - U1STAT = 0x1704; -_U1STAT = 0x1704; -_U1STATbits = 0x1704; - U1BRG = 0x1708; -_U1BRG = 0x1708; -_U1BRGbits = 0x1708; - U1RXB = 0x170C; -_U1RXB = 0x170C; -_U1RXBbits = 0x170C; - U1TXB = 0x1710; -_U1TXB = 0x1710; -_U1TXBbits = 0x1710; - U1PA = 0x1714; -_U1PA = 0x1714; -_U1PAbits = 0x1714; - U1PB = 0x1718; -_U1PB = 0x1718; -_U1PBbits = 0x1718; - U1CHK = 0x171C; -_U1CHK = 0x171C; -_U1CHKbits = 0x171C; - U1SCCON = 0x1720; -_U1SCCON = 0x1720; -_U1SCCONbits = 0x1720; - U1UIR = 0x1724; -_U1UIR = 0x1724; -_U1UIRbits = 0x1724; - U2CON = 0x1740; -_U2CON = 0x1740; -_U2CONbits = 0x1740; - U2STAT = 0x1744; -_U2STAT = 0x1744; -_U2STATbits = 0x1744; - U2BRG = 0x1748; -_U2BRG = 0x1748; -_U2BRGbits = 0x1748; - U2RXB = 0x174C; -_U2RXB = 0x174C; -_U2RXBbits = 0x174C; - U2TXB = 0x1750; -_U2TXB = 0x1750; -_U2TXBbits = 0x1750; - U2PA = 0x1754; -_U2PA = 0x1754; -_U2PAbits = 0x1754; - U2PB = 0x1758; -_U2PB = 0x1758; -_U2PBbits = 0x1758; - U2CHK = 0x175C; -_U2CHK = 0x175C; -_U2CHKbits = 0x175C; - U2SCCON = 0x1760; -_U2SCCON = 0x1760; -_U2SCCONbits = 0x1760; - U2UIR = 0x1764; -_U2UIR = 0x1764; -_U2UIRbits = 0x1764; - U3CON = 0x1780; -_U3CON = 0x1780; -_U3CONbits = 0x1780; - U3STAT = 0x1784; -_U3STAT = 0x1784; -_U3STATbits = 0x1784; - U3BRG = 0x1788; -_U3BRG = 0x1788; -_U3BRGbits = 0x1788; - U3RXB = 0x178C; -_U3RXB = 0x178C; -_U3RXBbits = 0x178C; - U3TXB = 0x1790; -_U3TXB = 0x1790; -_U3TXBbits = 0x1790; - U3PA = 0x1794; -_U3PA = 0x1794; -_U3PAbits = 0x1794; - U3PB = 0x1798; -_U3PB = 0x1798; -_U3PBbits = 0x1798; - U3CHK = 0x179C; -_U3CHK = 0x179C; -_U3CHKbits = 0x179C; - U3SCCON = 0x17A0; -_U3SCCON = 0x17A0; -_U3SCCONbits = 0x17A0; - U3UIR = 0x17A4; -_U3UIR = 0x17A4; -_U3UIRbits = 0x17A4; - SPI1CON1 = 0x1800; -_SPI1CON1 = 0x1800; -_SPI1CON1bits = 0x1800; - SPI1CON2 = 0x1804; -_SPI1CON2 = 0x1804; -_SPI1CON2bits = 0x1804; - SPI1STAT = 0x1808; -_SPI1STAT = 0x1808; -_SPI1STATbits = 0x1808; - SPI1BUF = 0x180C; -_SPI1BUF = 0x180C; - SPI1BRG = 0x1810; -_SPI1BRG = 0x1810; -_SPI1BRGbits = 0x1810; - SPI1IMSK = 0x1814; -_SPI1IMSK = 0x1814; -_SPI1IMSKbits = 0x1814; - SPI1URDT = 0x1818; -_SPI1URDT = 0x1818; - SPI2CON1 = 0x1820; -_SPI2CON1 = 0x1820; -_SPI2CON1bits = 0x1820; - SPI2CON2 = 0x1824; -_SPI2CON2 = 0x1824; -_SPI2CON2bits = 0x1824; - SPI2STAT = 0x1828; -_SPI2STAT = 0x1828; -_SPI2STATbits = 0x1828; - SPI2BUF = 0x182C; -_SPI2BUF = 0x182C; - SPI2BRG = 0x1830; -_SPI2BRG = 0x1830; -_SPI2BRGbits = 0x1830; - SPI2IMSK = 0x1834; -_SPI2IMSK = 0x1834; -_SPI2IMSKbits = 0x1834; - SPI2URDT = 0x1838; -_SPI2URDT = 0x1838; - SPI3CON1 = 0x1840; -_SPI3CON1 = 0x1840; -_SPI3CON1bits = 0x1840; - SPI3CON2 = 0x1844; -_SPI3CON2 = 0x1844; -_SPI3CON2bits = 0x1844; - SPI3STAT = 0x1848; -_SPI3STAT = 0x1848; -_SPI3STATbits = 0x1848; - SPI3BUF = 0x184C; -_SPI3BUF = 0x184C; - SPI3BRG = 0x1850; -_SPI3BRG = 0x1850; -_SPI3BRGbits = 0x1850; - SPI3IMSK = 0x1854; -_SPI3IMSK = 0x1854; -_SPI3IMSKbits = 0x1854; - SPI3URDT = 0x1858; -_SPI3URDT = 0x1858; - I2C1CON1 = 0x1880; -_I2C1CON1 = 0x1880; -_I2C1CON1bits = 0x1880; - I2C1STAT1 = 0x1884; -_I2C1STAT1 = 0x1884; -_I2C1STAT1bits = 0x1884; - I2C1ADD = 0x1888; -_I2C1ADD = 0x1888; -_I2C1ADDbits = 0x1888; - I2C1MSK = 0x188C; -_I2C1MSK = 0x188C; -_I2C1MSKbits = 0x188C; - I2C1HBRG = 0x1890; -_I2C1HBRG = 0x1890; -_I2C1HBRGbits = 0x1890; - I2C1TRN = 0x1894; -_I2C1TRN = 0x1894; -_I2C1TRNbits = 0x1894; - I2C1RCV = 0x1898; -_I2C1RCV = 0x1898; -_I2C1RCVbits = 0x1898; - I2C1CON2 = 0x189C; -_I2C1CON2 = 0x189C; -_I2C1CON2bits = 0x189C; - I2C1LBRG = 0x18A0; -_I2C1LBRG = 0x18A0; -_I2C1LBRGbits = 0x18A0; - I2C1INTC = 0x18A4; -_I2C1INTC = 0x18A4; -_I2C1INTCbits = 0x18A4; - I2C1STAT2 = 0x18A8; -_I2C1STAT2 = 0x18A8; -_I2C1STAT2bits = 0x18A8; - I2C1PEC = 0x18AC; -_I2C1PEC = 0x18AC; -_I2C1PECbits = 0x18AC; - I2C1BTO = 0x18B0; -_I2C1BTO = 0x18B0; -_I2C1BTObits = 0x18B0; - I2C1HBCTO = 0x18B4; -_I2C1HBCTO = 0x18B4; -_I2C1HBCTObits = 0x18B4; - I2C1CBCTO = 0x18B8; -_I2C1CBCTO = 0x18B8; -_I2C1CBCTObits = 0x18B8; - I2C1BITO = 0x18BC; -_I2C1BITO = 0x18BC; -_I2C1BITObits = 0x18BC; - I2C1SDASUT = 0x18C0; -_I2C1SDASUT = 0x18C0; -_I2C1SDASUTbits = 0x18C0; - I2C2CON1 = 0x18D0; -_I2C2CON1 = 0x18D0; -_I2C2CON1bits = 0x18D0; - I2C2STAT1 = 0x18D4; -_I2C2STAT1 = 0x18D4; -_I2C2STAT1bits = 0x18D4; - I2C2ADD = 0x18D8; -_I2C2ADD = 0x18D8; -_I2C2ADDbits = 0x18D8; - I2C2MSK = 0x18DC; -_I2C2MSK = 0x18DC; -_I2C2MSKbits = 0x18DC; - I2C2HBRG = 0x18E0; -_I2C2HBRG = 0x18E0; -_I2C2HBRGbits = 0x18E0; - I2C2TRN = 0x18E4; -_I2C2TRN = 0x18E4; -_I2C2TRNbits = 0x18E4; - I2C2RCV = 0x18E8; -_I2C2RCV = 0x18E8; -_I2C2RCVbits = 0x18E8; - I2C2CON2 = 0x18EC; -_I2C2CON2 = 0x18EC; -_I2C2CON2bits = 0x18EC; - I2C2LBRG = 0x18F0; -_I2C2LBRG = 0x18F0; -_I2C2LBRGbits = 0x18F0; - I2C2INTC = 0x18F4; -_I2C2INTC = 0x18F4; -_I2C2INTCbits = 0x18F4; - I2C2STAT2 = 0x18F8; -_I2C2STAT2 = 0x18F8; -_I2C2STAT2bits = 0x18F8; - I2C2PEC = 0x18FC; -_I2C2PEC = 0x18FC; -_I2C2PECbits = 0x18FC; - I2C2BTO = 0x1900; -_I2C2BTO = 0x1900; -_I2C2BTObits = 0x1900; - I2C2HBCTO = 0x1904; -_I2C2HBCTO = 0x1904; -_I2C2HBCTObits = 0x1904; - I2C2CBCTO = 0x1908; -_I2C2CBCTO = 0x1908; -_I2C2CBCTObits = 0x1908; - I2C2BITO = 0x190C; -_I2C2BITO = 0x190C; -_I2C2BITObits = 0x190C; - I2C2SDASUT = 0x1910; -_I2C2SDASUT = 0x1910; -_I2C2SDASUTbits = 0x1910; - SENT1CON1 = 0x19C0; -_SENT1CON1 = 0x19C0; -_SENT1CON1bits = 0x19C0; - SENT1CON2 = 0x19C4; -_SENT1CON2 = 0x19C4; -_SENT1CON2bits = 0x19C4; - SENT1CON3 = 0x19C8; -_SENT1CON3 = 0x19C8; -_SENT1CON3bits = 0x19C8; - SENT1STAT = 0x19CC; -_SENT1STAT = 0x19CC; -_SENT1STATbits = 0x19CC; - SENT1SYNC = 0x19D0; -_SENT1SYNC = 0x19D0; -_SENT1SYNCbits = 0x19D0; - SENT1DAT = 0x19D4; -_SENT1DAT = 0x19D4; -_SENT1DATbits = 0x19D4; - SENT2CON1 = 0x19E0; -_SENT2CON1 = 0x19E0; -_SENT2CON1bits = 0x19E0; - SENT2CON2 = 0x19E4; -_SENT2CON2 = 0x19E4; -_SENT2CON2bits = 0x19E4; - SENT2CON3 = 0x19E8; -_SENT2CON3 = 0x19E8; -_SENT2CON3bits = 0x19E8; - SENT2STAT = 0x19EC; -_SENT2STAT = 0x19EC; -_SENT2STATbits = 0x19EC; - SENT2SYNC = 0x19F0; -_SENT2SYNC = 0x19F0; -_SENT2SYNCbits = 0x19F0; - SENT2DAT = 0x19F4; -_SENT2DAT = 0x19F4; -_SENT2DATbits = 0x19F4; - QEI1CON = 0x1A00; -_QEI1CON = 0x1A00; -_QEI1CONbits = 0x1A00; - QEI1IOC = 0x1A04; -_QEI1IOC = 0x1A04; -_QEI1IOCbits = 0x1A04; - QEI1STAT = 0x1A08; -_QEI1STAT = 0x1A08; -_QEI1STATbits = 0x1A08; - POS1CNT = 0x1A0C; -_POS1CNT = 0x1A0C; - POS1HLD = 0x1A10; -_POS1HLD = 0x1A10; - VEL1CNT = 0x1A14; -_VEL1CNT = 0x1A14; - VEL1HLD = 0x1A18; -_VEL1HLD = 0x1A18; - INT1TMR = 0x1A1C; -_INT1TMR = 0x1A1C; - INT1HLD = 0x1A20; -_INT1HLD = 0x1A20; - INDX1CNT = 0x1A24; -_INDX1CNT = 0x1A24; - INDX1HLD = 0x1A28; -_INDX1HLD = 0x1A28; - QEI1GEC = 0x1A2C; -_QEI1GEC = 0x1A2C; - QEI1LEC = 0x1A30; -_QEI1LEC = 0x1A30; - CCP1CON1 = 0x1B00; -_CCP1CON1 = 0x1B00; -_CCP1CON1bits = 0x1B00; - CCP1CON2 = 0x1B04; -_CCP1CON2 = 0x1B04; -_CCP1CON2bits = 0x1B04; - CCP1CON3 = 0x1B08; -_CCP1CON3 = 0x1B08; -_CCP1CON3bits = 0x1B08; - CCP1STAT = 0x1B0C; -_CCP1STAT = 0x1B0C; -_CCP1STATbits = 0x1B0C; - CCP1TMR = 0x1B10; -_CCP1TMR = 0x1B10; -_CCP1TMRbits = 0x1B10; - CCP1PR = 0x1B14; -_CCP1PR = 0x1B14; -_CCP1PRbits = 0x1B14; - CCP1RA = 0x1B18; -_CCP1RA = 0x1B18; -_CCP1RAbits = 0x1B18; - CCP1RB = 0x1B1C; -_CCP1RB = 0x1B1C; -_CCP1RBbits = 0x1B1C; - CCP1BUF = 0x1B20; -_CCP1BUF = 0x1B20; -_CCP1BUFbits = 0x1B20; - CCP2CON1 = 0x1B30; -_CCP2CON1 = 0x1B30; -_CCP2CON1bits = 0x1B30; - CCP2CON2 = 0x1B34; -_CCP2CON2 = 0x1B34; -_CCP2CON2bits = 0x1B34; - CCP2CON3 = 0x1B38; -_CCP2CON3 = 0x1B38; -_CCP2CON3bits = 0x1B38; - CCP2STAT = 0x1B3C; -_CCP2STAT = 0x1B3C; -_CCP2STATbits = 0x1B3C; - CCP2TMR = 0x1B40; -_CCP2TMR = 0x1B40; -_CCP2TMRbits = 0x1B40; - CCP2PR = 0x1B44; -_CCP2PR = 0x1B44; -_CCP2PRbits = 0x1B44; - CCP2RA = 0x1B48; -_CCP2RA = 0x1B48; -_CCP2RAbits = 0x1B48; - CCP2RB = 0x1B4C; -_CCP2RB = 0x1B4C; -_CCP2RBbits = 0x1B4C; - CCP2BUF = 0x1B50; -_CCP2BUF = 0x1B50; -_CCP2BUFbits = 0x1B50; - CCP3CON1 = 0x1B60; -_CCP3CON1 = 0x1B60; -_CCP3CON1bits = 0x1B60; - CCP3CON2 = 0x1B64; -_CCP3CON2 = 0x1B64; -_CCP3CON2bits = 0x1B64; - CCP3CON3 = 0x1B68; -_CCP3CON3 = 0x1B68; -_CCP3CON3bits = 0x1B68; - CCP3STAT = 0x1B6C; -_CCP3STAT = 0x1B6C; -_CCP3STATbits = 0x1B6C; - CCP3TMR = 0x1B70; -_CCP3TMR = 0x1B70; -_CCP3TMRbits = 0x1B70; - CCP3PR = 0x1B74; -_CCP3PR = 0x1B74; -_CCP3PRbits = 0x1B74; - CCP3RA = 0x1B78; -_CCP3RA = 0x1B78; -_CCP3RAbits = 0x1B78; - CCP3RB = 0x1B7C; -_CCP3RB = 0x1B7C; -_CCP3RBbits = 0x1B7C; - CCP3BUF = 0x1B80; -_CCP3BUF = 0x1B80; -_CCP3BUFbits = 0x1B80; - CCP4CON1 = 0x1B90; -_CCP4CON1 = 0x1B90; -_CCP4CON1bits = 0x1B90; - CCP4CON2 = 0x1B94; -_CCP4CON2 = 0x1B94; -_CCP4CON2bits = 0x1B94; - CCP4CON3 = 0x1B98; -_CCP4CON3 = 0x1B98; -_CCP4CON3bits = 0x1B98; - CCP4STAT = 0x1B9C; -_CCP4STAT = 0x1B9C; -_CCP4STATbits = 0x1B9C; - CCP4TMR = 0x1BA0; -_CCP4TMR = 0x1BA0; -_CCP4TMRbits = 0x1BA0; - CCP4PR = 0x1BA4; -_CCP4PR = 0x1BA4; -_CCP4PRbits = 0x1BA4; - CCP4RA = 0x1BA8; -_CCP4RA = 0x1BA8; -_CCP4RAbits = 0x1BA8; - CCP4RB = 0x1BAC; -_CCP4RB = 0x1BAC; -_CCP4RBbits = 0x1BAC; - CCP4BUF = 0x1BB0; -_CCP4BUF = 0x1BB0; -_CCP4BUFbits = 0x1BB0; - DACCTRL1 = 0x1D40; -_DACCTRL1 = 0x1D40; -_DACCTRL1bits = 0x1D40; - DACCTRL2 = 0x1D44; -_DACCTRL2 = 0x1D44; -_DACCTRL2bits = 0x1D44; - DAC1CON = 0x1D48; -_DAC1CON = 0x1D48; -_DAC1CONbits = 0x1D48; - DAC1DAT = 0x1D4C; -_DAC1DAT = 0x1D4C; -_DAC1DATbits = 0x1D4C; - DAC1SLPCON = 0x1D50; -_DAC1SLPCON = 0x1D50; -_DAC1SLPCONbits = 0x1D50; - DAC1SLPDAT = 0x1D54; -_DAC1SLPDAT = 0x1D54; -_DAC1SLPDATbits = 0x1D54; - DAC2CON = 0x1D58; -_DAC2CON = 0x1D58; -_DAC2CONbits = 0x1D58; - DAC2DAT = 0x1D5C; -_DAC2DAT = 0x1D5C; -_DAC2DATbits = 0x1D5C; - DAC2SLPCON = 0x1D60; -_DAC2SLPCON = 0x1D60; -_DAC2SLPCONbits = 0x1D60; - DAC2SLPDAT = 0x1D64; -_DAC2SLPDAT = 0x1D64; -_DAC2SLPDATbits = 0x1D64; - DAC3CON = 0x1D68; -_DAC3CON = 0x1D68; -_DAC3CONbits = 0x1D68; - DAC3DAT = 0x1D6C; -_DAC3DAT = 0x1D6C; -_DAC3DATbits = 0x1D6C; - DAC3SLPCON = 0x1D70; -_DAC3SLPCON = 0x1D70; -_DAC3SLPCONbits = 0x1D70; - DAC3SLPDAT = 0x1D74; -_DAC3SLPDAT = 0x1D74; -_DAC3SLPDATbits = 0x1D74; - T1CON = 0x1E00; -_T1CON = 0x1E00; -_T1CONbits = 0x1E00; - TMR1 = 0x1E04; -_TMR1 = 0x1E04; - PR1 = 0x1E08; -_PR1 = 0x1E08; - HPCCON = 0x1E10; -_HPCCON = 0x1E10; -_HPCCONbits = 0x1E10; - HPSEL0 = 0x1E14; -_HPSEL0 = 0x1E14; -_HPSEL0bits = 0x1E14; - HPSEL1 = 0x1E18; -_HPSEL1 = 0x1E18; -_HPSEL1bits = 0x1E18; - HPCCNTL0 = 0x1E20; -_HPCCNTL0 = 0x1E20; - HPCCNTH0 = 0x1E24; -_HPCCNTH0 = 0x1E24; - HPCCNTL1 = 0x1E28; -_HPCCNTL1 = 0x1E28; - HPCCNTH1 = 0x1E2C; -_HPCCNTH1 = 0x1E2C; - HPCCNTL2 = 0x1E30; -_HPCCNTL2 = 0x1E30; - HPCCNTH2 = 0x1E34; -_HPCCNTH2 = 0x1E34; - HPCCNTL3 = 0x1E38; -_HPCCNTL3 = 0x1E38; - HPCCNTH3 = 0x1E3C; -_HPCCNTH3 = 0x1E3C; - HPCCNTL4 = 0x1E40; -_HPCCNTL4 = 0x1E40; - HPCCNTH4 = 0x1E44; -_HPCCNTH4 = 0x1E44; - HPCCNTL5 = 0x1E48; -_HPCCNTL5 = 0x1E48; - HPCCNTH5 = 0x1E4C; -_HPCCNTH5 = 0x1E4C; - HPCCNTL6 = 0x1E50; -_HPCCNTL6 = 0x1E50; - HPCCNTH6 = 0x1E54; -_HPCCNTH6 = 0x1E54; - HPCCNTL7 = 0x1E58; -_HPCCNTL7 = 0x1E58; - HPCCNTH7 = 0x1E5C; -_HPCCNTH7 = 0x1E5C; - CHECON = 0x1E60; -_CHECON = 0x1E60; -_CHECONbits = 0x1E60; - CHESTAT = 0x1E64; -_CHESTAT = 0x1E64; -_CHESTATbits = 0x1E64; - CHEFLTINJ = 0x1E68; -_CHEFLTINJ = 0x1E68; -_CHEFLTINJbits = 0x1E68; - PACCON1 = 0x1E80; -_PACCON1 = 0x1E80; -_PACCON1bits = 0x1E80; - PACCON2 = 0x1E84; -_PACCON2 = 0x1E84; -_PACCON2bits = 0x1E84; - IOIM1CON = 0x1E90; -_IOIM1CON = 0x1E90; -_IOIM1CONbits = 0x1E90; - IOIM1BCON = 0x1E94; -_IOIM1BCON = 0x1E94; -_IOIM1BCONbits = 0x1E94; - IOIM1STAT = 0x1E98; -_IOIM1STAT = 0x1E98; -_IOIM1STATbits = 0x1E98; - IOIM2CON = 0x1E9C; -_IOIM2CON = 0x1E9C; -_IOIM2CONbits = 0x1E9C; - IOIM2BCON = 0x1EA0; -_IOIM2BCON = 0x1EA0; -_IOIM2BCONbits = 0x1EA0; - IOIM2STAT = 0x1EA4; -_IOIM2STAT = 0x1EA4; -_IOIM2STATbits = 0x1EA4; - IOIM3CON = 0x1EA8; -_IOIM3CON = 0x1EA8; -_IOIM3CONbits = 0x1EA8; - IOIM3BCON = 0x1EAC; -_IOIM3BCON = 0x1EAC; -_IOIM3BCONbits = 0x1EAC; - IOIM3STAT = 0x1EB0; -_IOIM3STAT = 0x1EB0; -_IOIM3STATbits = 0x1EB0; - IOIM4CON = 0x1EB4; -_IOIM4CON = 0x1EB4; -_IOIM4CONbits = 0x1EB4; - IOIM4BCON = 0x1EB8; -_IOIM4BCON = 0x1EB8; -_IOIM4BCONbits = 0x1EB8; - IOIM4STAT = 0x1EBC; -_IOIM4STAT = 0x1EBC; -_IOIM4STATbits = 0x1EBC; - B1SCDATA0L = 0x1F00; -_B1SCDATA0L = 0x1F00; - B1SCDATA0H = 0x1F04; -_B1SCDATA0H = 0x1F04; - B1SCDATA1L = 0x1F08; -_B1SCDATA1L = 0x1F08; - B1SCDATA1H = 0x1F0C; -_B1SCDATA1H = 0x1F0C; - B1SCDATA2L = 0x1F10; -_B1SCDATA2L = 0x1F10; - B1SCDATA2H = 0x1F14; -_B1SCDATA2H = 0x1F14; - B1SCDATA3L = 0x1F18; -_B1SCDATA3L = 0x1F18; - B1SCDATA3H = 0x1F1C; -_B1SCDATA3H = 0x1F1C; - B1IDS0 = 0x1F80; -_B1IDS0 = 0x1F80; -_B1IDS0bits = 0x1F80; - B1RDATA0 = 0x1F80; -_B1RDATA0 = 0x1F80; -_B1RDATA0bits = 0x1F80; - B1IDS1 = 0x1F84; -_B1IDS1 = 0x1F84; -_B1IDS1bits = 0x1F84; - B1RDATA1 = 0x1F84; -_B1RDATA1 = 0x1F84; -_B1RDATA1bits = 0x1F84; - B1IDS2 = 0x1F88; -_B1IDS2 = 0x1F88; -_B1IDS2bits = 0x1F88; - B1RDATA2 = 0x1F88; -_B1RDATA2 = 0x1F88; -_B1RDATA2bits = 0x1F88; - B1IDS3 = 0x1F8C; -_B1IDS3 = 0x1F8C; -_B1IDS3bits = 0x1F8C; - B1RDATA3 = 0x1F8C; -_B1RDATA3 = 0x1F8C; -_B1RDATA3bits = 0x1F8C; - B1IDS4 = 0x1F90; -_B1IDS4 = 0x1F90; -_B1IDS4bits = 0x1F90; - B1RDATA4 = 0x1F90; -_B1RDATA4 = 0x1F90; -_B1RDATA4bits = 0x1F90; - B1IDS5 = 0x1F94; -_B1IDS5 = 0x1F94; -_B1IDS5bits = 0x1F94; - B1RDATA5 = 0x1F94; -_B1RDATA5 = 0x1F94; -_B1RDATA5bits = 0x1F94; - B1IDS6 = 0x1F98; -_B1IDS6 = 0x1F98; -_B1IDS6bits = 0x1F98; - B1RDATA6 = 0x1F98; -_B1RDATA6 = 0x1F98; -_B1RDATA6bits = 0x1F98; - B1IDS7 = 0x1F9C; -_B1IDS7 = 0x1F9C; -_B1IDS7bits = 0x1F9C; - B1RDATA7 = 0x1F9C; -_B1RDATA7 = 0x1F9C; -_B1RDATA7bits = 0x1F9C; - B1CLTCON0 = 0x1FC0; -_B1CLTCON0 = 0x1FC0; -_B1CLTCON0bits = 0x1FC0; - B1CLTCON1 = 0x1FC4; -_B1CLTCON1 = 0x1FC4; -_B1CLTCON1bits = 0x1FC4; - B1CLTCON2 = 0x1FC8; -_B1CLTCON2 = 0x1FC8; -_B1CLTCON2bits = 0x1FC8; - B1CLTCON3 = 0x1FCC; -_B1CLTCON3 = 0x1FCC; -_B1CLTCON3bits = 0x1FCC; - B1RCCON = 0x1FE0; -_B1RCCON = 0x1FE0; -_B1RCCONbits = 0x1FE0; - B1CTRLCON = 0x1FE4; -_B1CTRLCON = 0x1FE4; -_B1CTRLCONbits = 0x1FE4; - B1CCON = 0x1FE8; -_B1CCON = 0x1FE8; -_B1CCONbits = 0x1FE8; - B1CHCON = 0x1FEC; -_B1CHCON = 0x1FEC; -_B1CHCONbits = 0x1FEC; - B1STAT = 0x1FF0; -_B1STAT = 0x1FF0; -_B1STATbits = 0x1FF0; - B1INSTR = 0x1FF4; -_B1INSTR = 0x1FF4; -_B1INSTRbits = 0x1FF4; - B1CHSTAT = 0x1FF8; -_B1CHSTAT = 0x1FF8; -_B1CHSTATbits = 0x1FF8; - B1CON = 0x1FFC; -_B1CON = 0x1FFC; -_B1CONbits = 0x1FFC; - DMACON = 0x2300; -_DMACON = 0x2300; -_DMACONbits = 0x2300; - DMABUF = 0x2304; -_DMABUF = 0x2304; - DMALOW = 0x2308; -_DMALOW = 0x2308; -_DMALOWbits = 0x2308; - DMAHIGH = 0x230C; -_DMAHIGH = 0x230C; -_DMAHIGHbits = 0x230C; - DMA0CH = 0x2310; -_DMA0CH = 0x2310; -_DMA0CHbits = 0x2310; - DMA0SEL = 0x2314; -_DMA0SEL = 0x2314; -_DMA0SELbits = 0x2314; - DMA0STAT = 0x2318; -_DMA0STAT = 0x2318; -_DMA0STATbits = 0x2318; - DMA0SRC = 0x231C; -_DMA0SRC = 0x231C; -_DMA0SRCbits = 0x231C; - DMA0DST = 0x2320; -_DMA0DST = 0x2320; -_DMA0DSTbits = 0x2320; - DMA0CNT = 0x2324; -_DMA0CNT = 0x2324; -_DMA0CNTbits = 0x2324; - DMA0CLR = 0x2328; -_DMA0CLR = 0x2328; - DMA0SET = 0x232C; -_DMA0SET = 0x232C; - DMA0INV = 0x2330; -_DMA0INV = 0x2330; - DMA0MSK = 0x2334; -_DMA0MSK = 0x2334; - DMA0PAT = 0x2338; -_DMA0PAT = 0x2338; - DMA1CH = 0x233C; -_DMA1CH = 0x233C; -_DMA1CHbits = 0x233C; - DMA1SEL = 0x2340; -_DMA1SEL = 0x2340; -_DMA1SELbits = 0x2340; - DMA1STAT = 0x2344; -_DMA1STAT = 0x2344; -_DMA1STATbits = 0x2344; - DMA1SRC = 0x2348; -_DMA1SRC = 0x2348; -_DMA1SRCbits = 0x2348; - DMA1DST = 0x234C; -_DMA1DST = 0x234C; -_DMA1DSTbits = 0x234C; - DMA1CNT = 0x2350; -_DMA1CNT = 0x2350; -_DMA1CNTbits = 0x2350; - DMA1CLR = 0x2354; -_DMA1CLR = 0x2354; - DMA1SET = 0x2358; -_DMA1SET = 0x2358; - DMA1INV = 0x235C; -_DMA1INV = 0x235C; - DMA1MSK = 0x2360; -_DMA1MSK = 0x2360; - DMA1PAT = 0x2364; -_DMA1PAT = 0x2364; - DMA2CH = 0x2368; -_DMA2CH = 0x2368; -_DMA2CHbits = 0x2368; - DMA2SEL = 0x236C; -_DMA2SEL = 0x236C; -_DMA2SELbits = 0x236C; - DMA2STAT = 0x2370; -_DMA2STAT = 0x2370; -_DMA2STATbits = 0x2370; - DMA2SRC = 0x2374; -_DMA2SRC = 0x2374; -_DMA2SRCbits = 0x2374; - DMA2DST = 0x2378; -_DMA2DST = 0x2378; -_DMA2DSTbits = 0x2378; - DMA2CNT = 0x237C; -_DMA2CNT = 0x237C; -_DMA2CNTbits = 0x237C; - DMA2CLR = 0x2380; -_DMA2CLR = 0x2380; - DMA2SET = 0x2384; -_DMA2SET = 0x2384; - DMA2INV = 0x2388; -_DMA2INV = 0x2388; - DMA2MSK = 0x238C; -_DMA2MSK = 0x238C; - DMA2PAT = 0x2390; -_DMA2PAT = 0x2390; - DMA3CH = 0x2394; -_DMA3CH = 0x2394; -_DMA3CHbits = 0x2394; - DMA3SEL = 0x2398; -_DMA3SEL = 0x2398; -_DMA3SELbits = 0x2398; - DMA3STAT = 0x239C; -_DMA3STAT = 0x239C; -_DMA3STATbits = 0x239C; - DMA3SRC = 0x23A0; -_DMA3SRC = 0x23A0; -_DMA3SRCbits = 0x23A0; - DMA3DST = 0x23A4; -_DMA3DST = 0x23A4; -_DMA3DSTbits = 0x23A4; - DMA3CNT = 0x23A8; -_DMA3CNT = 0x23A8; -_DMA3CNTbits = 0x23A8; - DMA3CLR = 0x23AC; -_DMA3CLR = 0x23AC; - DMA3SET = 0x23B0; -_DMA3SET = 0x23B0; - DMA3INV = 0x23B4; -_DMA3INV = 0x23B4; - DMA3MSK = 0x23B8; -_DMA3MSK = 0x23B8; - DMA3PAT = 0x23BC; -_DMA3PAT = 0x23BC; - DMA4CH = 0x23C0; -_DMA4CH = 0x23C0; -_DMA4CHbits = 0x23C0; - DMA4SEL = 0x23C4; -_DMA4SEL = 0x23C4; -_DMA4SELbits = 0x23C4; - DMA4STAT = 0x23C8; -_DMA4STAT = 0x23C8; -_DMA4STATbits = 0x23C8; - DMA4SRC = 0x23CC; -_DMA4SRC = 0x23CC; -_DMA4SRCbits = 0x23CC; - DMA4DST = 0x23D0; -_DMA4DST = 0x23D0; -_DMA4DSTbits = 0x23D0; - DMA4CNT = 0x23D4; -_DMA4CNT = 0x23D4; -_DMA4CNTbits = 0x23D4; - DMA4CLR = 0x23D8; -_DMA4CLR = 0x23D8; - DMA4SET = 0x23DC; -_DMA4SET = 0x23DC; - DMA4INV = 0x23E0; -_DMA4INV = 0x23E0; - DMA4MSK = 0x23E4; -_DMA4MSK = 0x23E4; - DMA4PAT = 0x23E8; -_DMA4PAT = 0x23E8; - DMA5CH = 0x23EC; -_DMA5CH = 0x23EC; -_DMA5CHbits = 0x23EC; - DMA5SEL = 0x23F0; -_DMA5SEL = 0x23F0; -_DMA5SELbits = 0x23F0; - DMA5STAT = 0x23F4; -_DMA5STAT = 0x23F4; -_DMA5STATbits = 0x23F4; - DMA5SRC = 0x23F8; -_DMA5SRC = 0x23F8; -_DMA5SRCbits = 0x23F8; - DMA5DST = 0x23FC; -_DMA5DST = 0x23FC; -_DMA5DSTbits = 0x23FC; - DMA5CNT = 0x2400; -_DMA5CNT = 0x2400; -_DMA5CNTbits = 0x2400; - DMA5CLR = 0x2404; -_DMA5CLR = 0x2404; - DMA5SET = 0x2408; -_DMA5SET = 0x2408; - DMA5INV = 0x240C; -_DMA5INV = 0x240C; - DMA5MSK = 0x2410; -_DMA5MSK = 0x2410; - DMA5PAT = 0x2414; -_DMA5PAT = 0x2414; - NVMCON = 0x3000; -_NVMCON = 0x3000; -_NVMCONbits = 0x3000; - NVMADR = 0x3004; -_NVMADR = 0x3004; -_NVMADRbits = 0x3004; - NVMDATA0 = 0x3008; -_NVMDATA0 = 0x3008; - NVMDATA1 = 0x300C; -_NVMDATA1 = 0x300C; - NVMDATA2 = 0x3010; -_NVMDATA2 = 0x3010; - NVMDATA3 = 0x3014; -_NVMDATA3 = 0x3014; - NVMSRCADR = 0x3018; -_NVMSRCADR = 0x3018; -_NVMSRCADRbits = 0x3018; - NVMECCCON = 0x301C; -_NVMECCCON = 0x301C; -_NVMECCCONbits = 0x301C; - NVMECCSTAT = 0x3020; -_NVMECCSTAT = 0x3020; -_NVMECCSTATbits = 0x3020; - NVMECCFPTR = 0x3024; -_NVMECCFPTR = 0x3024; -_NVMECCFPTRbits = 0x3024; - NVMECCFADDR = 0x3028; -_NVMECCFADDR = 0x3028; -_NVMECCFADDRbits = 0x3028; - NVMECCEADDR = 0x302C; -_NVMECCEADDR = 0x302C; -_NVMECCEADDRbits = 0x302C; - NVMECCEDATA0 = 0x3030; -_NVMECCEDATA0 = 0x3030; - NVMECCEDATA1 = 0x3034; -_NVMECCEDATA1 = 0x3034; - NVMECCEDATA2 = 0x3038; -_NVMECCEDATA2 = 0x3038; - NVMECCEDATA3 = 0x303C; -_NVMECCEDATA3 = 0x303C; - NVMECCVAL = 0x3040; -_NVMECCVAL = 0x3040; -_NVMECCVALbits = 0x3040; - NVMECCSYND = 0x3044; -_NVMECCSYND = 0x3044; -_NVMECCSYNDbits = 0x3044; - NVMCRCCON = 0x3048; -_NVMCRCCON = 0x3048; -_NVMCRCCONbits = 0x3048; - NVMCRCST = 0x304C; -_NVMCRCST = 0x304C; -_NVMCRCSTbits = 0x304C; - NVMCRCEND = 0x3050; -_NVMCRCEND = 0x3050; -_NVMCRCENDbits = 0x3050; - NVMCRCSEED = 0x3054; -_NVMCRCSEED = 0x3054; - NVMCRCDATA = 0x3058; -_NVMCRCDATA = 0x3058; - OSCCTRL = 0x3100; -_OSCCTRL = 0x3100; -_OSCCTRLbits = 0x3100; - OSCCFG = 0x3104; -_OSCCFG = 0x3104; -_OSCCFGbits = 0x3104; - CLKFAIL = 0x3108; -_CLKFAIL = 0x3108; -_CLKFAILbits = 0x3108; - SCSFAIL = 0x310C; -_SCSFAIL = 0x310C; -_SCSFAILbits = 0x310C; - CLK1CON = 0x3118; -_CLK1CON = 0x3118; -_CLK1CONbits = 0x3118; - CLK1DIV = 0x311C; -_CLK1DIV = 0x311C; -_CLK1DIVbits = 0x311C; - CLK2CON = 0x3120; -_CLK2CON = 0x3120; -_CLK2CONbits = 0x3120; - CLK2DIV = 0x3124; -_CLK2DIV = 0x3124; -_CLK2DIVbits = 0x3124; - CLK3CON = 0x3128; -_CLK3CON = 0x3128; -_CLK3CONbits = 0x3128; - CLK3DIV = 0x312C; -_CLK3DIV = 0x312C; -_CLK3DIVbits = 0x312C; - CLK4CON = 0x3130; -_CLK4CON = 0x3130; -_CLK4CONbits = 0x3130; - CLK4DIV = 0x3134; -_CLK4DIV = 0x3134; -_CLK4DIVbits = 0x3134; - CLK5CON = 0x3138; -_CLK5CON = 0x3138; -_CLK5CONbits = 0x3138; - CLK5DIV = 0x313C; -_CLK5DIV = 0x313C; -_CLK5DIVbits = 0x313C; - CLK6CON = 0x3140; -_CLK6CON = 0x3140; -_CLK6CONbits = 0x3140; - CLK6DIV = 0x3144; -_CLK6DIV = 0x3144; -_CLK6DIVbits = 0x3144; - CLK7CON = 0x3148; -_CLK7CON = 0x3148; -_CLK7CONbits = 0x3148; - CLK7DIV = 0x314C; -_CLK7DIV = 0x314C; -_CLK7DIVbits = 0x314C; - CLK8CON = 0x3150; -_CLK8CON = 0x3150; -_CLK8CONbits = 0x3150; - CLK8DIV = 0x3154; -_CLK8DIV = 0x3154; -_CLK8DIVbits = 0x3154; - CLK9CON = 0x3158; -_CLK9CON = 0x3158; -_CLK9CONbits = 0x3158; - CLK9DIV = 0x315C; -_CLK9DIV = 0x315C; -_CLK9DIVbits = 0x315C; - CLK10CON = 0x3160; -_CLK10CON = 0x3160; -_CLK10CONbits = 0x3160; - CLK10DIV = 0x3164; -_CLK10DIV = 0x3164; -_CLK10DIVbits = 0x3164; - CLK11CON = 0x3168; -_CLK11CON = 0x3168; -_CLK11CONbits = 0x3168; - CLK11DIV = 0x316C; -_CLK11DIV = 0x316C; -_CLK11DIVbits = 0x316C; - CLK12CON = 0x3170; -_CLK12CON = 0x3170; -_CLK12CONbits = 0x3170; - CLK12DIV = 0x3174; -_CLK12DIV = 0x3174; -_CLK12DIVbits = 0x3174; - CLK13CON = 0x3178; -_CLK13CON = 0x3178; -_CLK13CONbits = 0x3178; - CLK13DIV = 0x317C; -_CLK13DIV = 0x317C; -_CLK13DIVbits = 0x317C; - PLL1CON = 0x3180; -_PLL1CON = 0x3180; -_PLL1CONbits = 0x3180; - PLL1DIV = 0x3184; -_PLL1DIV = 0x3184; -_PLL1DIVbits = 0x3184; - VCO1DIV = 0x3188; -_VCO1DIV = 0x3188; -_VCO1DIVbits = 0x3188; - PLL2CON = 0x318C; -_PLL2CON = 0x318C; -_PLL2CONbits = 0x318C; - PLL2DIV = 0x3190; -_PLL2DIV = 0x3190; -_PLL2DIVbits = 0x3190; - VCO2DIV = 0x3194; -_VCO2DIV = 0x3194; -_VCO2DIVbits = 0x3194; - RCON = 0x3198; -_RCON = 0x3198; -_RCONbits = 0x3198; - CLKDIAG = 0x319C; -_CLKDIAG = 0x319C; -_CLKDIAGbits = 0x319C; - CM1CON = 0x3200; -_CM1CON = 0x3200; -_CM1CONbits = 0x3200; - CM1STAT = 0x3204; -_CM1STAT = 0x3204; -_CM1STATbits = 0x3204; - CM1WINPR = 0x3208; -_CM1WINPR = 0x3208; - CM1SEL = 0x320C; -_CM1SEL = 0x320C; -_CM1SELbits = 0x320C; - CM1BUF = 0x3210; -_CM1BUF = 0x3210; - CM1SAT = 0x3214; -_CM1SAT = 0x3214; - CM1HFAIL = 0x3218; -_CM1HFAIL = 0x3218; - CM1LFAIL = 0x321C; -_CM1LFAIL = 0x321C; - CM1HWARN = 0x3220; -_CM1HWARN = 0x3220; - CM1LWARN = 0x3224; -_CM1LWARN = 0x3224; - CM2CON = 0x3230; -_CM2CON = 0x3230; -_CM2CONbits = 0x3230; - CM2STAT = 0x3234; -_CM2STAT = 0x3234; -_CM2STATbits = 0x3234; - CM2WINPR = 0x3238; -_CM2WINPR = 0x3238; - CM2SEL = 0x323C; -_CM2SEL = 0x323C; -_CM2SELbits = 0x323C; - CM2BUF = 0x3240; -_CM2BUF = 0x3240; - CM2SAT = 0x3244; -_CM2SAT = 0x3244; - CM2HFAIL = 0x3248; -_CM2HFAIL = 0x3248; - CM2LFAIL = 0x324C; -_CM2LFAIL = 0x324C; - CM2HWARN = 0x3250; -_CM2HWARN = 0x3250; - CM2LWARN = 0x3254; -_CM2LWARN = 0x3254; - CM3CON = 0x3260; -_CM3CON = 0x3260; -_CM3CONbits = 0x3260; - CM3STAT = 0x3264; -_CM3STAT = 0x3264; -_CM3STATbits = 0x3264; - CM3WINPR = 0x3268; -_CM3WINPR = 0x3268; - CM3SEL = 0x326C; -_CM3SEL = 0x326C; -_CM3SELbits = 0x326C; - CM3BUF = 0x3270; -_CM3BUF = 0x3270; - CM3SAT = 0x3274; -_CM3SAT = 0x3274; - CM3HFAIL = 0x3278; -_CM3HFAIL = 0x3278; - CM3LFAIL = 0x327C; -_CM3LFAIL = 0x327C; - CM3HWARN = 0x3280; -_CM3HWARN = 0x3280; - CM3LWARN = 0x3284; -_CM3LWARN = 0x3284; - CM4CON = 0x3290; -_CM4CON = 0x3290; -_CM4CONbits = 0x3290; - CM4STAT = 0x3294; -_CM4STAT = 0x3294; -_CM4STATbits = 0x3294; - CM4WINPR = 0x3298; -_CM4WINPR = 0x3298; - CM4SEL = 0x329C; -_CM4SEL = 0x329C; -_CM4SELbits = 0x329C; - CM4BUF = 0x32A0; -_CM4BUF = 0x32A0; - CM4SAT = 0x32A4; -_CM4SAT = 0x32A4; - CM4HFAIL = 0x32A8; -_CM4HFAIL = 0x32A8; - CM4LFAIL = 0x32AC; -_CM4LFAIL = 0x32AC; - CM4HWARN = 0x32B0; -_CM4HWARN = 0x32B0; - CM4LWARN = 0x32B4; -_CM4LWARN = 0x32B4; - FRCTUN = 0x32C0; -_FRCTUN = 0x32C0; -_FRCTUNbits = 0x32C0; - BFRCTUN = 0x32C4; -_BFRCTUN = 0x32C4; -_BFRCTUNbits = 0x32C4; - WDTCON = 0x32C8; -_WDTCON = 0x32C8; -_WDTCONbits = 0x32C8; - PTGCON = 0x3500; -_PTGCON = 0x3500; -_PTGCONbits = 0x3500; - PTGBTE = 0x3504; -_PTGBTE = 0x3504; - PTGHOLD = 0x3508; -_PTGHOLD = 0x3508; -_PTGHOLDbits = 0x3508; - PTGT0LIM = 0x350C; -_PTGT0LIM = 0x350C; -_PTGT0LIMbits = 0x350C; - PTGT1LIM = 0x3510; -_PTGT1LIM = 0x3510; -_PTGT1LIMbits = 0x3510; - PTGSDLIM = 0x3514; -_PTGSDLIM = 0x3514; -_PTGSDLIMbits = 0x3514; - PTGC0LIM = 0x3518; -_PTGC0LIM = 0x3518; -_PTGC0LIMbits = 0x3518; - PTGC1LIM = 0x351C; -_PTGC1LIM = 0x351C; -_PTGC1LIMbits = 0x351C; - PTGADJ = 0x3520; -_PTGADJ = 0x3520; -_PTGADJbits = 0x3520; - PTGL0 = 0x3524; -_PTGL0 = 0x3524; -_PTGL0bits = 0x3524; - PTGQPTR = 0x3528; -_PTGQPTR = 0x3528; -_PTGQPTRbits = 0x3528; - PTGQUE0 = 0x3530; -_PTGQUE0 = 0x3530; -_PTGQUE0bits = 0x3530; - PTGQUE1 = 0x3534; -_PTGQUE1 = 0x3534; -_PTGQUE1bits = 0x3534; - PTGQUE2 = 0x3538; -_PTGQUE2 = 0x3538; -_PTGQUE2bits = 0x3538; - PTGQUE3 = 0x353C; -_PTGQUE3 = 0x353C; -_PTGQUE3bits = 0x353C; - PTGQUE4 = 0x3540; -_PTGQUE4 = 0x3540; -_PTGQUE4bits = 0x3540; - PTGQUE5 = 0x3544; -_PTGQUE5 = 0x3544; -_PTGQUE5bits = 0x3544; - PTGQUE6 = 0x3548; -_PTGQUE6 = 0x3548; -_PTGQUE6bits = 0x3548; - PTGQUE7 = 0x354C; -_PTGQUE7 = 0x354C; -_PTGQUE7bits = 0x354C; - RAMXECCCON = 0x3580; -_RAMXECCCON = 0x3580; -_RAMXECCCONbits = 0x3580; - RAMXECCSTAT = 0x3584; -_RAMXECCSTAT = 0x3584; -_RAMXECCSTATbits = 0x3584; - RAMXECCFPTR = 0x3588; -_RAMXECCFPTR = 0x3588; -_RAMXECCFPTRbits = 0x3588; - RAMXECCFADDR = 0x358C; -_RAMXECCFADDR = 0x358C; - RAMXECCEADDR = 0x3590; -_RAMXECCEADDR = 0x3590; - RAMXECCEDATA = 0x3594; -_RAMXECCEDATA = 0x3594; - RAMXECCVAL = 0x3598; -_RAMXECCVAL = 0x3598; -_RAMXECCVALbits = 0x3598; - RAMXECCSYND = 0x359C; -_RAMXECCSYND = 0x359C; -_RAMXECCSYNDbits = 0x359C; - PWBXECCCON = 0x35A0; -_PWBXECCCON = 0x35A0; -_PWBXECCCONbits = 0x35A0; - PWBXECCSTAT = 0x35A4; -_PWBXECCSTAT = 0x35A4; -_PWBXECCSTATbits = 0x35A4; - PWBXECCFPTR = 0x35A8; -_PWBXECCFPTR = 0x35A8; -_PWBXECCFPTRbits = 0x35A8; - PWBXECCFADDR = 0x35AC; -_PWBXECCFADDR = 0x35AC; - PWBXECCEADDR = 0x35B0; -_PWBXECCEADDR = 0x35B0; - PWBXECCEDATA = 0x35B4; -_PWBXECCEDATA = 0x35B4; - PWBXECCVAL = 0x35B8; -_PWBXECCVAL = 0x35B8; -_PWBXECCVALbits = 0x35B8; - PWBXECCSYND = 0x35BC; -_PWBXECCSYND = 0x35BC; -_PWBXECCSYNDbits = 0x35BC; - RAMYECCCON = 0x35C0; -_RAMYECCCON = 0x35C0; -_RAMYECCCONbits = 0x35C0; - RAMYECCSTAT = 0x35C4; -_RAMYECCSTAT = 0x35C4; -_RAMYECCSTATbits = 0x35C4; - RAMYECCFPTR = 0x35C8; -_RAMYECCFPTR = 0x35C8; -_RAMYECCFPTRbits = 0x35C8; - RAMYECCFADDR = 0x35CC; -_RAMYECCFADDR = 0x35CC; - RAMYECCEADDR = 0x35D0; -_RAMYECCEADDR = 0x35D0; - RAMYECCEDATA = 0x35D4; -_RAMYECCEDATA = 0x35D4; - RAMYECCVAL = 0x35D8; -_RAMYECCVAL = 0x35D8; -_RAMYECCVALbits = 0x35D8; - RAMYECCSYND = 0x35DC; -_RAMYECCSYND = 0x35DC; -_RAMYECCSYNDbits = 0x35DC; - PWBYECCCON = 0x35E0; -_PWBYECCCON = 0x35E0; -_PWBYECCCONbits = 0x35E0; - PWBYECCSTAT = 0x35E4; -_PWBYECCSTAT = 0x35E4; -_PWBYECCSTATbits = 0x35E4; - PWBYECCFPTR = 0x35E8; -_PWBYECCFPTR = 0x35E8; -_PWBYECCFPTRbits = 0x35E8; - PWBYECCFADDR = 0x35EC; -_PWBYECCFADDR = 0x35EC; - PWBYECCEADDR = 0x35F0; -_PWBYECCEADDR = 0x35F0; - PWBYECCEDATA = 0x35F4; -_PWBYECCEDATA = 0x35F4; - PWBYECCVAL = 0x35F8; -_PWBYECCVAL = 0x35F8; -_PWBYECCVALbits = 0x35F8; - PWBYECCSYND = 0x35FC; -_PWBYECCSYND = 0x35FC; -_PWBYECCSYNDbits = 0x35FC; - ANSELA = 0x3640; -_ANSELA = 0x3640; -_ANSELAbits = 0x3640; - ODCA = 0x3644; -_ODCA = 0x3644; -_ODCAbits = 0x3644; - CNPUA = 0x3648; -_CNPUA = 0x3648; -_CNPUAbits = 0x3648; - CNPDA = 0x364C; -_CNPDA = 0x364C; -_CNPDAbits = 0x364C; - CNCONA = 0x3650; -_CNCONA = 0x3650; -_CNCONAbits = 0x3650; - CNEN0A = 0x3654; -_CNEN0A = 0x3654; -_CNEN0Abits = 0x3654; - CNEN1A = 0x3658; -_CNEN1A = 0x3658; -_CNEN1Abits = 0x3658; - ANSELB = 0x3664; -_ANSELB = 0x3664; -_ANSELBbits = 0x3664; - ODCB = 0x3668; -_ODCB = 0x3668; -_ODCBbits = 0x3668; - CNPUB = 0x366C; -_CNPUB = 0x366C; -_CNPUBbits = 0x366C; - CNPDB = 0x3670; -_CNPDB = 0x3670; -_CNPDBbits = 0x3670; - CNCONB = 0x3674; -_CNCONB = 0x3674; -_CNCONBbits = 0x3674; - CNEN0B = 0x3678; -_CNEN0B = 0x3678; -_CNEN0Bbits = 0x3678; - CNEN1B = 0x367C; -_CNEN1B = 0x367C; -_CNEN1Bbits = 0x367C; - ANSELC = 0x3688; -_ANSELC = 0x3688; - ODCC = 0x368C; -_ODCC = 0x368C; -_ODCCbits = 0x368C; - CNPUC = 0x3690; -_CNPUC = 0x3690; -_CNPUCbits = 0x3690; - CNPDC = 0x3694; -_CNPDC = 0x3694; -_CNPDCbits = 0x3694; - CNCONC = 0x3698; -_CNCONC = 0x3698; -_CNCONCbits = 0x3698; - CNEN0C = 0x369C; -_CNEN0C = 0x369C; -_CNEN0Cbits = 0x369C; - CNEN1C = 0x36A0; -_CNEN1C = 0x36A0; -_CNEN1Cbits = 0x36A0; - ANSELD = 0x36AC; -_ANSELD = 0x36AC; - ODCD = 0x36B0; -_ODCD = 0x36B0; -_ODCDbits = 0x36B0; - CNPUD = 0x36B4; -_CNPUD = 0x36B4; -_CNPUDbits = 0x36B4; - CNPDD = 0x36B8; -_CNPDD = 0x36B8; -_CNPDDbits = 0x36B8; - CNCOND = 0x36BC; -_CNCOND = 0x36BC; -_CNCONDbits = 0x36BC; - CNEN0D = 0x36C0; -_CNEN0D = 0x36C0; -_CNEN0Dbits = 0x36C0; - CNEN1D = 0x36C4; -_CNEN1D = 0x36C4; -_CNEN1Dbits = 0x36C4; - RPCON = 0x3900; -_RPCON = 0x3900; -_RPCONbits = 0x3900; - RPINR0 = 0x3904; -_RPINR0 = 0x3904; -_RPINR0bits = 0x3904; - RPINR1 = 0x3908; -_RPINR1 = 0x3908; -_RPINR1bits = 0x3908; - RPINR2 = 0x390C; -_RPINR2 = 0x390C; -_RPINR2bits = 0x390C; - RPINR5 = 0x3918; -_RPINR5 = 0x3918; -_RPINR5bits = 0x3918; - RPINR6 = 0x391C; -_RPINR6 = 0x391C; -_RPINR6bits = 0x391C; - RPINR7 = 0x3920; -_RPINR7 = 0x3920; -_RPINR7bits = 0x3920; - RPINR9 = 0x3928; -_RPINR9 = 0x3928; -_RPINR9bits = 0x3928; - RPINR10 = 0x392C; -_RPINR10 = 0x392C; -_RPINR10bits = 0x392C; - RPINR11 = 0x3930; -_RPINR11 = 0x3930; -_RPINR11bits = 0x3930; - RPINR13 = 0x3938; -_RPINR13 = 0x3938; -_RPINR13bits = 0x3938; - RPINR14 = 0x393C; -_RPINR14 = 0x393C; -_RPINR14bits = 0x393C; - RPINR15 = 0x3940; -_RPINR15 = 0x3940; -_RPINR15bits = 0x3940; - RPINR17 = 0x3948; -_RPINR17 = 0x3948; -_RPINR17bits = 0x3948; - RPINR18 = 0x394C; -_RPINR18 = 0x394C; -_RPINR18bits = 0x394C; - RPINR19 = 0x3950; -_RPINR19 = 0x3950; -_RPINR19bits = 0x3950; - RPINR20 = 0x3954; -_RPINR20 = 0x3954; -_RPINR20bits = 0x3954; - RPINR21 = 0x3958; -_RPINR21 = 0x3958; -_RPINR21bits = 0x3958; - RPOR0 = 0x3980; -_RPOR0 = 0x3980; -_RPOR0bits = 0x3980; - RPOR1 = 0x3984; -_RPOR1 = 0x3984; -_RPOR1bits = 0x3984; - RPOR2 = 0x3988; -_RPOR2 = 0x3988; -_RPOR2bits = 0x3988; - RPOR4 = 0x3990; -_RPOR4 = 0x3990; -_RPOR4bits = 0x3990; - RPOR5 = 0x3994; -_RPOR5 = 0x3994; -_RPOR5bits = 0x3994; - RPOR6 = 0x3998; -_RPOR6 = 0x3998; -_RPOR6bits = 0x3998; - RPOR8 = 0x39A0; -_RPOR8 = 0x39A0; -_RPOR8bits = 0x39A0; - RPOR9 = 0x39A4; -_RPOR9 = 0x39A4; -_RPOR9bits = 0x39A4; - RPOR10 = 0x39A8; -_RPOR10 = 0x39A8; -_RPOR10bits = 0x39A8; - RPOR12 = 0x39B0; -_RPOR12 = 0x39B0; -_RPOR12bits = 0x39B0; - RPOR13 = 0x39B4; -_RPOR13 = 0x39B4; -_RPOR13bits = 0x39B4; - RPOR14 = 0x39B8; -_RPOR14 = 0x39B8; -_RPOR14bits = 0x39B8; - RPOR15 = 0x39BC; -_RPOR15 = 0x39BC; -_RPOR15bits = 0x39BC; - RPOR16 = 0x39C0; -_RPOR16 = 0x39C0; -_RPOR16bits = 0x39C0; - RPOR17 = 0x39C4; -_RPOR17 = 0x39C4; -_RPOR17bits = 0x39C4; - RPOR18 = 0x39C8; -_RPOR18 = 0x39C8; -_RPOR18bits = 0x39C8; - RPOR19 = 0x39CC; -_RPOR19 = 0x39CC; -_RPOR19bits = 0x39CC; - DMTCON = 0x3A00; -_DMTCON = 0x3A00; -_DMTCONbits = 0x3A00; - DMTPRECLR = 0x3A04; -_DMTPRECLR = 0x3A04; -_DMTPRECLRbits = 0x3A04; - DMTCLR = 0x3A08; -_DMTCLR = 0x3A08; -_DMTCLRbits = 0x3A08; - DMTSTAT = 0x3A0C; -_DMTSTAT = 0x3A0C; -_DMTSTATbits = 0x3A0C; - DMTCNT = 0x3A10; -_DMTCNT = 0x3A10; - PSCNT = 0x3A14; -_PSCNT = 0x3A14; - PSINTV = 0x3A18; -_PSINTV = 0x3A18; - PPPC = 0x3A1C; -_PPPC = 0x3A1C; -_PPPCbits = 0x3A1C; - PPC = 0x3A20; -_PPC = 0x3A20; -_PPCbits = 0x3A20; - PMD1 = 0x3A44; -_PMD1 = 0x3A44; -_PMD1bits = 0x3A44; - PMD2 = 0x3A48; -_PMD2 = 0x3A48; -_PMD2bits = 0x3A48; - PMD3 = 0x3A4C; -_PMD3 = 0x3A4C; -_PMD3bits = 0x3A4C; - PMD4 = 0x3A50; -_PMD4 = 0x3A50; -_PMD4bits = 0x3A50; - CLC1CON = 0x3A60; -_CLC1CON = 0x3A60; -_CLC1CONbits = 0x3A60; - CLC1SEL = 0x3A64; -_CLC1SEL = 0x3A64; -_CLC1SELbits = 0x3A64; - CLC1GLS = 0x3A68; -_CLC1GLS = 0x3A68; -_CLC1GLSbits = 0x3A68; - CLC2CON = 0x3A70; -_CLC2CON = 0x3A70; -_CLC2CONbits = 0x3A70; - CLC2SEL = 0x3A74; -_CLC2SEL = 0x3A74; -_CLC2SELbits = 0x3A74; - CLC2GLS = 0x3A78; -_CLC2GLS = 0x3A78; -_CLC2GLSbits = 0x3A78; - CLC3CON = 0x3A80; -_CLC3CON = 0x3A80; -_CLC3CONbits = 0x3A80; - CLC3SEL = 0x3A84; -_CLC3SEL = 0x3A84; -_CLC3SELbits = 0x3A84; - CLC3GLS = 0x3A88; -_CLC3GLS = 0x3A88; -_CLC3GLSbits = 0x3A88; - CLC4CON = 0x3A90; -_CLC4CON = 0x3A90; -_CLC4CONbits = 0x3A90; - CLC4SEL = 0x3A94; -_CLC4SEL = 0x3A94; -_CLC4SELbits = 0x3A94; - CLC4GLS = 0x3A98; -_CLC4GLS = 0x3A98; -_CLC4GLSbits = 0x3A98; - MBISTCON = 0x3AA0; -_MBISTCON = 0x3AA0; -_MBISTCONbits = 0x3AA0; - IBIASCON = 0x3AA4; -_IBIASCON = 0x3AA4; -_IBIASCONbits = 0x3AA4; - AMP1CON1 = 0x3AB0; -_AMP1CON1 = 0x3AB0; -_AMP1CON1bits = 0x3AB0; - AMP1CON2 = 0x3AB4; -_AMP1CON2 = 0x3AB4; -_AMP1CON2bits = 0x3AB4; - AMP2CON1 = 0x3AB8; -_AMP2CON1 = 0x3AB8; -_AMP2CON1bits = 0x3AB8; - AMP2CON2 = 0x3ABC; -_AMP2CON2 = 0x3ABC; -_AMP2CON2bits = 0x3ABC; - AMP3CON1 = 0x3AC0; -_AMP3CON1 = 0x3AC0; -_AMP3CON1bits = 0x3AC0; - AMP3CON2 = 0x3AC4; -_AMP3CON2 = 0x3AC4; -_AMP3CON2bits = 0x3AC4; -/* -** ======= Base Addresses for Various Peripherals and ACC ====== -*/ - - SPI1 = 0x1808; -_SPI1 = 0x1808; - SPI2 = 0x1828; -_SPI2 = 0x1828; - SPI3 = 0x1848; -_SPI3 = 0x1848; +PROVIDE(__isr_wrapper = __COMMONInterrupt); diff --git a/include/zephyr/arch/dspic/thread.h b/include/zephyr/arch/dspic/thread.h index a70b79be3d14a..526dfa9cd6dec 100644 --- a/include/zephyr/arch/dspic/thread.h +++ b/include/zephyr/arch/dspic/thread.h @@ -94,6 +94,9 @@ struct _thread_arch { /* return value of z_swap */ uint32_t swap_return_value; + + /* flag to test whether to load return value*/ + uint32_t swapped_from_thread; }; typedef struct _thread_arch _thread_arch_t; diff --git a/include/zephyr/dt-bindings/pinctrl/mchp-p33ak128mc106-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/mchp-p33ak128mc106-pinctrl.h new file mode 100644 index 0000000000000..61d5a2c4261e6 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/mchp-p33ak128mc106-pinctrl.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MCHP_P33AK128MC106_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MCHP_P33AK128MC106_PINCTRL_H_ + +#include + +/* Masks & Shifts */ +#define DSPIC33_PORT_MASK 0x3U /* 2 bits for 0-3 */ +#define DSPIC33_PORT_SHIFT 30 + +#define DSPIC33_PIN_MASK 0x3FU /* 6 bits for 0-47 */ +#define DSPIC33_PIN_SHIFT 24 + +#define DSPIC33_FUNC_MASK 0xFFFFFFU /* 24 bits for 0-511 */ +#define DSPIC33_FUNC_SHIFT 0 + +/* Encode: pack port, pin, function */ +#define DSPIC33_PINMUX(port, pin, func) \ + ((((port) & DSPIC33_PORT_MASK) << DSPIC33_PORT_SHIFT) | \ + (((pin) & DSPIC33_PIN_MASK) << DSPIC33_PIN_SHIFT) | \ + (((func) & DSPIC33_FUNC_MASK) << DSPIC33_FUNC_SHIFT)) + +/* Decode: extract port, pin, function */ +#define DSPIC33_PINMUX_PORT(pinmux) (((pinmux) >> DSPIC33_PORT_SHIFT) & DSPIC33_PORT_MASK) +#define DSPIC33_PINMUX_PIN(pinmux) (((pinmux) >> DSPIC33_PIN_SHIFT) & DSPIC33_PIN_MASK) +#define DSPIC33_PINMUX_FUNC(pinmux) (((pinmux) >> DSPIC33_FUNC_SHIFT) & DSPIC33_FUNC_MASK) + +#define OFFSET_RPOR 0x3780 +#define OFFSET_RPIN 0x3704 +#define OFFSET_LATCH 0x0004 +#define OFFSET_TRIS 0x0008 +#define OFFSET_ANSEL 0x3440 + +/* Port definitions */ +#define PORT_A 0 +#define PORT_B 1 +#define PORT_C 2 +#define PORT_D 3 + +/* Input Function Macros (for RPINRx register configuration) */ +#define INT1 0x3905 +#define INT2 0x3906 +#define INT3 0x3907 +#define INT4 0x3908 +#define T1CK 0x3909 +#define REFI1 0x390A +#define REFI2 0x390B +#define ICM1 0x390C +#define ICM2 0x390D +#define ICM3 0x390E +#define ICM4 0x390F +#define OCFA 0x3918 +#define OCFB 0x3919 +#define OCFC 0x391A +#define OCFD 0x391B +#define PCI8 0x391C +#define PCI9 0x391D +#define PCI10 0x391E +#define PCI11 0x391F +#define QEIA1 0x3920 +#define QEIB1 0x3921 +#define QEINDX1 0x3922 +#define QEIHOM1 0x3923 +#define U1RX 0x3928 +#define U1DSR 0x3929 +#define U2RX 0x392A +#define U2DSR 0x392B +#define SDI1 0x392C +#define SCK1IN 0x392D +#define SS1 0x392E +#define SDI2 0x3930 +#define SCK2IN 0x3931 +#define SS2 0x3932 +#define U3RX 0x3938 +#define U3DSR 0x3939 +#define SENT1 0x393E +#define SENT2 0x393F +#define SDI3 0x3940 +#define SCK3IN 0x3941 +#define SS3 0x3942 +#define PCI12 0x3948 +#define PCI13 0x3949 +#define PCI14 0x394A +#define PCI15 0x394B +#define PCI16 0x394C +#define PCI17 0x394D +#define PCI18 0x394E +#define ADTRIG31 0x394F +#define BISS1SL 0x3950 +#define BISS1GS 0x3951 +#define CLCINA 0x3954 +#define CLCINB 0x3955 +#define CLCINC 0x3956 +#define CLCIND 0x3957 +#define U1CTS 0x3958 +#define U2CTS 0x3959 +#define U3CTS 0x395A + +/* Output Function Macros (for RPnR register configuration) */ +#define DEFAULT_PORT 0x00 +#define PWM1H 0x01 +#define PWM1L 0x02 +#define PWM2H 0x03 +#define PWM2L 0x04 +#define PWM3H 0x05 +#define PWM3L 0x06 +#define PWM4H 0x07 +#define PWM4L 0x08 +#define U1TX 0x09 +#define U1RTS 0x0A +#define U2TX 0x0B +#define U2RTS 0x0C +#define SDO1 0x0D +#define SCK1OUT 0x0E +#define SS1OUT 0x0F +#define SDO2 0x10 +#define SCK2OUT 0x11 +#define SS2OUT 0x12 +#define SDO3 0x13 +#define SCK3OUT 0x14 +#define SS3OUT 0x15 +#define REFO1 0x16 +#define REFO2 0x17 +#define OCM1 0x18 +#define OCM2 0x19 +#define OCM3 0x1A +#define OCM4 0x1B +#define CMP1 0x20 +#define CMP2 0x21 +#define CMP3 0x22 +#define U3TX 0x24 +#define U3RTS 0x25 +#define PEVTA 0x2B +#define PEVTB 0x2C +#define QEICMP1 0x2D +#define CLC1OUT 0x2F +#define CLC2OUT 0x30 +#define PEVTC 0x33 +#define PEVTD 0x34 +#define PEVTE 0x35 +#define PEVTF 0x36 +#define PTG_TRIG24 0x37 +#define PTG_TRIG25 0x38 +#define SENT1OUT 0x39 +#define SENT2OUT 0x3A +#define BISS1MO 0x3F +#define BISS1MA 0x40 +#define CLC3OUT 0x41 +#define CLC4OUT 0x42 +#define U1DTRn 0x43 +#define U2DTRn 0x44 +#define U3DTRn 0x45 + +#endif diff --git a/include/zephyr/dt-bindings/pinctrl/mchp-p33ak512mps512-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/mchp-p33ak512mps512-pinctrl.h new file mode 100644 index 0000000000000..a83ab58ee2a95 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/mchp-p33ak512mps512-pinctrl.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MCHP_P33AK512MPS512_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MCHP_P33AK512MPS512_PINCTRL_H_ + +#include + +/* Masks & Shifts */ +#define DSPIC33_PORT_MASK 0x7U /* 2 bits for 0-3 */ +#define DSPIC33_PORT_SHIFT 29 + +#define DSPIC33_PIN_MASK 0x0FU /* 4 bits for 0-11 */ +#define DSPIC33_PIN_SHIFT 24 + +#define DSPIC33_FUNC_MASK 0xFFFFFFU /* 24 bits for 0-511 */ +#define DSPIC33_FUNC_SHIFT 0 + +/* Encode: pack port, pin, function */ +#define DSPIC33_PINMUX(port, pin, func) \ + ((((port) & DSPIC33_PORT_MASK) << DSPIC33_PORT_SHIFT) | \ + (((pin) & DSPIC33_PIN_MASK) << DSPIC33_PIN_SHIFT) | \ + (((func) & DSPIC33_FUNC_MASK) << DSPIC33_FUNC_SHIFT)) + +/* Decode: extract port, pin, function */ +#define DSPIC33_PINMUX_PORT(pinmux) (((pinmux) >> DSPIC33_PORT_SHIFT) & DSPIC33_PORT_MASK) +#define DSPIC33_PINMUX_PIN(pinmux) (((pinmux) >> DSPIC33_PIN_SHIFT) & DSPIC33_PIN_MASK) +#define DSPIC33_PINMUX_FUNC(pinmux) (((pinmux) >> DSPIC33_FUNC_SHIFT) & DSPIC33_FUNC_MASK) + +#define OFFSET_RPOR 0x3150 +#define OFFSET_RPIN 0x30D4 +#define OFFSET_LATCH 0x0004 +#define OFFSET_TRIS 0x0008 +#define OFFSET_ANSEL 0x3440 + +/* Port definitions */ +#define PORT_A 0 +#define PORT_B 1 +#define PORT_C 2 +#define PORT_D 3 +#define PORT_E 4 +#define PORT_F 5 +#define PORT_G 6 +#define PORT_H 7 + +/* Input Function Macros (for RPINRx register configuration) */ +#define INT1 0x32D5 +#define INT2 0x32D6 +#define INT3 0x32D7 +#define INT4 0x32D8 +#define T1CK 0x32D9 +#define T2CK 0x32DA +#define T3CK 0x32DB +#define TCKI1 0x32DC +#define ICM1 0x32DD +#define TCKI2 0x32DE +#define ICM2 0x32DF +#define TCKI3 0x32E0 +#define ICM3 0x32E1 +#define TCKI4 0x32E2 +#define ICM4 0x32E3 +#define TCKI5 0x32E4 +#define ICM5 0x32E5 +#define TCKI6 0x32E6 +#define ICM6 0x32E7 +#define TCKI7 0x32E8 +#define ICM7 0x32E9 +#define TCKI8 0x32EA +#define ICM8 0x32EB +#define TCKI9 0x32EC +#define ICM9 0x32ED +#define RTCCTMP 0x32EE +#define RTCCPCLK 0x32EF +#define OCFAR 0x32F0 +#define OCFBR 0x32F1 +#define OCFCR 0x32F2 +#define OCFDR 0x32F3 +#define PCI8 0x32F4 +#define PCI9 0x32F5 +#define PCI10 0x32F6 +#define PCI11 0x32F7 +#define QEA1 0x32F8 +#define QEB1 0x32F9 +#define INDX1 0x32FA +#define HOME1 0x32FB +#define QEA2 0x32FC +#define QEB2 0x32FD +#define INDX2 0x32FE +#define HOME2 0x32FF +#define QEA3 0x3300 +#define QEB3 0x3301 +#define INDX3 0x3302 +#define HOME3 0x3303 +#define QEA4 0x3304 +#define QEB4 0x3305 +#define INDX4 0x3306 +#define HOME4 0x3307 +#define U1RX 0x3308 +#define U1DSR 0x3309 +#define U2RX 0x330A +#define U2DSR 0x330B +#define U3RX 0x330C +#define U3DSR 0x330D +#define SDI1 0x330E +#define SDK1 0x330F +#define SS1 0x3310 +#define SDI2 0x3311 +#define SDK2 0x3312 +#define SS2 0x3313 +#define SDI3 0x3314 +#define SDK3 0x3315 +#define SS3 0x3316 +#define SDI4 0x3317 +#define SDK4 0x3318 +#define SS4 0x3319 +#define CAN1RX 0x331A +#define CAN2RX 0x331B +#define SENT1 0x331C +#define SENT2 0x331D +#define REFI1 0x331E +#define REFI2 0x331F +#define PCI12 0x3320 +#define PCI13 0x3321 +#define PCI14 0x3322 +#define PCI15 0x3323 +#define PCI16 0x3324 +#define PCI17 0x3325 +#define PCI18 0x3326 +#define CLCINA 0x3327 +#define CLCINB 0x3328 +#define CLCINC 0x3329 +#define CLCIND 0x332A +#define CLCINE 0x332B +#define CLCINF 0x332C +#define CLCING 0x332D +#define CLCINH 0x332E +#define CLCINI 0x332F +#define CLCINJ 0x3330 +#define ADTRG 0x3331 +#define U1CTS 0x3332 +#define U2CTS 0x3333 +#define U3CTS 0x3334 +#define BISS1SL 0x3335 +#define BISS1GS 0x3336 +#define IOM0 0x3337 +#define IOM1 0x3338 +#define IOM2 0x3339 +#define IOM3 0x333A +#define IOM4 0x333B +#define IOM5 0x333C +#define IOM6 0x333D +#define IOM7 0x333E +#define PCI19 0x333F +#define PCI20 0x3340 +#define PCI21 0x3341 +#define PCI22 0x3342 + + +/* Output Function Macros (for RPnR register configuration) */ +#define DEFAULT_PORT 0x00 +#define PWM1H 0x01 +#define PWM1L 0x02 +#define PWM2H 0x03 +#define PWM2L 0x04 +#define PWM3H 0x05 +#define PWM3L 0x06 +#define PWM4H 0x07 +#define PWM4L 0x08 +#define PWM5L 0x09 +#define PWM5H 0x0A +#define PWM6L 0x0B +#define PWM6H 0x0C +#define PWM7L 0x0D +#define PWM7H 0x0E +#define PWM8L 0x0F +#define PWM8H 0x10 +#define CAN1TX 0x11 +#define CAN2TX 0x12 +#define U1TX 0x13 +#define U1RTS 0x14 +#define U2TX 0x15 +#define U2RTS 0x16 +#define U3TX 0x17 +#define U3RTS 0x18 +#define SDO1 0x19 +#define SCK1 0x1A +#define SS1OUT 0x1B +#define SDO2 0x1C +#define SCK2 0x1D +#define SS2OUT 0x1E +#define SDO3 0x1F +#define SCK3 0x20 +#define SS3OUT 0x21 +#define SDO4 0x22 +#define SCK4 0x23 +#define SS4OUT 0x24 +#define REFO1 0x25 +#define REFO2 0x26 +#define OCM1 0x27 +#define OCM2 0x28 +#define OCM3 0x29 +#define OCM4 0x2A +#define OCM5 0x2B +#define OCM6 0x2C +#define OCM7 0x2D +#define OCM8 0x2E +#define MCCP9A 0x2F +#define MCCP9B 0x30 +#define MCCP9C 0x31 +#define MCCP9D 0x32 +#define MCCP9E 0x33 +#define MCCP9F 0x34 +#define CMP1 0x35 +#define CMP2 0x36 +#define CMP3 0x37 +#define CMP4 0x38 +#define CMP5 0x39 +#define CMP6 0x3A +#define CMP7 0x3B +#define CMP8 0x3C +#define PEVTA 0x3D +#define PEVTB 0x3E +#define PEVTC 0x3F +#define PEVTD 0x40 +#define QEICMP1 0x41 +#define QEICMP2 0x42 +#define QEICMP3 0x43 +#define QEICMP4 0x44 +#define CLC1OUT 0x45 +#define CLC2OUT 0x46 +#define CLC3OUT 0x47 +#define CLC4OUT 0x48 +#define CLC5OUT 0x49 +#define CLC6OUT 0x4A +#define CLC7OUT 0x4B +#define CLC8OUT 0x4C +#define CLC9OUT 0x4D +#define CLC10OUT 0x4E +#define PTGTRG24 0x4F +#define PTGTRG25 0x50 +#define SENT1OUT 0x51 +#define SENT2OUT 0x52 +#define BISSMO1 0x53 +#define BISSMA1 0x54 +#define U1DTR 0x55 +#define U2DTR 0x56 +#define U3DTR 0x57 +#define APWM1H 0x58 +#define APWM1L 0x59 +#define APWM2H 0x5A +#define APWM2L 0x5B +#define APWM3H 0x5C +#define APWM3L 0x5D +#define APWM4H 0x5E +#define APWM4L 0x5F +#define APEVTA 0x60 +#define APEVTB 0x61 + +#endif diff --git a/include/zephyr/linker/linker-tool-xcdsc.h b/include/zephyr/linker/linker-tool-xcdsc.h index 529027be45035..111644d3c5b62 100644 --- a/include/zephyr/linker/linker-tool-xcdsc.h +++ b/include/zephyr/linker/linker-tool-xcdsc.h @@ -16,7 +16,11 @@ #include OUTPUT_FORMAT("elf32-pic30") +#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106) OUTPUT_ARCH("33AK128MC106") +#elif defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) +OUTPUT_ARCH("33AK512MPS512") +#endif /* * The GROUP_START() and GROUP_END() macros are used to define a group diff --git a/include/zephyr/toolchain/xcdsc.h b/include/zephyr/toolchain/xcdsc.h index a496d1c633a7f..26b161215f772 100644 --- a/include/zephyr/toolchain/xcdsc.h +++ b/include/zephyr/toolchain/xcdsc.h @@ -247,3 +247,7 @@ static inline int popcount(unsigned int x) #define __GENERIC_DOT_SECTION(segment) __attribute__((section("." STRINGIFY(segment)))) #define Z_GENERIC_DOT_SECTION(segment) __GENERIC_DOT_SECTION(segment) + +#define ALIAS_OF(of) __attribute__((alias(#of))) + +#define FUNC_ALIAS(real_func, new_alias, return_type) return_type new_alias() ALIAS_OF(real_func) diff --git a/kernel/include/kswap.h b/kernel/include/kswap.h index cff3efab6e90e..f25795d8c4181 100644 --- a/kernel/include/kswap.h +++ b/kernel/include/kswap.h @@ -206,7 +206,7 @@ static inline int z_swap_irqlock(unsigned int key) #ifdef CONFIG_SPIN_VALIDATE /* Refer to comment in do_swap() above for details */ -# ifndef CONFIG_ARM64 +# if !defined(CONFIG_ARM64) && !defined(CONFIG_DSPIC) __ASSERT(arch_irq_unlocked(key) || _current->base.thread_state & (_THREAD_DUMMY | _THREAD_DEAD), "Context switching while holding lock!"); diff --git a/kernel/thread.c b/kernel/thread.c index a23d4c2c36642..b7a8cfe221bc8 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -880,7 +880,7 @@ FUNC_NORETURN void k_thread_user_mode_enter(k_thread_entry_t entry, } #if defined(CONFIG_INIT_STACKS) && defined(CONFIG_THREAD_STACK_INFO) -#ifdef CONFIG_STACK_GROWS_UP +#if defined(CONFIG_STACK_GROWS_UP) && !defined(CONFIG_DSPIC) #error "Unsupported configuration for stack analysis" #endif /* CONFIG_STACK_GROWS_UP */ diff --git a/samples/basic/blinky/prj.conf b/samples/basic/blinky/prj.conf index 91c3c15b37d1e..fe2e63c01ec01 100644 --- a/samples/basic/blinky/prj.conf +++ b/samples/basic/blinky/prj.conf @@ -1 +1,5 @@ CONFIG_GPIO=y +CONFIG_PRINTK=y +CONFIG_RAM_CONSOLE=y +CONFIG_GPIO_DSPIC=y +CONFIG_STATIC_INIT_GNU=y diff --git a/samples/philosophers/src/main.c b/samples/philosophers/src/main.c index ddda605d5d21e..92d23af74fac0 100644 --- a/samples/philosophers/src/main.c +++ b/samples/philosophers/src/main.c @@ -59,8 +59,12 @@ #endif #ifndef NUM_PHIL +#if CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106 +#define NUM_PHIL 4 +#else #define NUM_PHIL 6 #endif +#endif #ifndef STATIC_OBJS #define STATIC_OBJS 0 diff --git a/samples/philosophers/src/phil_obj_abstract.h b/samples/philosophers/src/phil_obj_abstract.h index e749a3f8d4982..d8e898d5839e0 100644 --- a/samples/philosophers/src/phil_obj_abstract.h +++ b/samples/philosophers/src/phil_obj_abstract.h @@ -148,11 +148,28 @@ static fork_t forks[NUM_PHIL] = { #if STATIC_OBJS - &fork0, &fork1, &fork2, - &fork3, &fork4, &fork5, + &fork0, &fork1, + #if NUM_PHIL == 3 + &fork2, + #elif NUM_PHIL == 4 + &fork2, &fork3, + #elif NUM_PHIL == 5 + &fork2, &fork3, &fork4, + #elif NUM_PHIL == 6 + &fork2, &fork3, &fork4, &fork5, + #endif #else - (fork_t)&fork_objs[0], (fork_t)&fork_objs[1], (fork_t)&fork_objs[2], - (fork_t)&fork_objs[3], (fork_t)&fork_objs[4], (fork_t)&fork_objs[5], + (fork_t)&fork_objs[0], (fork_t)&fork_objs[1], + #if NUM_PHIL == 3 + (fork_t)&fork_objs[2], + #elif NUM_PHIL == 4 + (fork_t)&fork_objs[2], (fork_t)&fork_objs[3], + #elif NUM_PHIL == 5 + (fork_t)&fork_objs[2], (fork_t)&fork_objs[3], (fork_t)&fork_objs[4], + #elif NUM_PHIL == 6 + (fork_t)&fork_objs[2], (fork_t)&fork_objs[3], (fork_t)&fork_objs[4], + (fork_t)&fork_objs[5], + #endif #endif }; diff --git a/soc/microchip/dspic33/dspic33a/CMakeLists.txt b/soc/microchip/dspic33/dspic33a/CMakeLists.txt index fc4b7df67049a..2f2e2a20b86af 100644 --- a/soc/microchip/dspic33/dspic33a/CMakeLists.txt +++ b/soc/microchip/dspic33/dspic33a/CMakeLists.txt @@ -1,8 +1,14 @@ zephyr_include_directories(.) -zephyr_include_directories(${XCDSC_TOOLCHAIN_PATH}/support/generic/h) +zephyr_include_directories(${DFP_ROOT}/support/generic/h) zephyr_sources_ifdef(CONFIG_PM power.c ) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/dspic/linker.ld CACHE INTERNAL "" ) + +if(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106) + zephyr_ld_options(-T ${ZEPHYR_BASE}/soc/microchip/dspic33/dspic33a/p33ak128mc106_regs.ld) +elseif(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) + zephyr_ld_options(-T ${ZEPHYR_BASE}/soc/microchip/dspic33/dspic33a/p33ak512mps512_regs.ld) +endif() \ No newline at end of file diff --git a/soc/microchip/dspic33/dspic33a/Kconfig b/soc/microchip/dspic33/dspic33a/Kconfig index a51dc3592dced..d7b4cd98319d5 100644 --- a/soc/microchip/dspic33/dspic33a/Kconfig +++ b/soc/microchip/dspic33/dspic33a/Kconfig @@ -12,4 +12,3 @@ config SOC_SERIES_DSPIC33A select GEN_IRQ_VECTOR_TABLE select GEN_SW_ISR_TABLE select HAS_PM - select PM diff --git a/soc/microchip/dspic33/dspic33a/Kconfig.defconfig.p33ak128mc106 b/soc/microchip/dspic33/dspic33a/Kconfig.defconfig.p33ak128mc106 index 0ff17992b7a19..d42ac2707069a 100644 --- a/soc/microchip/dspic33/dspic33a/Kconfig.defconfig.p33ak128mc106 +++ b/soc/microchip/dspic33/dspic33a/Kconfig.defconfig.p33ak128mc106 @@ -16,8 +16,11 @@ config FLASH_BASE_ADDRESS default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) config MAIN_STACK_SIZE - default 128 + default 512 +config NUM_IRQS + default 279 + config IDLE_STACK_SIZE default 512 @@ -29,6 +32,10 @@ config NEWLIB_LIBC_SUPPORTED bool default n +config SPIN_VALIDATE + bool + default n + # Picolibc with C++ support in Zephyr SDK is handled by Zephyr SDK's own Kconfig. config PICOLIBC_SUPPORTED bool diff --git a/soc/microchip/dspic33/dspic33a/Kconfig.defconfig.p33ak512mps512 b/soc/microchip/dspic33/dspic33a/Kconfig.defconfig.p33ak512mps512 new file mode 100644 index 0000000000000..8590aa5121fb6 --- /dev/null +++ b/soc/microchip/dspic33/dspic33a/Kconfig.defconfig.p33ak512mps512 @@ -0,0 +1,44 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_P33AK512MPS512 + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K) + +config SRAM_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)) + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config MAIN_STACK_SIZE + default 512 + +config IDLE_STACK_SIZE + default 512 + +config NUM_IRQS + default 355 + +config MINIMAL_LIBC_SUPPORTED + bool + default n + +config NEWLIB_LIBC_SUPPORTED + bool + default n + +config SPIN_VALIDATE + bool + default n + +# Picolibc with C++ support in Zephyr SDK is handled by Zephyr SDK's own Kconfig. +config PICOLIBC_SUPPORTED + bool + default n + +endif # SOC_P33AK512MPS512 diff --git a/soc/microchip/dspic33/dspic33a/Kconfig.soc b/soc/microchip/dspic33/dspic33a/Kconfig.soc index 69cde09e0b3c1..ce681e7832048 100644 --- a/soc/microchip/dspic33/dspic33a/Kconfig.soc +++ b/soc/microchip/dspic33/dspic33a/Kconfig.soc @@ -11,6 +11,10 @@ select SOC_FAMILY_MICROCHIP_DSPIC33 config SOC_SERIES default "dspic33a" if SOC_SERIES_DSPIC33A +config SOC_P33AK512MPS512 + bool + select SOC_SERIES_DSPIC33A + config SOC_P33AK128MC106 bool select SOC_SERIES_DSPIC33A @@ -22,3 +26,4 @@ config SOC_P33AK256MC506 config SOC default "p33ak128mc106" if SOC_P33AK128MC106 default "p33ak256mc506" if SOC_P33AK256MC506 + default "p33ak512mps512" if SOC_P33AK512MPS512 diff --git a/soc/microchip/dspic33/dspic33a/p33ak128mc106_regs.ld b/soc/microchip/dspic33/dspic33a/p33ak128mc106_regs.ld new file mode 100644 index 0000000000000..1a0d04897a8f7 --- /dev/null +++ b/soc/microchip/dspic33/dspic33a/p33ak128mc106_regs.ld @@ -0,0 +1,2827 @@ +/* +** ============== Equates for SFR Addresses ============= +*/ +PC = 0x0; +_PC = 0x0; +_PCbits = 0x0; + SPLIM = 0x4; +_SPLIM = 0x4; +_SPLIMbits = 0x4; + RCOUNT = 0x8; +_RCOUNT = 0x8; + DISIIPL = 0xC; +_DISIIPL = 0xC; +_DISIIPLbits = 0xC; + CORCON = 0x10; +_CORCON = 0x10; +_CORCONbits = 0x10; + MODCON = 0x14; +_MODCON = 0x14; +_MODCONbits = 0x14; + XMODSRT = 0x18; +_XMODSRT = 0x18; +_XMODSRTbits = 0x18; + XMODEND = 0x1C; +_XMODEND = 0x1C; +_XMODENDbits = 0x1C; + YMODSRT = 0x20; +_YMODSRT = 0x20; +_YMODSRTbits = 0x20; + YMODEND = 0x24; +_YMODEND = 0x24; +_YMODENDbits = 0x24; + XBREV = 0x28; +_XBREV = 0x28; +_XBREVbits = 0x28; + PCTRAP = 0x2C; +_PCTRAP = 0x2C; +_PCTRAPbits = 0x2C; + FEX = 0x30; +_FEX = 0x30; + FEX2 = 0x34; +_FEX2 = 0x34; + PCHOLD = 0x38; +_PCHOLD = 0x38; +_PCHOLDbits = 0x38; + VFA = 0x3C; +_VFA = 0x3C; +_VFAbits = 0x3C; + INTCON1 = 0x70; +_INTCON1 = 0x70; +_INTCON1bits = 0x70; + INTCON2 = 0x74; +_INTCON2 = 0x74; +_INTCON2bits = 0x74; + INTCON3 = 0x78; +_INTCON3 = 0x78; +_INTCON3bits = 0x78; + INTCON4 = 0x7C; +_INTCON4 = 0x7C; +_INTCON4bits = 0x7C; + INTCON5 = 0x80; +_INTCON5 = 0x80; +_INTCON5bits = 0x80; + INTTREG = 0x84; +_INTTREG = 0x84; +_INTTREGbits = 0x84; + IVTBASE = 0x88; +_IVTBASE = 0x88; + IVTCREG = 0x8C; +_IVTCREG = 0x8C; +_IVTCREGbits = 0x8C; + IFS0 = 0x90; +_IFS0 = 0x90; +_IFS0bits = 0x90; + IFS1 = 0x94; +_IFS1 = 0x94; +_IFS1bits = 0x94; + IFS2 = 0x98; +_IFS2 = 0x98; +_IFS2bits = 0x98; + IFS3 = 0x9C; +_IFS3 = 0x9C; +_IFS3bits = 0x9C; + IFS4 = 0xA0; +_IFS4 = 0xA0; +_IFS4bits = 0xA0; + IFS5 = 0xA4; +_IFS5 = 0xA4; +_IFS5bits = 0xA4; + IFS6 = 0xA8; +_IFS6 = 0xA8; +_IFS6bits = 0xA8; + IFS7 = 0xAC; +_IFS7 = 0xAC; +_IFS7bits = 0xAC; + IFS8 = 0xB0; +_IFS8 = 0xB0; +_IFS8bits = 0xB0; + IEC0 = 0xB4; +_IEC0 = 0xB4; +_IEC0bits = 0xB4; + IEC1 = 0xB8; +_IEC1 = 0xB8; +_IEC1bits = 0xB8; + IEC2 = 0xBC; +_IEC2 = 0xBC; +_IEC2bits = 0xBC; + IEC3 = 0xC0; +_IEC3 = 0xC0; +_IEC3bits = 0xC0; + IEC4 = 0xC4; +_IEC4 = 0xC4; +_IEC4bits = 0xC4; + IEC5 = 0xC8; +_IEC5 = 0xC8; +_IEC5bits = 0xC8; + IEC6 = 0xCC; +_IEC6 = 0xCC; +_IEC6bits = 0xCC; + IEC7 = 0xD0; +_IEC7 = 0xD0; +_IEC7bits = 0xD0; + IEC8 = 0xD4; +_IEC8 = 0xD4; +_IEC8bits = 0xD4; + IPC0 = 0xD8; +_IPC0 = 0xD8; +_IPC0bits = 0xD8; + IPC1 = 0xDC; +_IPC1 = 0xDC; +_IPC1bits = 0xDC; + IPC2 = 0xE0; +_IPC2 = 0xE0; +_IPC2bits = 0xE0; + IPC3 = 0xE4; +_IPC3 = 0xE4; +_IPC3bits = 0xE4; + IPC4 = 0xE8; +_IPC4 = 0xE8; +_IPC4bits = 0xE8; + IPC5 = 0xEC; +_IPC5 = 0xEC; +_IPC5bits = 0xEC; + IPC6 = 0xF0; +_IPC6 = 0xF0; +_IPC6bits = 0xF0; + IPC7 = 0xF4; +_IPC7 = 0xF4; +_IPC7bits = 0xF4; + IPC8 = 0xF8; +_IPC8 = 0xF8; +_IPC8bits = 0xF8; + IPC9 = 0xFC; +_IPC9 = 0xFC; +_IPC9bits = 0xFC; + IPC10 = 0x100; +_IPC10 = 0x100; +_IPC10bits = 0x100; + IPC11 = 0x104; +_IPC11 = 0x104; +_IPC11bits = 0x104; + IPC12 = 0x108; +_IPC12 = 0x108; +_IPC12bits = 0x108; + IPC13 = 0x10C; +_IPC13 = 0x10C; +_IPC13bits = 0x10C; + IPC14 = 0x110; +_IPC14 = 0x110; +_IPC14bits = 0x110; + IPC15 = 0x114; +_IPC15 = 0x114; +_IPC15bits = 0x114; + IPC16 = 0x118; +_IPC16 = 0x118; +_IPC16bits = 0x118; + IPC17 = 0x11C; +_IPC17 = 0x11C; +_IPC17bits = 0x11C; + IPC18 = 0x120; +_IPC18 = 0x120; +_IPC18bits = 0x120; + IPC19 = 0x124; +_IPC19 = 0x124; +_IPC19bits = 0x124; + IPC20 = 0x128; +_IPC20 = 0x128; +_IPC20bits = 0x128; + IPC21 = 0x12C; +_IPC21 = 0x12C; +_IPC21bits = 0x12C; + IPC22 = 0x130; +_IPC22 = 0x130; +_IPC22bits = 0x130; + IPC23 = 0x134; +_IPC23 = 0x134; +_IPC23bits = 0x134; + IPC24 = 0x138; +_IPC24 = 0x138; +_IPC24bits = 0x138; + IPC25 = 0x13C; +_IPC25 = 0x13C; +_IPC25bits = 0x13C; + IPC26 = 0x140; +_IPC26 = 0x140; +_IPC26bits = 0x140; + IPC27 = 0x144; +_IPC27 = 0x144; +_IPC27bits = 0x144; + IPC28 = 0x148; +_IPC28 = 0x148; +_IPC28bits = 0x148; + IPC29 = 0x14C; +_IPC29 = 0x14C; +_IPC29bits = 0x14C; + IPC35 = 0x160; +_IPC35 = 0x160; +_IPC35bits = 0x160; + PORTA = 0x200; +_PORTA = 0x200; +_PORTAbits = 0x200; + LATA = 0x204; +_LATA = 0x204; +_LATAbits = 0x204; + TRISA = 0x208; +_TRISA = 0x208; +_TRISAbits = 0x208; + CNSTATA = 0x20C; +_CNSTATA = 0x20C; +_CNSTATAbits = 0x20C; + CNFA = 0x210; +_CNFA = 0x210; +_CNFAbits = 0x210; + PORTB = 0x214; +_PORTB = 0x214; +_PORTBbits = 0x214; + LATB = 0x218; +_LATB = 0x218; +_LATBbits = 0x218; + TRISB = 0x21C; +_TRISB = 0x21C; +_TRISBbits = 0x21C; + CNSTATB = 0x220; +_CNSTATB = 0x220; +_CNSTATBbits = 0x220; + CNFB = 0x224; +_CNFB = 0x224; +_CNFBbits = 0x224; + PORTC = 0x228; +_PORTC = 0x228; +_PORTCbits = 0x228; + LATC = 0x22C; +_LATC = 0x22C; +_LATCbits = 0x22C; + TRISC = 0x230; +_TRISC = 0x230; +_TRISCbits = 0x230; + CNSTATC = 0x234; +_CNSTATC = 0x234; +_CNSTATCbits = 0x234; + CNFC = 0x238; +_CNFC = 0x238; +_CNFCbits = 0x238; + PORTD = 0x23C; +_PORTD = 0x23C; +_PORTDbits = 0x23C; + LATD = 0x240; +_LATD = 0x240; +_LATDbits = 0x240; + TRISD = 0x244; +_TRISD = 0x244; +_TRISDbits = 0x244; + CNSTATD = 0x248; +_CNSTATD = 0x248; +_CNSTATDbits = 0x248; + CNFD = 0x24C; +_CNFD = 0x24C; +_CNFDbits = 0x24C; + CRCCON = 0x2C8; +_CRCCON = 0x2C8; +_CRCCONbits = 0x2C8; + CRCXOR = 0x2CC; +_CRCXOR = 0x2CC; +_CRCXORbits = 0x2CC; + CRCDAT = 0x2D0; +_CRCDAT = 0x2D0; + CRCWDAT = 0x2D4; +_CRCWDAT = 0x2D4; + UCPROT = 0x2E0; +_UCPROT = 0x2E0; +_UCPROTbits = 0x2E0; + IRTCTRL = 0x2E4; +_IRTCTRL = 0x2E4; +_IRTCTRLbits = 0x2E4; + IRTSTAT = 0x2E8; +_IRTSTAT = 0x2E8; + PR0CTRL = 0x300; +_PR0CTRL = 0x300; +_PR0CTRLbits = 0x300; + PR0ST = 0x304; +_PR0ST = 0x304; +_PR0STbits = 0x304; + PR0END = 0x308; +_PR0END = 0x308; +_PR0ENDbits = 0x308; + PR0LOCK = 0x30C; +_PR0LOCK = 0x30C; +_PR0LOCKbits = 0x30C; + PR1CTRL = 0x310; +_PR1CTRL = 0x310; +_PR1CTRLbits = 0x310; + PR1ST = 0x314; +_PR1ST = 0x314; +_PR1STbits = 0x314; + PR1END = 0x318; +_PR1END = 0x318; +_PR1ENDbits = 0x318; + PR1LOCK = 0x31C; +_PR1LOCK = 0x31C; +_PR1LOCKbits = 0x31C; + PR2CTRL = 0x320; +_PR2CTRL = 0x320; +_PR2CTRLbits = 0x320; + PR2ST = 0x324; +_PR2ST = 0x324; +_PR2STbits = 0x324; + PR2END = 0x328; +_PR2END = 0x328; +_PR2ENDbits = 0x328; + PR2LOCK = 0x32C; +_PR2LOCK = 0x32C; +_PR2LOCKbits = 0x32C; + PR3CTRL = 0x330; +_PR3CTRL = 0x330; +_PR3CTRLbits = 0x330; + PR3ST = 0x334; +_PR3ST = 0x334; +_PR3STbits = 0x334; + PR3END = 0x338; +_PR3END = 0x338; +_PR3ENDbits = 0x338; + PR3LOCK = 0x33C; +_PR3LOCK = 0x33C; +_PR3LOCKbits = 0x33C; + PR4CTRL = 0x340; +_PR4CTRL = 0x340; +_PR4CTRLbits = 0x340; + PR4ST = 0x344; +_PR4ST = 0x344; +_PR4STbits = 0x344; + PR4END = 0x348; +_PR4END = 0x348; +_PR4ENDbits = 0x348; + PR4LOCK = 0x34C; +_PR4LOCK = 0x34C; +_PR4LOCKbits = 0x34C; + PR5CTRL = 0x350; +_PR5CTRL = 0x350; +_PR5CTRLbits = 0x350; + PR5ST = 0x354; +_PR5ST = 0x354; +_PR5STbits = 0x354; + PR5END = 0x358; +_PR5END = 0x358; +_PR5ENDbits = 0x358; + PR5LOCK = 0x35C; +_PR5LOCK = 0x35C; +_PR5LOCKbits = 0x35C; + PR6CTRL = 0x360; +_PR6CTRL = 0x360; +_PR6CTRLbits = 0x360; + PR6ST = 0x364; +_PR6ST = 0x364; +_PR6STbits = 0x364; + PR6END = 0x368; +_PR6END = 0x368; +_PR6ENDbits = 0x368; + PR6LOCK = 0x36C; +_PR6LOCK = 0x36C; +_PR6LOCKbits = 0x36C; + PR7CTRL = 0x370; +_PR7CTRL = 0x370; +_PR7CTRLbits = 0x370; + PR7ST = 0x374; +_PR7ST = 0x374; +_PR7STbits = 0x374; + PR7END = 0x378; +_PR7END = 0x378; +_PR7ENDbits = 0x378; + PR7LOCK = 0x37C; +_PR7LOCK = 0x37C; +_PR7LOCKbits = 0x37C; + BMXINITPR = 0x770; +_BMXINITPR = 0x770; +_BMXINITPRbits = 0x770; + BMXIRAML = 0x774; +_BMXIRAML = 0x774; + BMXIRAMH = 0x778; +_BMXIRAMH = 0x778; + BMXXDATERR = 0x77C; +_BMXXDATERR = 0x77C; +_BMXXDATERRbits = 0x77C; + BMXYDATERR = 0x780; +_BMXYDATERR = 0x780; +_BMXYDATERRbits = 0x780; + BMXDMAERR = 0x784; +_BMXDMAERR = 0x784; +_BMXDMAERRbits = 0x784; + BMXNVMERR = 0x788; +_BMXNVMERR = 0x788; +_BMXNVMERRbits = 0x788; + BMXICDERR = 0x78C; +_BMXICDERR = 0x78C; +_BMXICDERRbits = 0x78C; + AD1CON = 0x800; +_AD1CON = 0x800; +_AD1CONbits = 0x800; + AD1DATAOVR = 0x804; +_AD1DATAOVR = 0x804; + AD1STAT = 0x808; +_AD1STAT = 0x808; +_AD1STATbits = 0x808; + AD1CMPSTAT = 0x80C; +_AD1CMPSTAT = 0x80C; +_AD1CMPSTATbits = 0x80C; + AD1SWTRG = 0x810; +_AD1SWTRG = 0x810; +_AD1SWTRGbits = 0x810; + AD1CH0CON = 0x814; +_AD1CH0CON = 0x814; +_AD1CH0CONbits = 0x814; + AD1CH0DATA = 0x818; +_AD1CH0DATA = 0x818; + AD1CH0CNT = 0x81C; +_AD1CH0CNT = 0x81C; +_AD1CH0CNTbits = 0x81C; + AD1CH0CMPLO = 0x820; +_AD1CH0CMPLO = 0x820; + AD1CH0CMPHI = 0x824; +_AD1CH0CMPHI = 0x824; + AD1CH0ACC = 0x828; +_AD1CH0ACC = 0x828; + AD1CH1CON = 0x82C; +_AD1CH1CON = 0x82C; +_AD1CH1CONbits = 0x82C; + AD1CH1DATA = 0x830; +_AD1CH1DATA = 0x830; + AD1CH1CNT = 0x834; +_AD1CH1CNT = 0x834; +_AD1CH1CNTbits = 0x834; + AD1CH1CMPLO = 0x838; +_AD1CH1CMPLO = 0x838; + AD1CH1CMPHI = 0x83C; +_AD1CH1CMPHI = 0x83C; + AD1CH1ACC = 0x840; +_AD1CH1ACC = 0x840; + AD1CH2CON = 0x844; +_AD1CH2CON = 0x844; +_AD1CH2CONbits = 0x844; + AD1CH2DATA = 0x848; +_AD1CH2DATA = 0x848; + AD1CH2CNT = 0x84C; +_AD1CH2CNT = 0x84C; +_AD1CH2CNTbits = 0x84C; + AD1CH2CMPLO = 0x850; +_AD1CH2CMPLO = 0x850; + AD1CH2CMPHI = 0x854; +_AD1CH2CMPHI = 0x854; + AD1CH2ACC = 0x858; +_AD1CH2ACC = 0x858; + AD1CH3CON = 0x85C; +_AD1CH3CON = 0x85C; +_AD1CH3CONbits = 0x85C; + AD1CH3DATA = 0x860; +_AD1CH3DATA = 0x860; + AD1CH3CNT = 0x864; +_AD1CH3CNT = 0x864; +_AD1CH3CNTbits = 0x864; + AD1CH3CMPLO = 0x868; +_AD1CH3CMPLO = 0x868; + AD1CH3CMPHI = 0x86C; +_AD1CH3CMPHI = 0x86C; + AD1CH3ACC = 0x870; +_AD1CH3ACC = 0x870; + AD1CH4CON = 0x874; +_AD1CH4CON = 0x874; +_AD1CH4CONbits = 0x874; + AD1CH4DATA = 0x878; +_AD1CH4DATA = 0x878; + AD1CH4CNT = 0x87C; +_AD1CH4CNT = 0x87C; +_AD1CH4CNTbits = 0x87C; + AD1CH4CMPLO = 0x880; +_AD1CH4CMPLO = 0x880; + AD1CH4CMPHI = 0x884; +_AD1CH4CMPHI = 0x884; + AD1CH4ACC = 0x888; +_AD1CH4ACC = 0x888; + AD1CH5CON = 0x88C; +_AD1CH5CON = 0x88C; +_AD1CH5CONbits = 0x88C; + AD1CH5DATA = 0x890; +_AD1CH5DATA = 0x890; + AD1CH5CNT = 0x894; +_AD1CH5CNT = 0x894; +_AD1CH5CNTbits = 0x894; + AD1CH5CMPLO = 0x898; +_AD1CH5CMPLO = 0x898; + AD1CH5CMPHI = 0x89C; +_AD1CH5CMPHI = 0x89C; + AD1CH5ACC = 0x8A0; +_AD1CH5ACC = 0x8A0; + AD1CH6CON = 0x8A4; +_AD1CH6CON = 0x8A4; +_AD1CH6CONbits = 0x8A4; + AD1CH6DATA = 0x8A8; +_AD1CH6DATA = 0x8A8; + AD1CH6CNT = 0x8AC; +_AD1CH6CNT = 0x8AC; +_AD1CH6CNTbits = 0x8AC; + AD1CH6CMPLO = 0x8B0; +_AD1CH6CMPLO = 0x8B0; + AD1CH6CMPHI = 0x8B4; +_AD1CH6CMPHI = 0x8B4; + AD1CH6ACC = 0x8B8; +_AD1CH6ACC = 0x8B8; + AD1CH7CON = 0x8BC; +_AD1CH7CON = 0x8BC; +_AD1CH7CONbits = 0x8BC; + AD1CH7DATA = 0x8C0; +_AD1CH7DATA = 0x8C0; + AD1CH7CNT = 0x8C4; +_AD1CH7CNT = 0x8C4; +_AD1CH7CNTbits = 0x8C4; + AD1CH7CMPLO = 0x8C8; +_AD1CH7CMPLO = 0x8C8; + AD1CH7CMPHI = 0x8CC; +_AD1CH7CMPHI = 0x8CC; + AD1CH7ACC = 0x8D0; +_AD1CH7ACC = 0x8D0; + AD1CH8CON = 0x8D4; +_AD1CH8CON = 0x8D4; +_AD1CH8CONbits = 0x8D4; + AD1CH8DATA = 0x8D8; +_AD1CH8DATA = 0x8D8; + AD1CH8CNT = 0x8DC; +_AD1CH8CNT = 0x8DC; +_AD1CH8CNTbits = 0x8DC; + AD1CH8CMPLO = 0x8E0; +_AD1CH8CMPLO = 0x8E0; + AD1CH8CMPHI = 0x8E4; +_AD1CH8CMPHI = 0x8E4; + AD1CH8ACC = 0x8E8; +_AD1CH8ACC = 0x8E8; + AD1CH9CON = 0x8EC; +_AD1CH9CON = 0x8EC; +_AD1CH9CONbits = 0x8EC; + AD1CH9DATA = 0x8F0; +_AD1CH9DATA = 0x8F0; + AD1CH9CNT = 0x8F4; +_AD1CH9CNT = 0x8F4; +_AD1CH9CNTbits = 0x8F4; + AD1CH9CMPLO = 0x8F8; +_AD1CH9CMPLO = 0x8F8; + AD1CH9CMPHI = 0x8FC; +_AD1CH9CMPHI = 0x8FC; + AD1CH9ACC = 0x900; +_AD1CH9ACC = 0x900; + AD1CH10CON = 0x904; +_AD1CH10CON = 0x904; +_AD1CH10CONbits = 0x904; + AD1CH10DATA = 0x908; +_AD1CH10DATA = 0x908; + AD1CH10CNT = 0x90C; +_AD1CH10CNT = 0x90C; +_AD1CH10CNTbits = 0x90C; + AD1CH10CMPLO = 0x910; +_AD1CH10CMPLO = 0x910; + AD1CH10CMPHI = 0x914; +_AD1CH10CMPHI = 0x914; + AD1CH10ACC = 0x918; +_AD1CH10ACC = 0x918; + AD1CH11CON = 0x91C; +_AD1CH11CON = 0x91C; +_AD1CH11CONbits = 0x91C; + AD1CH11DATA = 0x920; +_AD1CH11DATA = 0x920; + AD1CH11CNT = 0x924; +_AD1CH11CNT = 0x924; +_AD1CH11CNTbits = 0x924; + AD1CH11CMPLO = 0x928; +_AD1CH11CMPLO = 0x928; + AD1CH11CMPHI = 0x92C; +_AD1CH11CMPHI = 0x92C; + AD1CH11ACC = 0x930; +_AD1CH11ACC = 0x930; + AD1CH12CON = 0x934; +_AD1CH12CON = 0x934; +_AD1CH12CONbits = 0x934; + AD1CH12DATA = 0x938; +_AD1CH12DATA = 0x938; + AD1CH12CNT = 0x93C; +_AD1CH12CNT = 0x93C; +_AD1CH12CNTbits = 0x93C; + AD1CH12CMPLO = 0x940; +_AD1CH12CMPLO = 0x940; + AD1CH12CMPHI = 0x944; +_AD1CH12CMPHI = 0x944; + AD1CH12ACC = 0x948; +_AD1CH12ACC = 0x948; + AD1CH13CON = 0x94C; +_AD1CH13CON = 0x94C; +_AD1CH13CONbits = 0x94C; + AD1CH13DATA = 0x950; +_AD1CH13DATA = 0x950; + AD1CH13CNT = 0x954; +_AD1CH13CNT = 0x954; +_AD1CH13CNTbits = 0x954; + AD1CH13CMPLO = 0x958; +_AD1CH13CMPLO = 0x958; + AD1CH13CMPHI = 0x95C; +_AD1CH13CMPHI = 0x95C; + AD1CH13ACC = 0x960; +_AD1CH13ACC = 0x960; + AD1CH14CON = 0x964; +_AD1CH14CON = 0x964; +_AD1CH14CONbits = 0x964; + AD1CH14DATA = 0x968; +_AD1CH14DATA = 0x968; + AD1CH14CNT = 0x96C; +_AD1CH14CNT = 0x96C; +_AD1CH14CNTbits = 0x96C; + AD1CH14CMPLO = 0x970; +_AD1CH14CMPLO = 0x970; + AD1CH14CMPHI = 0x974; +_AD1CH14CMPHI = 0x974; + AD1CH14ACC = 0x978; +_AD1CH14ACC = 0x978; + AD1CH15CON = 0x97C; +_AD1CH15CON = 0x97C; +_AD1CH15CONbits = 0x97C; + AD1CH15DATA = 0x980; +_AD1CH15DATA = 0x980; + AD1CH15CNT = 0x984; +_AD1CH15CNT = 0x984; +_AD1CH15CNTbits = 0x984; + AD1CH15CMPLO = 0x988; +_AD1CH15CMPLO = 0x988; + AD1CH15CMPHI = 0x98C; +_AD1CH15CMPHI = 0x98C; + AD1CH15ACC = 0x990; +_AD1CH15ACC = 0x990; + AD1CH16CON = 0x994; +_AD1CH16CON = 0x994; +_AD1CH16CONbits = 0x994; + AD1CH16DATA = 0x998; +_AD1CH16DATA = 0x998; + AD1CH16CNT = 0x99C; +_AD1CH16CNT = 0x99C; +_AD1CH16CNTbits = 0x99C; + AD1CH16CMPLO = 0x9A0; +_AD1CH16CMPLO = 0x9A0; + AD1CH16CMPHI = 0x9A4; +_AD1CH16CMPHI = 0x9A4; + AD1CH16ACC = 0x9A8; +_AD1CH16ACC = 0x9A8; + AD1CH17CON = 0x9AC; +_AD1CH17CON = 0x9AC; +_AD1CH17CONbits = 0x9AC; + AD1CH17DATA = 0x9B0; +_AD1CH17DATA = 0x9B0; + AD1CH17CNT = 0x9B4; +_AD1CH17CNT = 0x9B4; +_AD1CH17CNTbits = 0x9B4; + AD1CH17CMPLO = 0x9B8; +_AD1CH17CMPLO = 0x9B8; + AD1CH17CMPHI = 0x9BC; +_AD1CH17CMPHI = 0x9BC; + AD1CH17ACC = 0x9C0; +_AD1CH17ACC = 0x9C0; + AD1CH18CON = 0x9C4; +_AD1CH18CON = 0x9C4; +_AD1CH18CONbits = 0x9C4; + AD1CH18DATA = 0x9C8; +_AD1CH18DATA = 0x9C8; + AD1CH18CNT = 0x9CC; +_AD1CH18CNT = 0x9CC; +_AD1CH18CNTbits = 0x9CC; + AD1CH18CMPLO = 0x9D0; +_AD1CH18CMPLO = 0x9D0; + AD1CH18CMPHI = 0x9D4; +_AD1CH18CMPHI = 0x9D4; + AD1CH18ACC = 0x9D8; +_AD1CH18ACC = 0x9D8; + AD1CH19CON = 0x9DC; +_AD1CH19CON = 0x9DC; +_AD1CH19CONbits = 0x9DC; + AD1CH19DATA = 0x9E0; +_AD1CH19DATA = 0x9E0; + AD1CH19CNT = 0x9E4; +_AD1CH19CNT = 0x9E4; +_AD1CH19CNTbits = 0x9E4; + AD1CH19CMPLO = 0x9E8; +_AD1CH19CMPLO = 0x9E8; + AD1CH19CMPHI = 0x9EC; +_AD1CH19CMPHI = 0x9EC; + AD1CH19ACC = 0x9F0; +_AD1CH19ACC = 0x9F0; + AD2CON = 0xA00; +_AD2CON = 0xA00; +_AD2CONbits = 0xA00; + AD2DATAOVR = 0xA04; +_AD2DATAOVR = 0xA04; + AD2STAT = 0xA08; +_AD2STAT = 0xA08; +_AD2STATbits = 0xA08; + AD2CMPSTAT = 0xA0C; +_AD2CMPSTAT = 0xA0C; +_AD2CMPSTATbits = 0xA0C; + AD2SWTRG = 0xA10; +_AD2SWTRG = 0xA10; +_AD2SWTRGbits = 0xA10; + AD2CH0CON = 0xA14; +_AD2CH0CON = 0xA14; +_AD2CH0CONbits = 0xA14; + AD2CH0DATA = 0xA18; +_AD2CH0DATA = 0xA18; + AD2CH0CNT = 0xA1C; +_AD2CH0CNT = 0xA1C; +_AD2CH0CNTbits = 0xA1C; + AD2CH0CMPLO = 0xA20; +_AD2CH0CMPLO = 0xA20; + AD2CH0CMPHI = 0xA24; +_AD2CH0CMPHI = 0xA24; + AD2CH0ACC = 0xA28; +_AD2CH0ACC = 0xA28; + AD2CH1CON = 0xA2C; +_AD2CH1CON = 0xA2C; +_AD2CH1CONbits = 0xA2C; + AD2CH1DATA = 0xA30; +_AD2CH1DATA = 0xA30; + AD2CH1CNT = 0xA34; +_AD2CH1CNT = 0xA34; +_AD2CH1CNTbits = 0xA34; + AD2CH1CMPLO = 0xA38; +_AD2CH1CMPLO = 0xA38; + AD2CH1CMPHI = 0xA3C; +_AD2CH1CMPHI = 0xA3C; + AD2CH1ACC = 0xA40; +_AD2CH1ACC = 0xA40; + AD2CH2CON = 0xA44; +_AD2CH2CON = 0xA44; +_AD2CH2CONbits = 0xA44; + AD2CH2DATA = 0xA48; +_AD2CH2DATA = 0xA48; + AD2CH2CNT = 0xA4C; +_AD2CH2CNT = 0xA4C; +_AD2CH2CNTbits = 0xA4C; + AD2CH2CMPLO = 0xA50; +_AD2CH2CMPLO = 0xA50; + AD2CH2CMPHI = 0xA54; +_AD2CH2CMPHI = 0xA54; + AD2CH2ACC = 0xA58; +_AD2CH2ACC = 0xA58; + AD2CH3CON = 0xA5C; +_AD2CH3CON = 0xA5C; +_AD2CH3CONbits = 0xA5C; + AD2CH3DATA = 0xA60; +_AD2CH3DATA = 0xA60; + AD2CH3CNT = 0xA64; +_AD2CH3CNT = 0xA64; +_AD2CH3CNTbits = 0xA64; + AD2CH3CMPLO = 0xA68; +_AD2CH3CMPLO = 0xA68; + AD2CH3CMPHI = 0xA6C; +_AD2CH3CMPHI = 0xA6C; + AD2CH3ACC = 0xA70; +_AD2CH3ACC = 0xA70; + AD2CH4CON = 0xA74; +_AD2CH4CON = 0xA74; +_AD2CH4CONbits = 0xA74; + AD2CH4DATA = 0xA78; +_AD2CH4DATA = 0xA78; + AD2CH4CNT = 0xA7C; +_AD2CH4CNT = 0xA7C; +_AD2CH4CNTbits = 0xA7C; + AD2CH4CMPLO = 0xA80; +_AD2CH4CMPLO = 0xA80; + AD2CH4CMPHI = 0xA84; +_AD2CH4CMPHI = 0xA84; + AD2CH4ACC = 0xA88; +_AD2CH4ACC = 0xA88; + AD2CH5CON = 0xA8C; +_AD2CH5CON = 0xA8C; +_AD2CH5CONbits = 0xA8C; + AD2CH5DATA = 0xA90; +_AD2CH5DATA = 0xA90; + AD2CH5CNT = 0xA94; +_AD2CH5CNT = 0xA94; +_AD2CH5CNTbits = 0xA94; + AD2CH5CMPLO = 0xA98; +_AD2CH5CMPLO = 0xA98; + AD2CH5CMPHI = 0xA9C; +_AD2CH5CMPHI = 0xA9C; + AD2CH5ACC = 0xAA0; +_AD2CH5ACC = 0xAA0; + AD2CH6CON = 0xAA4; +_AD2CH6CON = 0xAA4; +_AD2CH6CONbits = 0xAA4; + AD2CH6DATA = 0xAA8; +_AD2CH6DATA = 0xAA8; + AD2CH6CNT = 0xAAC; +_AD2CH6CNT = 0xAAC; +_AD2CH6CNTbits = 0xAAC; + AD2CH6CMPLO = 0xAB0; +_AD2CH6CMPLO = 0xAB0; + AD2CH6CMPHI = 0xAB4; +_AD2CH6CMPHI = 0xAB4; + AD2CH6ACC = 0xAB8; +_AD2CH6ACC = 0xAB8; + AD2CH7CON = 0xABC; +_AD2CH7CON = 0xABC; +_AD2CH7CONbits = 0xABC; + AD2CH7DATA = 0xAC0; +_AD2CH7DATA = 0xAC0; + AD2CH7CNT = 0xAC4; +_AD2CH7CNT = 0xAC4; +_AD2CH7CNTbits = 0xAC4; + AD2CH7CMPLO = 0xAC8; +_AD2CH7CMPLO = 0xAC8; + AD2CH7CMPHI = 0xACC; +_AD2CH7CMPHI = 0xACC; + AD2CH7ACC = 0xAD0; +_AD2CH7ACC = 0xAD0; + AD2CH8CON = 0xAD4; +_AD2CH8CON = 0xAD4; +_AD2CH8CONbits = 0xAD4; + AD2CH8DATA = 0xAD8; +_AD2CH8DATA = 0xAD8; + AD2CH8CNT = 0xADC; +_AD2CH8CNT = 0xADC; +_AD2CH8CNTbits = 0xADC; + AD2CH8CMPLO = 0xAE0; +_AD2CH8CMPLO = 0xAE0; + AD2CH8CMPHI = 0xAE4; +_AD2CH8CMPHI = 0xAE4; + AD2CH8ACC = 0xAE8; +_AD2CH8ACC = 0xAE8; + AD2CH9CON = 0xAEC; +_AD2CH9CON = 0xAEC; +_AD2CH9CONbits = 0xAEC; + AD2CH9DATA = 0xAF0; +_AD2CH9DATA = 0xAF0; + AD2CH9CNT = 0xAF4; +_AD2CH9CNT = 0xAF4; +_AD2CH9CNTbits = 0xAF4; + AD2CH9CMPLO = 0xAF8; +_AD2CH9CMPLO = 0xAF8; + AD2CH9CMPHI = 0xAFC; +_AD2CH9CMPHI = 0xAFC; + AD2CH9ACC = 0xB00; +_AD2CH9ACC = 0xB00; + AD2CH10CON = 0xB04; +_AD2CH10CON = 0xB04; +_AD2CH10CONbits = 0xB04; + AD2CH10DATA = 0xB08; +_AD2CH10DATA = 0xB08; + AD2CH10CNT = 0xB0C; +_AD2CH10CNT = 0xB0C; +_AD2CH10CNTbits = 0xB0C; + AD2CH10CMPLO = 0xB10; +_AD2CH10CMPLO = 0xB10; + AD2CH10CMPHI = 0xB14; +_AD2CH10CMPHI = 0xB14; + AD2CH10ACC = 0xB18; +_AD2CH10ACC = 0xB18; + AD2CH11CON = 0xB1C; +_AD2CH11CON = 0xB1C; +_AD2CH11CONbits = 0xB1C; + AD2CH11DATA = 0xB20; +_AD2CH11DATA = 0xB20; + AD2CH11CNT = 0xB24; +_AD2CH11CNT = 0xB24; +_AD2CH11CNTbits = 0xB24; + AD2CH11CMPLO = 0xB28; +_AD2CH11CMPLO = 0xB28; + AD2CH11CMPHI = 0xB2C; +_AD2CH11CMPHI = 0xB2C; + AD2CH11ACC = 0xB30; +_AD2CH11ACC = 0xB30; + AD2CH12CON = 0xB34; +_AD2CH12CON = 0xB34; +_AD2CH12CONbits = 0xB34; + AD2CH12DATA = 0xB38; +_AD2CH12DATA = 0xB38; + AD2CH12CNT = 0xB3C; +_AD2CH12CNT = 0xB3C; +_AD2CH12CNTbits = 0xB3C; + AD2CH12CMPLO = 0xB40; +_AD2CH12CMPLO = 0xB40; + AD2CH12CMPHI = 0xB44; +_AD2CH12CMPHI = 0xB44; + AD2CH12ACC = 0xB48; +_AD2CH12ACC = 0xB48; + AD2CH13CON = 0xB4C; +_AD2CH13CON = 0xB4C; +_AD2CH13CONbits = 0xB4C; + AD2CH13DATA = 0xB50; +_AD2CH13DATA = 0xB50; + AD2CH13CNT = 0xB54; +_AD2CH13CNT = 0xB54; +_AD2CH13CNTbits = 0xB54; + AD2CH13CMPLO = 0xB58; +_AD2CH13CMPLO = 0xB58; + AD2CH13CMPHI = 0xB5C; +_AD2CH13CMPHI = 0xB5C; + AD2CH13ACC = 0xB60; +_AD2CH13ACC = 0xB60; + AD2CH14CON = 0xB64; +_AD2CH14CON = 0xB64; +_AD2CH14CONbits = 0xB64; + AD2CH14DATA = 0xB68; +_AD2CH14DATA = 0xB68; + AD2CH14CNT = 0xB6C; +_AD2CH14CNT = 0xB6C; +_AD2CH14CNTbits = 0xB6C; + AD2CH14CMPLO = 0xB70; +_AD2CH14CMPLO = 0xB70; + AD2CH14CMPHI = 0xB74; +_AD2CH14CMPHI = 0xB74; + AD2CH14ACC = 0xB78; +_AD2CH14ACC = 0xB78; + AD2CH15CON = 0xB7C; +_AD2CH15CON = 0xB7C; +_AD2CH15CONbits = 0xB7C; + AD2CH15DATA = 0xB80; +_AD2CH15DATA = 0xB80; + AD2CH15CNT = 0xB84; +_AD2CH15CNT = 0xB84; +_AD2CH15CNTbits = 0xB84; + AD2CH15CMPLO = 0xB88; +_AD2CH15CMPLO = 0xB88; + AD2CH15CMPHI = 0xB8C; +_AD2CH15CMPHI = 0xB8C; + AD2CH15ACC = 0xB90; +_AD2CH15ACC = 0xB90; + AD2CH16CON = 0xB94; +_AD2CH16CON = 0xB94; +_AD2CH16CONbits = 0xB94; + AD2CH16DATA = 0xB98; +_AD2CH16DATA = 0xB98; + AD2CH16CNT = 0xB9C; +_AD2CH16CNT = 0xB9C; +_AD2CH16CNTbits = 0xB9C; + AD2CH16CMPLO = 0xBA0; +_AD2CH16CMPLO = 0xBA0; + AD2CH16CMPHI = 0xBA4; +_AD2CH16CMPHI = 0xBA4; + AD2CH16ACC = 0xBA8; +_AD2CH16ACC = 0xBA8; + AD2CH17CON = 0xBAC; +_AD2CH17CON = 0xBAC; +_AD2CH17CONbits = 0xBAC; + AD2CH17DATA = 0xBB0; +_AD2CH17DATA = 0xBB0; + AD2CH17CNT = 0xBB4; +_AD2CH17CNT = 0xBB4; +_AD2CH17CNTbits = 0xBB4; + AD2CH17CMPLO = 0xBB8; +_AD2CH17CMPLO = 0xBB8; + AD2CH17CMPHI = 0xBBC; +_AD2CH17CMPHI = 0xBBC; + AD2CH17ACC = 0xBC0; +_AD2CH17ACC = 0xBC0; + AD2CH18CON = 0xBC4; +_AD2CH18CON = 0xBC4; +_AD2CH18CONbits = 0xBC4; + AD2CH18DATA = 0xBC8; +_AD2CH18DATA = 0xBC8; + AD2CH18CNT = 0xBCC; +_AD2CH18CNT = 0xBCC; +_AD2CH18CNTbits = 0xBCC; + AD2CH18CMPLO = 0xBD0; +_AD2CH18CMPLO = 0xBD0; + AD2CH18CMPHI = 0xBD4; +_AD2CH18CMPHI = 0xBD4; + AD2CH18ACC = 0xBD8; +_AD2CH18ACC = 0xBD8; + AD2CH19CON = 0xBDC; +_AD2CH19CON = 0xBDC; +_AD2CH19CONbits = 0xBDC; + AD2CH19DATA = 0xBE0; +_AD2CH19DATA = 0xBE0; + AD2CH19CNT = 0xBE4; +_AD2CH19CNT = 0xBE4; +_AD2CH19CNTbits = 0xBE4; + AD2CH19CMPLO = 0xBE8; +_AD2CH19CMPLO = 0xBE8; + AD2CH19CMPHI = 0xBEC; +_AD2CH19CMPHI = 0xBEC; + AD2CH19ACC = 0xBF0; +_AD2CH19ACC = 0xBF0; + PCLKCON = 0x1000; +_PCLKCON = 0x1000; +_PCLKCONbits = 0x1000; + FSCL = 0x1004; +_FSCL = 0x1004; +_FSCLbits = 0x1004; + FSMINPER = 0x1008; +_FSMINPER = 0x1008; +_FSMINPERbits = 0x1008; + MPHASE = 0x100C; +_MPHASE = 0x100C; +_MPHASEbits = 0x100C; + MDC = 0x1010; +_MDC = 0x1010; +_MDCbits = 0x1010; + MPER = 0x1014; +_MPER = 0x1014; +_MPERbits = 0x1014; + LFSR = 0x1018; +_LFSR = 0x1018; +_LFSRbits = 0x1018; + CMBTRIG = 0x101C; +_CMBTRIG = 0x101C; +_CMBTRIGbits = 0x101C; + LOGCONA = 0x1020; +_LOGCONA = 0x1020; +_LOGCONAbits = 0x1020; + LOGCONB = 0x1024; +_LOGCONB = 0x1024; +_LOGCONBbits = 0x1024; + LOGCONC = 0x1028; +_LOGCONC = 0x1028; +_LOGCONCbits = 0x1028; + LOGCOND = 0x102C; +_LOGCOND = 0x102C; +_LOGCONDbits = 0x102C; + LOGCONE = 0x1030; +_LOGCONE = 0x1030; +_LOGCONEbits = 0x1030; + LOGCONF = 0x1034; +_LOGCONF = 0x1034; +_LOGCONFbits = 0x1034; + PWMEVTA = 0x1038; +_PWMEVTA = 0x1038; +_PWMEVTAbits = 0x1038; + PWMEVTB = 0x103C; +_PWMEVTB = 0x103C; +_PWMEVTBbits = 0x103C; + PWMEVTC = 0x1040; +_PWMEVTC = 0x1040; +_PWMEVTCbits = 0x1040; + PWMEVTD = 0x1044; +_PWMEVTD = 0x1044; +_PWMEVTDbits = 0x1044; + PWMEVTE = 0x1048; +_PWMEVTE = 0x1048; +_PWMEVTEbits = 0x1048; + PWMEVTF = 0x104C; +_PWMEVTF = 0x104C; +_PWMEVTFbits = 0x104C; + PG1CON = 0x1050; +_PG1CON = 0x1050; +_PG1CONbits = 0x1050; + PG1STAT = 0x1054; +_PG1STAT = 0x1054; +_PG1STATbits = 0x1054; + PG1IOCON = 0x1058; +_PG1IOCON = 0x1058; +_PG1IOCONbits = 0x1058; + PG1EVT = 0x105C; +_PG1EVT = 0x105C; +_PG1EVTbits = 0x105C; + PG1FPCI = 0x1060; +_PG1FPCI = 0x1060; +_PG1FPCIbits = 0x1060; + PG1CLPCI = 0x1064; +_PG1CLPCI = 0x1064; +_PG1CLPCIbits = 0x1064; + PG1FFPCI = 0x1068; +_PG1FFPCI = 0x1068; +_PG1FFPCIbits = 0x1068; + PG1SPCI = 0x106C; +_PG1SPCI = 0x106C; +_PG1SPCIbits = 0x106C; + PG1LEB = 0x1070; +_PG1LEB = 0x1070; +_PG1LEBbits = 0x1070; + PG1PHASE = 0x1074; +_PG1PHASE = 0x1074; +_PG1PHASEbits = 0x1074; + PG1DC = 0x1078; +_PG1DC = 0x1078; +_PG1DCbits = 0x1078; + PG1DCA = 0x107C; +_PG1DCA = 0x107C; +_PG1DCAbits = 0x107C; + PG1PER = 0x1080; +_PG1PER = 0x1080; +_PG1PERbits = 0x1080; + PG1TRIGA = 0x1084; +_PG1TRIGA = 0x1084; +_PG1TRIGAbits = 0x1084; + PG1TRIGB = 0x1088; +_PG1TRIGB = 0x1088; +_PG1TRIGBbits = 0x1088; + PG1TRIGC = 0x108C; +_PG1TRIGC = 0x108C; +_PG1TRIGCbits = 0x108C; + PG1DT = 0x1090; +_PG1DT = 0x1090; +_PG1DTbits = 0x1090; + PG1CAP = 0x1094; +_PG1CAP = 0x1094; +_PG1CAPbits = 0x1094; + PG2CON = 0x1098; +_PG2CON = 0x1098; +_PG2CONbits = 0x1098; + PG2STAT = 0x109C; +_PG2STAT = 0x109C; +_PG2STATbits = 0x109C; + PG2IOCON = 0x10A0; +_PG2IOCON = 0x10A0; +_PG2IOCONbits = 0x10A0; + PG2EVT = 0x10A4; +_PG2EVT = 0x10A4; +_PG2EVTbits = 0x10A4; + PG2FPCI = 0x10A8; +_PG2FPCI = 0x10A8; +_PG2FPCIbits = 0x10A8; + PG2CLPCI = 0x10AC; +_PG2CLPCI = 0x10AC; +_PG2CLPCIbits = 0x10AC; + PG2FFPCI = 0x10B0; +_PG2FFPCI = 0x10B0; +_PG2FFPCIbits = 0x10B0; + PG2SPCI = 0x10B4; +_PG2SPCI = 0x10B4; +_PG2SPCIbits = 0x10B4; + PG2LEB = 0x10B8; +_PG2LEB = 0x10B8; +_PG2LEBbits = 0x10B8; + PG2PHASE = 0x10BC; +_PG2PHASE = 0x10BC; +_PG2PHASEbits = 0x10BC; + PG2DC = 0x10C0; +_PG2DC = 0x10C0; +_PG2DCbits = 0x10C0; + PG2DCA = 0x10C4; +_PG2DCA = 0x10C4; +_PG2DCAbits = 0x10C4; + PG2PER = 0x10C8; +_PG2PER = 0x10C8; +_PG2PERbits = 0x10C8; + PG2TRIGA = 0x10CC; +_PG2TRIGA = 0x10CC; +_PG2TRIGAbits = 0x10CC; + PG2TRIGB = 0x10D0; +_PG2TRIGB = 0x10D0; +_PG2TRIGBbits = 0x10D0; + PG2TRIGC = 0x10D4; +_PG2TRIGC = 0x10D4; +_PG2TRIGCbits = 0x10D4; + PG2DT = 0x10D8; +_PG2DT = 0x10D8; +_PG2DTbits = 0x10D8; + PG2CAP = 0x10DC; +_PG2CAP = 0x10DC; +_PG2CAPbits = 0x10DC; + PG3CON = 0x10E0; +_PG3CON = 0x10E0; +_PG3CONbits = 0x10E0; + PG3STAT = 0x10E4; +_PG3STAT = 0x10E4; +_PG3STATbits = 0x10E4; + PG3IOCON = 0x10E8; +_PG3IOCON = 0x10E8; +_PG3IOCONbits = 0x10E8; + PG3EVT = 0x10EC; +_PG3EVT = 0x10EC; +_PG3EVTbits = 0x10EC; + PG3FPCI = 0x10F0; +_PG3FPCI = 0x10F0; +_PG3FPCIbits = 0x10F0; + PG3CLPCI = 0x10F4; +_PG3CLPCI = 0x10F4; +_PG3CLPCIbits = 0x10F4; + PG3FFPCI = 0x10F8; +_PG3FFPCI = 0x10F8; +_PG3FFPCIbits = 0x10F8; + PG3SPCI = 0x10FC; +_PG3SPCI = 0x10FC; +_PG3SPCIbits = 0x10FC; + PG3LEB = 0x1100; +_PG3LEB = 0x1100; +_PG3LEBbits = 0x1100; + PG3PHASE = 0x1104; +_PG3PHASE = 0x1104; +_PG3PHASEbits = 0x1104; + PG3DC = 0x1108; +_PG3DC = 0x1108; +_PG3DCbits = 0x1108; + PG3DCA = 0x110C; +_PG3DCA = 0x110C; +_PG3DCAbits = 0x110C; + PG3PER = 0x1110; +_PG3PER = 0x1110; +_PG3PERbits = 0x1110; + PG3TRIGA = 0x1114; +_PG3TRIGA = 0x1114; +_PG3TRIGAbits = 0x1114; + PG3TRIGB = 0x1118; +_PG3TRIGB = 0x1118; +_PG3TRIGBbits = 0x1118; + PG3TRIGC = 0x111C; +_PG3TRIGC = 0x111C; +_PG3TRIGCbits = 0x111C; + PG3DT = 0x1120; +_PG3DT = 0x1120; +_PG3DTbits = 0x1120; + PG3CAP = 0x1124; +_PG3CAP = 0x1124; +_PG3CAPbits = 0x1124; + PG4CON = 0x1128; +_PG4CON = 0x1128; +_PG4CONbits = 0x1128; + PG4STAT = 0x112C; +_PG4STAT = 0x112C; +_PG4STATbits = 0x112C; + PG4IOCON = 0x1130; +_PG4IOCON = 0x1130; +_PG4IOCONbits = 0x1130; + PG4EVT = 0x1134; +_PG4EVT = 0x1134; +_PG4EVTbits = 0x1134; + PG4FPCI = 0x1138; +_PG4FPCI = 0x1138; +_PG4FPCIbits = 0x1138; + PG4CLPCI = 0x113C; +_PG4CLPCI = 0x113C; +_PG4CLPCIbits = 0x113C; + PG4FFPCI = 0x1140; +_PG4FFPCI = 0x1140; +_PG4FFPCIbits = 0x1140; + PG4SPCI = 0x1144; +_PG4SPCI = 0x1144; +_PG4SPCIbits = 0x1144; + PG4LEB = 0x1148; +_PG4LEB = 0x1148; +_PG4LEBbits = 0x1148; + PG4PHASE = 0x114C; +_PG4PHASE = 0x114C; +_PG4PHASEbits = 0x114C; + PG4DC = 0x1150; +_PG4DC = 0x1150; +_PG4DCbits = 0x1150; + PG4DCA = 0x1154; +_PG4DCA = 0x1154; +_PG4DCAbits = 0x1154; + PG4PER = 0x1158; +_PG4PER = 0x1158; +_PG4PERbits = 0x1158; + PG4TRIGA = 0x115C; +_PG4TRIGA = 0x115C; +_PG4TRIGAbits = 0x115C; + PG4TRIGB = 0x1160; +_PG4TRIGB = 0x1160; +_PG4TRIGBbits = 0x1160; + PG4TRIGC = 0x1164; +_PG4TRIGC = 0x1164; +_PG4TRIGCbits = 0x1164; + PG4DT = 0x1168; +_PG4DT = 0x1168; +_PG4DTbits = 0x1168; + PG4CAP = 0x116C; +_PG4CAP = 0x116C; +_PG4CAPbits = 0x116C; + U1CON = 0x1700; +_U1CON = 0x1700; +_U1CONbits = 0x1700; + U1STAT = 0x1704; +_U1STAT = 0x1704; +_U1STATbits = 0x1704; + U1BRG = 0x1708; +_U1BRG = 0x1708; +_U1BRGbits = 0x1708; + U1RXB = 0x170C; +_U1RXB = 0x170C; +_U1RXBbits = 0x170C; + U1TXB = 0x1710; +_U1TXB = 0x1710; +_U1TXBbits = 0x1710; + U1PA = 0x1714; +_U1PA = 0x1714; +_U1PAbits = 0x1714; + U1PB = 0x1718; +_U1PB = 0x1718; +_U1PBbits = 0x1718; + U1CHK = 0x171C; +_U1CHK = 0x171C; +_U1CHKbits = 0x171C; + U1SCCON = 0x1720; +_U1SCCON = 0x1720; +_U1SCCONbits = 0x1720; + U1UIR = 0x1724; +_U1UIR = 0x1724; +_U1UIRbits = 0x1724; + U2CON = 0x1740; +_U2CON = 0x1740; +_U2CONbits = 0x1740; + U2STAT = 0x1744; +_U2STAT = 0x1744; +_U2STATbits = 0x1744; + U2BRG = 0x1748; +_U2BRG = 0x1748; +_U2BRGbits = 0x1748; + U2RXB = 0x174C; +_U2RXB = 0x174C; +_U2RXBbits = 0x174C; + U2TXB = 0x1750; +_U2TXB = 0x1750; +_U2TXBbits = 0x1750; + U2PA = 0x1754; +_U2PA = 0x1754; +_U2PAbits = 0x1754; + U2PB = 0x1758; +_U2PB = 0x1758; +_U2PBbits = 0x1758; + U2CHK = 0x175C; +_U2CHK = 0x175C; +_U2CHKbits = 0x175C; + U2SCCON = 0x1760; +_U2SCCON = 0x1760; +_U2SCCONbits = 0x1760; + U2UIR = 0x1764; +_U2UIR = 0x1764; +_U2UIRbits = 0x1764; + U3CON = 0x1780; +_U3CON = 0x1780; +_U3CONbits = 0x1780; + U3STAT = 0x1784; +_U3STAT = 0x1784; +_U3STATbits = 0x1784; + U3BRG = 0x1788; +_U3BRG = 0x1788; +_U3BRGbits = 0x1788; + U3RXB = 0x178C; +_U3RXB = 0x178C; +_U3RXBbits = 0x178C; + U3TXB = 0x1790; +_U3TXB = 0x1790; +_U3TXBbits = 0x1790; + U3PA = 0x1794; +_U3PA = 0x1794; +_U3PAbits = 0x1794; + U3PB = 0x1798; +_U3PB = 0x1798; +_U3PBbits = 0x1798; + U3CHK = 0x179C; +_U3CHK = 0x179C; +_U3CHKbits = 0x179C; + U3SCCON = 0x17A0; +_U3SCCON = 0x17A0; +_U3SCCONbits = 0x17A0; + U3UIR = 0x17A4; +_U3UIR = 0x17A4; +_U3UIRbits = 0x17A4; + SPI1CON1 = 0x1800; +_SPI1CON1 = 0x1800; +_SPI1CON1bits = 0x1800; + SPI1CON2 = 0x1804; +_SPI1CON2 = 0x1804; +_SPI1CON2bits = 0x1804; + SPI1STAT = 0x1808; +_SPI1STAT = 0x1808; +_SPI1STATbits = 0x1808; + SPI1BUF = 0x180C; +_SPI1BUF = 0x180C; + SPI1BRG = 0x1810; +_SPI1BRG = 0x1810; +_SPI1BRGbits = 0x1810; + SPI1IMSK = 0x1814; +_SPI1IMSK = 0x1814; +_SPI1IMSKbits = 0x1814; + SPI1URDT = 0x1818; +_SPI1URDT = 0x1818; + SPI2CON1 = 0x1820; +_SPI2CON1 = 0x1820; +_SPI2CON1bits = 0x1820; + SPI2CON2 = 0x1824; +_SPI2CON2 = 0x1824; +_SPI2CON2bits = 0x1824; + SPI2STAT = 0x1828; +_SPI2STAT = 0x1828; +_SPI2STATbits = 0x1828; + SPI2BUF = 0x182C; +_SPI2BUF = 0x182C; + SPI2BRG = 0x1830; +_SPI2BRG = 0x1830; +_SPI2BRGbits = 0x1830; + SPI2IMSK = 0x1834; +_SPI2IMSK = 0x1834; +_SPI2IMSKbits = 0x1834; + SPI2URDT = 0x1838; +_SPI2URDT = 0x1838; + SPI3CON1 = 0x1840; +_SPI3CON1 = 0x1840; +_SPI3CON1bits = 0x1840; + SPI3CON2 = 0x1844; +_SPI3CON2 = 0x1844; +_SPI3CON2bits = 0x1844; + SPI3STAT = 0x1848; +_SPI3STAT = 0x1848; +_SPI3STATbits = 0x1848; + SPI3BUF = 0x184C; +_SPI3BUF = 0x184C; + SPI3BRG = 0x1850; +_SPI3BRG = 0x1850; +_SPI3BRGbits = 0x1850; + SPI3IMSK = 0x1854; +_SPI3IMSK = 0x1854; +_SPI3IMSKbits = 0x1854; + SPI3URDT = 0x1858; +_SPI3URDT = 0x1858; + I2C1CON1 = 0x1880; +_I2C1CON1 = 0x1880; +_I2C1CON1bits = 0x1880; + I2C1STAT1 = 0x1884; +_I2C1STAT1 = 0x1884; +_I2C1STAT1bits = 0x1884; + I2C1ADD = 0x1888; +_I2C1ADD = 0x1888; +_I2C1ADDbits = 0x1888; + I2C1MSK = 0x188C; +_I2C1MSK = 0x188C; +_I2C1MSKbits = 0x188C; + I2C1HBRG = 0x1890; +_I2C1HBRG = 0x1890; +_I2C1HBRGbits = 0x1890; + I2C1TRN = 0x1894; +_I2C1TRN = 0x1894; +_I2C1TRNbits = 0x1894; + I2C1RCV = 0x1898; +_I2C1RCV = 0x1898; +_I2C1RCVbits = 0x1898; + I2C1CON2 = 0x189C; +_I2C1CON2 = 0x189C; +_I2C1CON2bits = 0x189C; + I2C1LBRG = 0x18A0; +_I2C1LBRG = 0x18A0; +_I2C1LBRGbits = 0x18A0; + I2C1INTC = 0x18A4; +_I2C1INTC = 0x18A4; +_I2C1INTCbits = 0x18A4; + I2C1STAT2 = 0x18A8; +_I2C1STAT2 = 0x18A8; +_I2C1STAT2bits = 0x18A8; + I2C1PEC = 0x18AC; +_I2C1PEC = 0x18AC; +_I2C1PECbits = 0x18AC; + I2C1BTO = 0x18B0; +_I2C1BTO = 0x18B0; +_I2C1BTObits = 0x18B0; + I2C1HBCTO = 0x18B4; +_I2C1HBCTO = 0x18B4; +_I2C1HBCTObits = 0x18B4; + I2C1CBCTO = 0x18B8; +_I2C1CBCTO = 0x18B8; +_I2C1CBCTObits = 0x18B8; + I2C1BITO = 0x18BC; +_I2C1BITO = 0x18BC; +_I2C1BITObits = 0x18BC; + I2C1SDASUT = 0x18C0; +_I2C1SDASUT = 0x18C0; +_I2C1SDASUTbits = 0x18C0; + I2C2CON1 = 0x18D0; +_I2C2CON1 = 0x18D0; +_I2C2CON1bits = 0x18D0; + I2C2STAT1 = 0x18D4; +_I2C2STAT1 = 0x18D4; +_I2C2STAT1bits = 0x18D4; + I2C2ADD = 0x18D8; +_I2C2ADD = 0x18D8; +_I2C2ADDbits = 0x18D8; + I2C2MSK = 0x18DC; +_I2C2MSK = 0x18DC; +_I2C2MSKbits = 0x18DC; + I2C2HBRG = 0x18E0; +_I2C2HBRG = 0x18E0; +_I2C2HBRGbits = 0x18E0; + I2C2TRN = 0x18E4; +_I2C2TRN = 0x18E4; +_I2C2TRNbits = 0x18E4; + I2C2RCV = 0x18E8; +_I2C2RCV = 0x18E8; +_I2C2RCVbits = 0x18E8; + I2C2CON2 = 0x18EC; +_I2C2CON2 = 0x18EC; +_I2C2CON2bits = 0x18EC; + I2C2LBRG = 0x18F0; +_I2C2LBRG = 0x18F0; +_I2C2LBRGbits = 0x18F0; + I2C2INTC = 0x18F4; +_I2C2INTC = 0x18F4; +_I2C2INTCbits = 0x18F4; + I2C2STAT2 = 0x18F8; +_I2C2STAT2 = 0x18F8; +_I2C2STAT2bits = 0x18F8; + I2C2PEC = 0x18FC; +_I2C2PEC = 0x18FC; +_I2C2PECbits = 0x18FC; + I2C2BTO = 0x1900; +_I2C2BTO = 0x1900; +_I2C2BTObits = 0x1900; + I2C2HBCTO = 0x1904; +_I2C2HBCTO = 0x1904; +_I2C2HBCTObits = 0x1904; + I2C2CBCTO = 0x1908; +_I2C2CBCTO = 0x1908; +_I2C2CBCTObits = 0x1908; + I2C2BITO = 0x190C; +_I2C2BITO = 0x190C; +_I2C2BITObits = 0x190C; + I2C2SDASUT = 0x1910; +_I2C2SDASUT = 0x1910; +_I2C2SDASUTbits = 0x1910; + SENT1CON1 = 0x19C0; +_SENT1CON1 = 0x19C0; +_SENT1CON1bits = 0x19C0; + SENT1CON2 = 0x19C4; +_SENT1CON2 = 0x19C4; +_SENT1CON2bits = 0x19C4; + SENT1CON3 = 0x19C8; +_SENT1CON3 = 0x19C8; +_SENT1CON3bits = 0x19C8; + SENT1STAT = 0x19CC; +_SENT1STAT = 0x19CC; +_SENT1STATbits = 0x19CC; + SENT1SYNC = 0x19D0; +_SENT1SYNC = 0x19D0; +_SENT1SYNCbits = 0x19D0; + SENT1DAT = 0x19D4; +_SENT1DAT = 0x19D4; +_SENT1DATbits = 0x19D4; + SENT2CON1 = 0x19E0; +_SENT2CON1 = 0x19E0; +_SENT2CON1bits = 0x19E0; + SENT2CON2 = 0x19E4; +_SENT2CON2 = 0x19E4; +_SENT2CON2bits = 0x19E4; + SENT2CON3 = 0x19E8; +_SENT2CON3 = 0x19E8; +_SENT2CON3bits = 0x19E8; + SENT2STAT = 0x19EC; +_SENT2STAT = 0x19EC; +_SENT2STATbits = 0x19EC; + SENT2SYNC = 0x19F0; +_SENT2SYNC = 0x19F0; +_SENT2SYNCbits = 0x19F0; + SENT2DAT = 0x19F4; +_SENT2DAT = 0x19F4; +_SENT2DATbits = 0x19F4; + QEI1CON = 0x1A00; +_QEI1CON = 0x1A00; +_QEI1CONbits = 0x1A00; + QEI1IOC = 0x1A04; +_QEI1IOC = 0x1A04; +_QEI1IOCbits = 0x1A04; + QEI1STAT = 0x1A08; +_QEI1STAT = 0x1A08; +_QEI1STATbits = 0x1A08; + POS1CNT = 0x1A0C; +_POS1CNT = 0x1A0C; + POS1HLD = 0x1A10; +_POS1HLD = 0x1A10; + VEL1CNT = 0x1A14; +_VEL1CNT = 0x1A14; + VEL1HLD = 0x1A18; +_VEL1HLD = 0x1A18; + INT1TMR = 0x1A1C; +_INT1TMR = 0x1A1C; + INT1HLD = 0x1A20; +_INT1HLD = 0x1A20; + INDX1CNT = 0x1A24; +_INDX1CNT = 0x1A24; + INDX1HLD = 0x1A28; +_INDX1HLD = 0x1A28; + QEI1GEC = 0x1A2C; +_QEI1GEC = 0x1A2C; + QEI1LEC = 0x1A30; +_QEI1LEC = 0x1A30; + CCP1CON1 = 0x1B00; +_CCP1CON1 = 0x1B00; +_CCP1CON1bits = 0x1B00; + CCP1CON2 = 0x1B04; +_CCP1CON2 = 0x1B04; +_CCP1CON2bits = 0x1B04; + CCP1CON3 = 0x1B08; +_CCP1CON3 = 0x1B08; +_CCP1CON3bits = 0x1B08; + CCP1STAT = 0x1B0C; +_CCP1STAT = 0x1B0C; +_CCP1STATbits = 0x1B0C; + CCP1TMR = 0x1B10; +_CCP1TMR = 0x1B10; +_CCP1TMRbits = 0x1B10; + CCP1PR = 0x1B14; +_CCP1PR = 0x1B14; +_CCP1PRbits = 0x1B14; + CCP1RA = 0x1B18; +_CCP1RA = 0x1B18; +_CCP1RAbits = 0x1B18; + CCP1RB = 0x1B1C; +_CCP1RB = 0x1B1C; +_CCP1RBbits = 0x1B1C; + CCP1BUF = 0x1B20; +_CCP1BUF = 0x1B20; +_CCP1BUFbits = 0x1B20; + CCP2CON1 = 0x1B30; +_CCP2CON1 = 0x1B30; +_CCP2CON1bits = 0x1B30; + CCP2CON2 = 0x1B34; +_CCP2CON2 = 0x1B34; +_CCP2CON2bits = 0x1B34; + CCP2CON3 = 0x1B38; +_CCP2CON3 = 0x1B38; +_CCP2CON3bits = 0x1B38; + CCP2STAT = 0x1B3C; +_CCP2STAT = 0x1B3C; +_CCP2STATbits = 0x1B3C; + CCP2TMR = 0x1B40; +_CCP2TMR = 0x1B40; +_CCP2TMRbits = 0x1B40; + CCP2PR = 0x1B44; +_CCP2PR = 0x1B44; +_CCP2PRbits = 0x1B44; + CCP2RA = 0x1B48; +_CCP2RA = 0x1B48; +_CCP2RAbits = 0x1B48; + CCP2RB = 0x1B4C; +_CCP2RB = 0x1B4C; +_CCP2RBbits = 0x1B4C; + CCP2BUF = 0x1B50; +_CCP2BUF = 0x1B50; +_CCP2BUFbits = 0x1B50; + CCP3CON1 = 0x1B60; +_CCP3CON1 = 0x1B60; +_CCP3CON1bits = 0x1B60; + CCP3CON2 = 0x1B64; +_CCP3CON2 = 0x1B64; +_CCP3CON2bits = 0x1B64; + CCP3CON3 = 0x1B68; +_CCP3CON3 = 0x1B68; +_CCP3CON3bits = 0x1B68; + CCP3STAT = 0x1B6C; +_CCP3STAT = 0x1B6C; +_CCP3STATbits = 0x1B6C; + CCP3TMR = 0x1B70; +_CCP3TMR = 0x1B70; +_CCP3TMRbits = 0x1B70; + CCP3PR = 0x1B74; +_CCP3PR = 0x1B74; +_CCP3PRbits = 0x1B74; + CCP3RA = 0x1B78; +_CCP3RA = 0x1B78; +_CCP3RAbits = 0x1B78; + CCP3RB = 0x1B7C; +_CCP3RB = 0x1B7C; +_CCP3RBbits = 0x1B7C; + CCP3BUF = 0x1B80; +_CCP3BUF = 0x1B80; +_CCP3BUFbits = 0x1B80; + CCP4CON1 = 0x1B90; +_CCP4CON1 = 0x1B90; +_CCP4CON1bits = 0x1B90; + CCP4CON2 = 0x1B94; +_CCP4CON2 = 0x1B94; +_CCP4CON2bits = 0x1B94; + CCP4CON3 = 0x1B98; +_CCP4CON3 = 0x1B98; +_CCP4CON3bits = 0x1B98; + CCP4STAT = 0x1B9C; +_CCP4STAT = 0x1B9C; +_CCP4STATbits = 0x1B9C; + CCP4TMR = 0x1BA0; +_CCP4TMR = 0x1BA0; +_CCP4TMRbits = 0x1BA0; + CCP4PR = 0x1BA4; +_CCP4PR = 0x1BA4; +_CCP4PRbits = 0x1BA4; + CCP4RA = 0x1BA8; +_CCP4RA = 0x1BA8; +_CCP4RAbits = 0x1BA8; + CCP4RB = 0x1BAC; +_CCP4RB = 0x1BAC; +_CCP4RBbits = 0x1BAC; + CCP4BUF = 0x1BB0; +_CCP4BUF = 0x1BB0; +_CCP4BUFbits = 0x1BB0; + DACCTRL1 = 0x1D40; +_DACCTRL1 = 0x1D40; +_DACCTRL1bits = 0x1D40; + DACCTRL2 = 0x1D44; +_DACCTRL2 = 0x1D44; +_DACCTRL2bits = 0x1D44; + DAC1CON = 0x1D48; +_DAC1CON = 0x1D48; +_DAC1CONbits = 0x1D48; + DAC1DAT = 0x1D4C; +_DAC1DAT = 0x1D4C; +_DAC1DATbits = 0x1D4C; + DAC1SLPCON = 0x1D50; +_DAC1SLPCON = 0x1D50; +_DAC1SLPCONbits = 0x1D50; + DAC1SLPDAT = 0x1D54; +_DAC1SLPDAT = 0x1D54; +_DAC1SLPDATbits = 0x1D54; + DAC2CON = 0x1D58; +_DAC2CON = 0x1D58; +_DAC2CONbits = 0x1D58; + DAC2DAT = 0x1D5C; +_DAC2DAT = 0x1D5C; +_DAC2DATbits = 0x1D5C; + DAC2SLPCON = 0x1D60; +_DAC2SLPCON = 0x1D60; +_DAC2SLPCONbits = 0x1D60; + DAC2SLPDAT = 0x1D64; +_DAC2SLPDAT = 0x1D64; +_DAC2SLPDATbits = 0x1D64; + DAC3CON = 0x1D68; +_DAC3CON = 0x1D68; +_DAC3CONbits = 0x1D68; + DAC3DAT = 0x1D6C; +_DAC3DAT = 0x1D6C; +_DAC3DATbits = 0x1D6C; + DAC3SLPCON = 0x1D70; +_DAC3SLPCON = 0x1D70; +_DAC3SLPCONbits = 0x1D70; + DAC3SLPDAT = 0x1D74; +_DAC3SLPDAT = 0x1D74; +_DAC3SLPDATbits = 0x1D74; + T1CON = 0x1E00; +_T1CON = 0x1E00; +_T1CONbits = 0x1E00; + TMR1 = 0x1E04; +_TMR1 = 0x1E04; + PR1 = 0x1E08; +_PR1 = 0x1E08; + HPCCON = 0x1E10; +_HPCCON = 0x1E10; +_HPCCONbits = 0x1E10; + HPSEL0 = 0x1E14; +_HPSEL0 = 0x1E14; +_HPSEL0bits = 0x1E14; + HPSEL1 = 0x1E18; +_HPSEL1 = 0x1E18; +_HPSEL1bits = 0x1E18; + HPCCNTL0 = 0x1E20; +_HPCCNTL0 = 0x1E20; + HPCCNTH0 = 0x1E24; +_HPCCNTH0 = 0x1E24; + HPCCNTL1 = 0x1E28; +_HPCCNTL1 = 0x1E28; + HPCCNTH1 = 0x1E2C; +_HPCCNTH1 = 0x1E2C; + HPCCNTL2 = 0x1E30; +_HPCCNTL2 = 0x1E30; + HPCCNTH2 = 0x1E34; +_HPCCNTH2 = 0x1E34; + HPCCNTL3 = 0x1E38; +_HPCCNTL3 = 0x1E38; + HPCCNTH3 = 0x1E3C; +_HPCCNTH3 = 0x1E3C; + HPCCNTL4 = 0x1E40; +_HPCCNTL4 = 0x1E40; + HPCCNTH4 = 0x1E44; +_HPCCNTH4 = 0x1E44; + HPCCNTL5 = 0x1E48; +_HPCCNTL5 = 0x1E48; + HPCCNTH5 = 0x1E4C; +_HPCCNTH5 = 0x1E4C; + HPCCNTL6 = 0x1E50; +_HPCCNTL6 = 0x1E50; + HPCCNTH6 = 0x1E54; +_HPCCNTH6 = 0x1E54; + HPCCNTL7 = 0x1E58; +_HPCCNTL7 = 0x1E58; + HPCCNTH7 = 0x1E5C; +_HPCCNTH7 = 0x1E5C; + CHECON = 0x1E60; +_CHECON = 0x1E60; +_CHECONbits = 0x1E60; + CHESTAT = 0x1E64; +_CHESTAT = 0x1E64; +_CHESTATbits = 0x1E64; + CHEFLTINJ = 0x1E68; +_CHEFLTINJ = 0x1E68; +_CHEFLTINJbits = 0x1E68; + PACCON1 = 0x1E80; +_PACCON1 = 0x1E80; +_PACCON1bits = 0x1E80; + PACCON2 = 0x1E84; +_PACCON2 = 0x1E84; +_PACCON2bits = 0x1E84; + IOIM1CON = 0x1E90; +_IOIM1CON = 0x1E90; +_IOIM1CONbits = 0x1E90; + IOIM1BCON = 0x1E94; +_IOIM1BCON = 0x1E94; +_IOIM1BCONbits = 0x1E94; + IOIM1STAT = 0x1E98; +_IOIM1STAT = 0x1E98; +_IOIM1STATbits = 0x1E98; + IOIM2CON = 0x1E9C; +_IOIM2CON = 0x1E9C; +_IOIM2CONbits = 0x1E9C; + IOIM2BCON = 0x1EA0; +_IOIM2BCON = 0x1EA0; +_IOIM2BCONbits = 0x1EA0; + IOIM2STAT = 0x1EA4; +_IOIM2STAT = 0x1EA4; +_IOIM2STATbits = 0x1EA4; + IOIM3CON = 0x1EA8; +_IOIM3CON = 0x1EA8; +_IOIM3CONbits = 0x1EA8; + IOIM3BCON = 0x1EAC; +_IOIM3BCON = 0x1EAC; +_IOIM3BCONbits = 0x1EAC; + IOIM3STAT = 0x1EB0; +_IOIM3STAT = 0x1EB0; +_IOIM3STATbits = 0x1EB0; + IOIM4CON = 0x1EB4; +_IOIM4CON = 0x1EB4; +_IOIM4CONbits = 0x1EB4; + IOIM4BCON = 0x1EB8; +_IOIM4BCON = 0x1EB8; +_IOIM4BCONbits = 0x1EB8; + IOIM4STAT = 0x1EBC; +_IOIM4STAT = 0x1EBC; +_IOIM4STATbits = 0x1EBC; + B1SCDATA0L = 0x1F00; +_B1SCDATA0L = 0x1F00; + B1SCDATA0H = 0x1F04; +_B1SCDATA0H = 0x1F04; + B1SCDATA1L = 0x1F08; +_B1SCDATA1L = 0x1F08; + B1SCDATA1H = 0x1F0C; +_B1SCDATA1H = 0x1F0C; + B1SCDATA2L = 0x1F10; +_B1SCDATA2L = 0x1F10; + B1SCDATA2H = 0x1F14; +_B1SCDATA2H = 0x1F14; + B1SCDATA3L = 0x1F18; +_B1SCDATA3L = 0x1F18; + B1SCDATA3H = 0x1F1C; +_B1SCDATA3H = 0x1F1C; + B1IDS0 = 0x1F80; +_B1IDS0 = 0x1F80; +_B1IDS0bits = 0x1F80; + B1RDATA0 = 0x1F80; +_B1RDATA0 = 0x1F80; +_B1RDATA0bits = 0x1F80; + B1IDS1 = 0x1F84; +_B1IDS1 = 0x1F84; +_B1IDS1bits = 0x1F84; + B1RDATA1 = 0x1F84; +_B1RDATA1 = 0x1F84; +_B1RDATA1bits = 0x1F84; + B1IDS2 = 0x1F88; +_B1IDS2 = 0x1F88; +_B1IDS2bits = 0x1F88; + B1RDATA2 = 0x1F88; +_B1RDATA2 = 0x1F88; +_B1RDATA2bits = 0x1F88; + B1IDS3 = 0x1F8C; +_B1IDS3 = 0x1F8C; +_B1IDS3bits = 0x1F8C; + B1RDATA3 = 0x1F8C; +_B1RDATA3 = 0x1F8C; +_B1RDATA3bits = 0x1F8C; + B1IDS4 = 0x1F90; +_B1IDS4 = 0x1F90; +_B1IDS4bits = 0x1F90; + B1RDATA4 = 0x1F90; +_B1RDATA4 = 0x1F90; +_B1RDATA4bits = 0x1F90; + B1IDS5 = 0x1F94; +_B1IDS5 = 0x1F94; +_B1IDS5bits = 0x1F94; + B1RDATA5 = 0x1F94; +_B1RDATA5 = 0x1F94; +_B1RDATA5bits = 0x1F94; + B1IDS6 = 0x1F98; +_B1IDS6 = 0x1F98; +_B1IDS6bits = 0x1F98; + B1RDATA6 = 0x1F98; +_B1RDATA6 = 0x1F98; +_B1RDATA6bits = 0x1F98; + B1IDS7 = 0x1F9C; +_B1IDS7 = 0x1F9C; +_B1IDS7bits = 0x1F9C; + B1RDATA7 = 0x1F9C; +_B1RDATA7 = 0x1F9C; +_B1RDATA7bits = 0x1F9C; + B1CLTCON0 = 0x1FC0; +_B1CLTCON0 = 0x1FC0; +_B1CLTCON0bits = 0x1FC0; + B1CLTCON1 = 0x1FC4; +_B1CLTCON1 = 0x1FC4; +_B1CLTCON1bits = 0x1FC4; + B1CLTCON2 = 0x1FC8; +_B1CLTCON2 = 0x1FC8; +_B1CLTCON2bits = 0x1FC8; + B1CLTCON3 = 0x1FCC; +_B1CLTCON3 = 0x1FCC; +_B1CLTCON3bits = 0x1FCC; + B1RCCON = 0x1FE0; +_B1RCCON = 0x1FE0; +_B1RCCONbits = 0x1FE0; + B1CTRLCON = 0x1FE4; +_B1CTRLCON = 0x1FE4; +_B1CTRLCONbits = 0x1FE4; + B1CCON = 0x1FE8; +_B1CCON = 0x1FE8; +_B1CCONbits = 0x1FE8; + B1CHCON = 0x1FEC; +_B1CHCON = 0x1FEC; +_B1CHCONbits = 0x1FEC; + B1STAT = 0x1FF0; +_B1STAT = 0x1FF0; +_B1STATbits = 0x1FF0; + B1INSTR = 0x1FF4; +_B1INSTR = 0x1FF4; +_B1INSTRbits = 0x1FF4; + B1CHSTAT = 0x1FF8; +_B1CHSTAT = 0x1FF8; +_B1CHSTATbits = 0x1FF8; + B1CON = 0x1FFC; +_B1CON = 0x1FFC; +_B1CONbits = 0x1FFC; + DMACON = 0x2300; +_DMACON = 0x2300; +_DMACONbits = 0x2300; + DMABUF = 0x2304; +_DMABUF = 0x2304; + DMALOW = 0x2308; +_DMALOW = 0x2308; +_DMALOWbits = 0x2308; + DMAHIGH = 0x230C; +_DMAHIGH = 0x230C; +_DMAHIGHbits = 0x230C; + DMA0CH = 0x2310; +_DMA0CH = 0x2310; +_DMA0CHbits = 0x2310; + DMA0SEL = 0x2314; +_DMA0SEL = 0x2314; +_DMA0SELbits = 0x2314; + DMA0STAT = 0x2318; +_DMA0STAT = 0x2318; +_DMA0STATbits = 0x2318; + DMA0SRC = 0x231C; +_DMA0SRC = 0x231C; +_DMA0SRCbits = 0x231C; + DMA0DST = 0x2320; +_DMA0DST = 0x2320; +_DMA0DSTbits = 0x2320; + DMA0CNT = 0x2324; +_DMA0CNT = 0x2324; +_DMA0CNTbits = 0x2324; + DMA0CLR = 0x2328; +_DMA0CLR = 0x2328; + DMA0SET = 0x232C; +_DMA0SET = 0x232C; + DMA0INV = 0x2330; +_DMA0INV = 0x2330; + DMA0MSK = 0x2334; +_DMA0MSK = 0x2334; + DMA0PAT = 0x2338; +_DMA0PAT = 0x2338; + DMA1CH = 0x233C; +_DMA1CH = 0x233C; +_DMA1CHbits = 0x233C; + DMA1SEL = 0x2340; +_DMA1SEL = 0x2340; +_DMA1SELbits = 0x2340; + DMA1STAT = 0x2344; +_DMA1STAT = 0x2344; +_DMA1STATbits = 0x2344; + DMA1SRC = 0x2348; +_DMA1SRC = 0x2348; +_DMA1SRCbits = 0x2348; + DMA1DST = 0x234C; +_DMA1DST = 0x234C; +_DMA1DSTbits = 0x234C; + DMA1CNT = 0x2350; +_DMA1CNT = 0x2350; +_DMA1CNTbits = 0x2350; + DMA1CLR = 0x2354; +_DMA1CLR = 0x2354; + DMA1SET = 0x2358; +_DMA1SET = 0x2358; + DMA1INV = 0x235C; +_DMA1INV = 0x235C; + DMA1MSK = 0x2360; +_DMA1MSK = 0x2360; + DMA1PAT = 0x2364; +_DMA1PAT = 0x2364; + DMA2CH = 0x2368; +_DMA2CH = 0x2368; +_DMA2CHbits = 0x2368; + DMA2SEL = 0x236C; +_DMA2SEL = 0x236C; +_DMA2SELbits = 0x236C; + DMA2STAT = 0x2370; +_DMA2STAT = 0x2370; +_DMA2STATbits = 0x2370; + DMA2SRC = 0x2374; +_DMA2SRC = 0x2374; +_DMA2SRCbits = 0x2374; + DMA2DST = 0x2378; +_DMA2DST = 0x2378; +_DMA2DSTbits = 0x2378; + DMA2CNT = 0x237C; +_DMA2CNT = 0x237C; +_DMA2CNTbits = 0x237C; + DMA2CLR = 0x2380; +_DMA2CLR = 0x2380; + DMA2SET = 0x2384; +_DMA2SET = 0x2384; + DMA2INV = 0x2388; +_DMA2INV = 0x2388; + DMA2MSK = 0x238C; +_DMA2MSK = 0x238C; + DMA2PAT = 0x2390; +_DMA2PAT = 0x2390; + DMA3CH = 0x2394; +_DMA3CH = 0x2394; +_DMA3CHbits = 0x2394; + DMA3SEL = 0x2398; +_DMA3SEL = 0x2398; +_DMA3SELbits = 0x2398; + DMA3STAT = 0x239C; +_DMA3STAT = 0x239C; +_DMA3STATbits = 0x239C; + DMA3SRC = 0x23A0; +_DMA3SRC = 0x23A0; +_DMA3SRCbits = 0x23A0; + DMA3DST = 0x23A4; +_DMA3DST = 0x23A4; +_DMA3DSTbits = 0x23A4; + DMA3CNT = 0x23A8; +_DMA3CNT = 0x23A8; +_DMA3CNTbits = 0x23A8; + DMA3CLR = 0x23AC; +_DMA3CLR = 0x23AC; + DMA3SET = 0x23B0; +_DMA3SET = 0x23B0; + DMA3INV = 0x23B4; +_DMA3INV = 0x23B4; + DMA3MSK = 0x23B8; +_DMA3MSK = 0x23B8; + DMA3PAT = 0x23BC; +_DMA3PAT = 0x23BC; + DMA4CH = 0x23C0; +_DMA4CH = 0x23C0; +_DMA4CHbits = 0x23C0; + DMA4SEL = 0x23C4; +_DMA4SEL = 0x23C4; +_DMA4SELbits = 0x23C4; + DMA4STAT = 0x23C8; +_DMA4STAT = 0x23C8; +_DMA4STATbits = 0x23C8; + DMA4SRC = 0x23CC; +_DMA4SRC = 0x23CC; +_DMA4SRCbits = 0x23CC; + DMA4DST = 0x23D0; +_DMA4DST = 0x23D0; +_DMA4DSTbits = 0x23D0; + DMA4CNT = 0x23D4; +_DMA4CNT = 0x23D4; +_DMA4CNTbits = 0x23D4; + DMA4CLR = 0x23D8; +_DMA4CLR = 0x23D8; + DMA4SET = 0x23DC; +_DMA4SET = 0x23DC; + DMA4INV = 0x23E0; +_DMA4INV = 0x23E0; + DMA4MSK = 0x23E4; +_DMA4MSK = 0x23E4; + DMA4PAT = 0x23E8; +_DMA4PAT = 0x23E8; + DMA5CH = 0x23EC; +_DMA5CH = 0x23EC; +_DMA5CHbits = 0x23EC; + DMA5SEL = 0x23F0; +_DMA5SEL = 0x23F0; +_DMA5SELbits = 0x23F0; + DMA5STAT = 0x23F4; +_DMA5STAT = 0x23F4; +_DMA5STATbits = 0x23F4; + DMA5SRC = 0x23F8; +_DMA5SRC = 0x23F8; +_DMA5SRCbits = 0x23F8; + DMA5DST = 0x23FC; +_DMA5DST = 0x23FC; +_DMA5DSTbits = 0x23FC; + DMA5CNT = 0x2400; +_DMA5CNT = 0x2400; +_DMA5CNTbits = 0x2400; + DMA5CLR = 0x2404; +_DMA5CLR = 0x2404; + DMA5SET = 0x2408; +_DMA5SET = 0x2408; + DMA5INV = 0x240C; +_DMA5INV = 0x240C; + DMA5MSK = 0x2410; +_DMA5MSK = 0x2410; + DMA5PAT = 0x2414; +_DMA5PAT = 0x2414; + NVMCON = 0x3000; +_NVMCON = 0x3000; +_NVMCONbits = 0x3000; + NVMADR = 0x3004; +_NVMADR = 0x3004; +_NVMADRbits = 0x3004; + NVMDATA0 = 0x3008; +_NVMDATA0 = 0x3008; + NVMDATA1 = 0x300C; +_NVMDATA1 = 0x300C; + NVMDATA2 = 0x3010; +_NVMDATA2 = 0x3010; + NVMDATA3 = 0x3014; +_NVMDATA3 = 0x3014; + NVMSRCADR = 0x3018; +_NVMSRCADR = 0x3018; +_NVMSRCADRbits = 0x3018; + NVMECCCON = 0x301C; +_NVMECCCON = 0x301C; +_NVMECCCONbits = 0x301C; + NVMECCSTAT = 0x3020; +_NVMECCSTAT = 0x3020; +_NVMECCSTATbits = 0x3020; + NVMECCFPTR = 0x3024; +_NVMECCFPTR = 0x3024; +_NVMECCFPTRbits = 0x3024; + NVMECCFADDR = 0x3028; +_NVMECCFADDR = 0x3028; +_NVMECCFADDRbits = 0x3028; + NVMECCEADDR = 0x302C; +_NVMECCEADDR = 0x302C; +_NVMECCEADDRbits = 0x302C; + NVMECCEDATA0 = 0x3030; +_NVMECCEDATA0 = 0x3030; + NVMECCEDATA1 = 0x3034; +_NVMECCEDATA1 = 0x3034; + NVMECCEDATA2 = 0x3038; +_NVMECCEDATA2 = 0x3038; + NVMECCEDATA3 = 0x303C; +_NVMECCEDATA3 = 0x303C; + NVMECCVAL = 0x3040; +_NVMECCVAL = 0x3040; +_NVMECCVALbits = 0x3040; + NVMECCSYND = 0x3044; +_NVMECCSYND = 0x3044; +_NVMECCSYNDbits = 0x3044; + NVMCRCCON = 0x3048; +_NVMCRCCON = 0x3048; +_NVMCRCCONbits = 0x3048; + NVMCRCST = 0x304C; +_NVMCRCST = 0x304C; +_NVMCRCSTbits = 0x304C; + NVMCRCEND = 0x3050; +_NVMCRCEND = 0x3050; +_NVMCRCENDbits = 0x3050; + NVMCRCSEED = 0x3054; +_NVMCRCSEED = 0x3054; + NVMCRCDATA = 0x3058; +_NVMCRCDATA = 0x3058; + OSCCTRL = 0x3100; +_OSCCTRL = 0x3100; +_OSCCTRLbits = 0x3100; + OSCCFG = 0x3104; +_OSCCFG = 0x3104; +_OSCCFGbits = 0x3104; + CLKFAIL = 0x3108; +_CLKFAIL = 0x3108; +_CLKFAILbits = 0x3108; + SCSFAIL = 0x310C; +_SCSFAIL = 0x310C; +_SCSFAILbits = 0x310C; + CLK1CON = 0x3118; +_CLK1CON = 0x3118; +_CLK1CONbits = 0x3118; + CLK1DIV = 0x311C; +_CLK1DIV = 0x311C; +_CLK1DIVbits = 0x311C; + CLK2CON = 0x3120; +_CLK2CON = 0x3120; +_CLK2CONbits = 0x3120; + CLK2DIV = 0x3124; +_CLK2DIV = 0x3124; +_CLK2DIVbits = 0x3124; + CLK3CON = 0x3128; +_CLK3CON = 0x3128; +_CLK3CONbits = 0x3128; + CLK3DIV = 0x312C; +_CLK3DIV = 0x312C; +_CLK3DIVbits = 0x312C; + CLK4CON = 0x3130; +_CLK4CON = 0x3130; +_CLK4CONbits = 0x3130; + CLK4DIV = 0x3134; +_CLK4DIV = 0x3134; +_CLK4DIVbits = 0x3134; + CLK5CON = 0x3138; +_CLK5CON = 0x3138; +_CLK5CONbits = 0x3138; + CLK5DIV = 0x313C; +_CLK5DIV = 0x313C; +_CLK5DIVbits = 0x313C; + CLK6CON = 0x3140; +_CLK6CON = 0x3140; +_CLK6CONbits = 0x3140; + CLK6DIV = 0x3144; +_CLK6DIV = 0x3144; +_CLK6DIVbits = 0x3144; + CLK7CON = 0x3148; +_CLK7CON = 0x3148; +_CLK7CONbits = 0x3148; + CLK7DIV = 0x314C; +_CLK7DIV = 0x314C; +_CLK7DIVbits = 0x314C; + CLK8CON = 0x3150; +_CLK8CON = 0x3150; +_CLK8CONbits = 0x3150; + CLK8DIV = 0x3154; +_CLK8DIV = 0x3154; +_CLK8DIVbits = 0x3154; + CLK9CON = 0x3158; +_CLK9CON = 0x3158; +_CLK9CONbits = 0x3158; + CLK9DIV = 0x315C; +_CLK9DIV = 0x315C; +_CLK9DIVbits = 0x315C; + CLK10CON = 0x3160; +_CLK10CON = 0x3160; +_CLK10CONbits = 0x3160; + CLK10DIV = 0x3164; +_CLK10DIV = 0x3164; +_CLK10DIVbits = 0x3164; + CLK11CON = 0x3168; +_CLK11CON = 0x3168; +_CLK11CONbits = 0x3168; + CLK11DIV = 0x316C; +_CLK11DIV = 0x316C; +_CLK11DIVbits = 0x316C; + CLK12CON = 0x3170; +_CLK12CON = 0x3170; +_CLK12CONbits = 0x3170; + CLK12DIV = 0x3174; +_CLK12DIV = 0x3174; +_CLK12DIVbits = 0x3174; + CLK13CON = 0x3178; +_CLK13CON = 0x3178; +_CLK13CONbits = 0x3178; + CLK13DIV = 0x317C; +_CLK13DIV = 0x317C; +_CLK13DIVbits = 0x317C; + PLL1CON = 0x3180; +_PLL1CON = 0x3180; +_PLL1CONbits = 0x3180; + PLL1DIV = 0x3184; +_PLL1DIV = 0x3184; +_PLL1DIVbits = 0x3184; + VCO1DIV = 0x3188; +_VCO1DIV = 0x3188; +_VCO1DIVbits = 0x3188; + PLL2CON = 0x318C; +_PLL2CON = 0x318C; +_PLL2CONbits = 0x318C; + PLL2DIV = 0x3190; +_PLL2DIV = 0x3190; +_PLL2DIVbits = 0x3190; + VCO2DIV = 0x3194; +_VCO2DIV = 0x3194; +_VCO2DIVbits = 0x3194; + RCON = 0x3198; +_RCON = 0x3198; +_RCONbits = 0x3198; + CLKDIAG = 0x319C; +_CLKDIAG = 0x319C; +_CLKDIAGbits = 0x319C; + CM1CON = 0x3200; +_CM1CON = 0x3200; +_CM1CONbits = 0x3200; + CM1STAT = 0x3204; +_CM1STAT = 0x3204; +_CM1STATbits = 0x3204; + CM1WINPR = 0x3208; +_CM1WINPR = 0x3208; + CM1SEL = 0x320C; +_CM1SEL = 0x320C; +_CM1SELbits = 0x320C; + CM1BUF = 0x3210; +_CM1BUF = 0x3210; + CM1SAT = 0x3214; +_CM1SAT = 0x3214; + CM1HFAIL = 0x3218; +_CM1HFAIL = 0x3218; + CM1LFAIL = 0x321C; +_CM1LFAIL = 0x321C; + CM1HWARN = 0x3220; +_CM1HWARN = 0x3220; + CM1LWARN = 0x3224; +_CM1LWARN = 0x3224; + CM2CON = 0x3230; +_CM2CON = 0x3230; +_CM2CONbits = 0x3230; + CM2STAT = 0x3234; +_CM2STAT = 0x3234; +_CM2STATbits = 0x3234; + CM2WINPR = 0x3238; +_CM2WINPR = 0x3238; + CM2SEL = 0x323C; +_CM2SEL = 0x323C; +_CM2SELbits = 0x323C; + CM2BUF = 0x3240; +_CM2BUF = 0x3240; + CM2SAT = 0x3244; +_CM2SAT = 0x3244; + CM2HFAIL = 0x3248; +_CM2HFAIL = 0x3248; + CM2LFAIL = 0x324C; +_CM2LFAIL = 0x324C; + CM2HWARN = 0x3250; +_CM2HWARN = 0x3250; + CM2LWARN = 0x3254; +_CM2LWARN = 0x3254; + CM3CON = 0x3260; +_CM3CON = 0x3260; +_CM3CONbits = 0x3260; + CM3STAT = 0x3264; +_CM3STAT = 0x3264; +_CM3STATbits = 0x3264; + CM3WINPR = 0x3268; +_CM3WINPR = 0x3268; + CM3SEL = 0x326C; +_CM3SEL = 0x326C; +_CM3SELbits = 0x326C; + CM3BUF = 0x3270; +_CM3BUF = 0x3270; + CM3SAT = 0x3274; +_CM3SAT = 0x3274; + CM3HFAIL = 0x3278; +_CM3HFAIL = 0x3278; + CM3LFAIL = 0x327C; +_CM3LFAIL = 0x327C; + CM3HWARN = 0x3280; +_CM3HWARN = 0x3280; + CM3LWARN = 0x3284; +_CM3LWARN = 0x3284; + CM4CON = 0x3290; +_CM4CON = 0x3290; +_CM4CONbits = 0x3290; + CM4STAT = 0x3294; +_CM4STAT = 0x3294; +_CM4STATbits = 0x3294; + CM4WINPR = 0x3298; +_CM4WINPR = 0x3298; + CM4SEL = 0x329C; +_CM4SEL = 0x329C; +_CM4SELbits = 0x329C; + CM4BUF = 0x32A0; +_CM4BUF = 0x32A0; + CM4SAT = 0x32A4; +_CM4SAT = 0x32A4; + CM4HFAIL = 0x32A8; +_CM4HFAIL = 0x32A8; + CM4LFAIL = 0x32AC; +_CM4LFAIL = 0x32AC; + CM4HWARN = 0x32B0; +_CM4HWARN = 0x32B0; + CM4LWARN = 0x32B4; +_CM4LWARN = 0x32B4; + FRCTUN = 0x32C0; +_FRCTUN = 0x32C0; +_FRCTUNbits = 0x32C0; + BFRCTUN = 0x32C4; +_BFRCTUN = 0x32C4; +_BFRCTUNbits = 0x32C4; + WDTCON = 0x32C8; +_WDTCON = 0x32C8; +_WDTCONbits = 0x32C8; + PTGCON = 0x3500; +_PTGCON = 0x3500; +_PTGCONbits = 0x3500; + PTGBTE = 0x3504; +_PTGBTE = 0x3504; + PTGHOLD = 0x3508; +_PTGHOLD = 0x3508; +_PTGHOLDbits = 0x3508; + PTGT0LIM = 0x350C; +_PTGT0LIM = 0x350C; +_PTGT0LIMbits = 0x350C; + PTGT1LIM = 0x3510; +_PTGT1LIM = 0x3510; +_PTGT1LIMbits = 0x3510; + PTGSDLIM = 0x3514; +_PTGSDLIM = 0x3514; +_PTGSDLIMbits = 0x3514; + PTGC0LIM = 0x3518; +_PTGC0LIM = 0x3518; +_PTGC0LIMbits = 0x3518; + PTGC1LIM = 0x351C; +_PTGC1LIM = 0x351C; +_PTGC1LIMbits = 0x351C; + PTGADJ = 0x3520; +_PTGADJ = 0x3520; +_PTGADJbits = 0x3520; + PTGL0 = 0x3524; +_PTGL0 = 0x3524; +_PTGL0bits = 0x3524; + PTGQPTR = 0x3528; +_PTGQPTR = 0x3528; +_PTGQPTRbits = 0x3528; + PTGQUE0 = 0x3530; +_PTGQUE0 = 0x3530; +_PTGQUE0bits = 0x3530; + PTGQUE1 = 0x3534; +_PTGQUE1 = 0x3534; +_PTGQUE1bits = 0x3534; + PTGQUE2 = 0x3538; +_PTGQUE2 = 0x3538; +_PTGQUE2bits = 0x3538; + PTGQUE3 = 0x353C; +_PTGQUE3 = 0x353C; +_PTGQUE3bits = 0x353C; + PTGQUE4 = 0x3540; +_PTGQUE4 = 0x3540; +_PTGQUE4bits = 0x3540; + PTGQUE5 = 0x3544; +_PTGQUE5 = 0x3544; +_PTGQUE5bits = 0x3544; + PTGQUE6 = 0x3548; +_PTGQUE6 = 0x3548; +_PTGQUE6bits = 0x3548; + PTGQUE7 = 0x354C; +_PTGQUE7 = 0x354C; +_PTGQUE7bits = 0x354C; + RAMXECCCON = 0x3580; +_RAMXECCCON = 0x3580; +_RAMXECCCONbits = 0x3580; + RAMXECCSTAT = 0x3584; +_RAMXECCSTAT = 0x3584; +_RAMXECCSTATbits = 0x3584; + RAMXECCFPTR = 0x3588; +_RAMXECCFPTR = 0x3588; +_RAMXECCFPTRbits = 0x3588; + RAMXECCFADDR = 0x358C; +_RAMXECCFADDR = 0x358C; + RAMXECCEADDR = 0x3590; +_RAMXECCEADDR = 0x3590; + RAMXECCEDATA = 0x3594; +_RAMXECCEDATA = 0x3594; + RAMXECCVAL = 0x3598; +_RAMXECCVAL = 0x3598; +_RAMXECCVALbits = 0x3598; + RAMXECCSYND = 0x359C; +_RAMXECCSYND = 0x359C; +_RAMXECCSYNDbits = 0x359C; + PWBXECCCON = 0x35A0; +_PWBXECCCON = 0x35A0; +_PWBXECCCONbits = 0x35A0; + PWBXECCSTAT = 0x35A4; +_PWBXECCSTAT = 0x35A4; +_PWBXECCSTATbits = 0x35A4; + PWBXECCFPTR = 0x35A8; +_PWBXECCFPTR = 0x35A8; +_PWBXECCFPTRbits = 0x35A8; + PWBXECCFADDR = 0x35AC; +_PWBXECCFADDR = 0x35AC; + PWBXECCEADDR = 0x35B0; +_PWBXECCEADDR = 0x35B0; + PWBXECCEDATA = 0x35B4; +_PWBXECCEDATA = 0x35B4; + PWBXECCVAL = 0x35B8; +_PWBXECCVAL = 0x35B8; +_PWBXECCVALbits = 0x35B8; + PWBXECCSYND = 0x35BC; +_PWBXECCSYND = 0x35BC; +_PWBXECCSYNDbits = 0x35BC; + RAMYECCCON = 0x35C0; +_RAMYECCCON = 0x35C0; +_RAMYECCCONbits = 0x35C0; + RAMYECCSTAT = 0x35C4; +_RAMYECCSTAT = 0x35C4; +_RAMYECCSTATbits = 0x35C4; + RAMYECCFPTR = 0x35C8; +_RAMYECCFPTR = 0x35C8; +_RAMYECCFPTRbits = 0x35C8; + RAMYECCFADDR = 0x35CC; +_RAMYECCFADDR = 0x35CC; + RAMYECCEADDR = 0x35D0; +_RAMYECCEADDR = 0x35D0; + RAMYECCEDATA = 0x35D4; +_RAMYECCEDATA = 0x35D4; + RAMYECCVAL = 0x35D8; +_RAMYECCVAL = 0x35D8; +_RAMYECCVALbits = 0x35D8; + RAMYECCSYND = 0x35DC; +_RAMYECCSYND = 0x35DC; +_RAMYECCSYNDbits = 0x35DC; + PWBYECCCON = 0x35E0; +_PWBYECCCON = 0x35E0; +_PWBYECCCONbits = 0x35E0; + PWBYECCSTAT = 0x35E4; +_PWBYECCSTAT = 0x35E4; +_PWBYECCSTATbits = 0x35E4; + PWBYECCFPTR = 0x35E8; +_PWBYECCFPTR = 0x35E8; +_PWBYECCFPTRbits = 0x35E8; + PWBYECCFADDR = 0x35EC; +_PWBYECCFADDR = 0x35EC; + PWBYECCEADDR = 0x35F0; +_PWBYECCEADDR = 0x35F0; + PWBYECCEDATA = 0x35F4; +_PWBYECCEDATA = 0x35F4; + PWBYECCVAL = 0x35F8; +_PWBYECCVAL = 0x35F8; +_PWBYECCVALbits = 0x35F8; + PWBYECCSYND = 0x35FC; +_PWBYECCSYND = 0x35FC; +_PWBYECCSYNDbits = 0x35FC; + ANSELA = 0x3640; +_ANSELA = 0x3640; +_ANSELAbits = 0x3640; + ODCA = 0x3644; +_ODCA = 0x3644; +_ODCAbits = 0x3644; + CNPUA = 0x3648; +_CNPUA = 0x3648; +_CNPUAbits = 0x3648; + CNPDA = 0x364C; +_CNPDA = 0x364C; +_CNPDAbits = 0x364C; + CNCONA = 0x3650; +_CNCONA = 0x3650; +_CNCONAbits = 0x3650; + CNEN0A = 0x3654; +_CNEN0A = 0x3654; +_CNEN0Abits = 0x3654; + CNEN1A = 0x3658; +_CNEN1A = 0x3658; +_CNEN1Abits = 0x3658; + ANSELB = 0x3664; +_ANSELB = 0x3664; +_ANSELBbits = 0x3664; + ODCB = 0x3668; +_ODCB = 0x3668; +_ODCBbits = 0x3668; + CNPUB = 0x366C; +_CNPUB = 0x366C; +_CNPUBbits = 0x366C; + CNPDB = 0x3670; +_CNPDB = 0x3670; +_CNPDBbits = 0x3670; + CNCONB = 0x3674; +_CNCONB = 0x3674; +_CNCONBbits = 0x3674; + CNEN0B = 0x3678; +_CNEN0B = 0x3678; +_CNEN0Bbits = 0x3678; + CNEN1B = 0x367C; +_CNEN1B = 0x367C; +_CNEN1Bbits = 0x367C; + ANSELC = 0x3688; +_ANSELC = 0x3688; + ODCC = 0x368C; +_ODCC = 0x368C; +_ODCCbits = 0x368C; + CNPUC = 0x3690; +_CNPUC = 0x3690; +_CNPUCbits = 0x3690; + CNPDC = 0x3694; +_CNPDC = 0x3694; +_CNPDCbits = 0x3694; + CNCONC = 0x3698; +_CNCONC = 0x3698; +_CNCONCbits = 0x3698; + CNEN0C = 0x369C; +_CNEN0C = 0x369C; +_CNEN0Cbits = 0x369C; + CNEN1C = 0x36A0; +_CNEN1C = 0x36A0; +_CNEN1Cbits = 0x36A0; + ANSELD = 0x36AC; +_ANSELD = 0x36AC; + ODCD = 0x36B0; +_ODCD = 0x36B0; +_ODCDbits = 0x36B0; + CNPUD = 0x36B4; +_CNPUD = 0x36B4; +_CNPUDbits = 0x36B4; + CNPDD = 0x36B8; +_CNPDD = 0x36B8; +_CNPDDbits = 0x36B8; + CNCOND = 0x36BC; +_CNCOND = 0x36BC; +_CNCONDbits = 0x36BC; + CNEN0D = 0x36C0; +_CNEN0D = 0x36C0; +_CNEN0Dbits = 0x36C0; + CNEN1D = 0x36C4; +_CNEN1D = 0x36C4; +_CNEN1Dbits = 0x36C4; + RPCON = 0x3900; +_RPCON = 0x3900; +_RPCONbits = 0x3900; + RPINR0 = 0x3904; +_RPINR0 = 0x3904; +_RPINR0bits = 0x3904; + RPINR1 = 0x3908; +_RPINR1 = 0x3908; +_RPINR1bits = 0x3908; + RPINR2 = 0x390C; +_RPINR2 = 0x390C; +_RPINR2bits = 0x390C; + RPINR5 = 0x3918; +_RPINR5 = 0x3918; +_RPINR5bits = 0x3918; + RPINR6 = 0x391C; +_RPINR6 = 0x391C; +_RPINR6bits = 0x391C; + RPINR7 = 0x3920; +_RPINR7 = 0x3920; +_RPINR7bits = 0x3920; + RPINR9 = 0x3928; +_RPINR9 = 0x3928; +_RPINR9bits = 0x3928; + RPINR10 = 0x392C; +_RPINR10 = 0x392C; +_RPINR10bits = 0x392C; + RPINR11 = 0x3930; +_RPINR11 = 0x3930; +_RPINR11bits = 0x3930; + RPINR13 = 0x3938; +_RPINR13 = 0x3938; +_RPINR13bits = 0x3938; + RPINR14 = 0x393C; +_RPINR14 = 0x393C; +_RPINR14bits = 0x393C; + RPINR15 = 0x3940; +_RPINR15 = 0x3940; +_RPINR15bits = 0x3940; + RPINR17 = 0x3948; +_RPINR17 = 0x3948; +_RPINR17bits = 0x3948; + RPINR18 = 0x394C; +_RPINR18 = 0x394C; +_RPINR18bits = 0x394C; + RPINR19 = 0x3950; +_RPINR19 = 0x3950; +_RPINR19bits = 0x3950; + RPINR20 = 0x3954; +_RPINR20 = 0x3954; +_RPINR20bits = 0x3954; + RPINR21 = 0x3958; +_RPINR21 = 0x3958; +_RPINR21bits = 0x3958; + RPOR0 = 0x3980; +_RPOR0 = 0x3980; +_RPOR0bits = 0x3980; + RPOR1 = 0x3984; +_RPOR1 = 0x3984; +_RPOR1bits = 0x3984; + RPOR2 = 0x3988; +_RPOR2 = 0x3988; +_RPOR2bits = 0x3988; + RPOR4 = 0x3990; +_RPOR4 = 0x3990; +_RPOR4bits = 0x3990; + RPOR5 = 0x3994; +_RPOR5 = 0x3994; +_RPOR5bits = 0x3994; + RPOR6 = 0x3998; +_RPOR6 = 0x3998; +_RPOR6bits = 0x3998; + RPOR8 = 0x39A0; +_RPOR8 = 0x39A0; +_RPOR8bits = 0x39A0; + RPOR9 = 0x39A4; +_RPOR9 = 0x39A4; +_RPOR9bits = 0x39A4; + RPOR10 = 0x39A8; +_RPOR10 = 0x39A8; +_RPOR10bits = 0x39A8; + RPOR12 = 0x39B0; +_RPOR12 = 0x39B0; +_RPOR12bits = 0x39B0; + RPOR13 = 0x39B4; +_RPOR13 = 0x39B4; +_RPOR13bits = 0x39B4; + RPOR14 = 0x39B8; +_RPOR14 = 0x39B8; +_RPOR14bits = 0x39B8; + RPOR15 = 0x39BC; +_RPOR15 = 0x39BC; +_RPOR15bits = 0x39BC; + RPOR16 = 0x39C0; +_RPOR16 = 0x39C0; +_RPOR16bits = 0x39C0; + RPOR17 = 0x39C4; +_RPOR17 = 0x39C4; +_RPOR17bits = 0x39C4; + RPOR18 = 0x39C8; +_RPOR18 = 0x39C8; +_RPOR18bits = 0x39C8; + RPOR19 = 0x39CC; +_RPOR19 = 0x39CC; +_RPOR19bits = 0x39CC; + DMTCON = 0x3A00; +_DMTCON = 0x3A00; +_DMTCONbits = 0x3A00; + DMTPRECLR = 0x3A04; +_DMTPRECLR = 0x3A04; +_DMTPRECLRbits = 0x3A04; + DMTCLR = 0x3A08; +_DMTCLR = 0x3A08; +_DMTCLRbits = 0x3A08; + DMTSTAT = 0x3A0C; +_DMTSTAT = 0x3A0C; +_DMTSTATbits = 0x3A0C; + DMTCNT = 0x3A10; +_DMTCNT = 0x3A10; + PSCNT = 0x3A14; +_PSCNT = 0x3A14; + PSINTV = 0x3A18; +_PSINTV = 0x3A18; + PPPC = 0x3A1C; +_PPPC = 0x3A1C; +_PPPCbits = 0x3A1C; + PPC = 0x3A20; +_PPC = 0x3A20; +_PPCbits = 0x3A20; + PMD1 = 0x3A44; +_PMD1 = 0x3A44; +_PMD1bits = 0x3A44; + PMD2 = 0x3A48; +_PMD2 = 0x3A48; +_PMD2bits = 0x3A48; + PMD3 = 0x3A4C; +_PMD3 = 0x3A4C; +_PMD3bits = 0x3A4C; + PMD4 = 0x3A50; +_PMD4 = 0x3A50; +_PMD4bits = 0x3A50; + CLC1CON = 0x3A60; +_CLC1CON = 0x3A60; +_CLC1CONbits = 0x3A60; + CLC1SEL = 0x3A64; +_CLC1SEL = 0x3A64; +_CLC1SELbits = 0x3A64; + CLC1GLS = 0x3A68; +_CLC1GLS = 0x3A68; +_CLC1GLSbits = 0x3A68; + CLC2CON = 0x3A70; +_CLC2CON = 0x3A70; +_CLC2CONbits = 0x3A70; + CLC2SEL = 0x3A74; +_CLC2SEL = 0x3A74; +_CLC2SELbits = 0x3A74; + CLC2GLS = 0x3A78; +_CLC2GLS = 0x3A78; +_CLC2GLSbits = 0x3A78; + CLC3CON = 0x3A80; +_CLC3CON = 0x3A80; +_CLC3CONbits = 0x3A80; + CLC3SEL = 0x3A84; +_CLC3SEL = 0x3A84; +_CLC3SELbits = 0x3A84; + CLC3GLS = 0x3A88; +_CLC3GLS = 0x3A88; +_CLC3GLSbits = 0x3A88; + CLC4CON = 0x3A90; +_CLC4CON = 0x3A90; +_CLC4CONbits = 0x3A90; + CLC4SEL = 0x3A94; +_CLC4SEL = 0x3A94; +_CLC4SELbits = 0x3A94; + CLC4GLS = 0x3A98; +_CLC4GLS = 0x3A98; +_CLC4GLSbits = 0x3A98; + MBISTCON = 0x3AA0; +_MBISTCON = 0x3AA0; +_MBISTCONbits = 0x3AA0; + IBIASCON = 0x3AA4; +_IBIASCON = 0x3AA4; +_IBIASCONbits = 0x3AA4; + AMP1CON1 = 0x3AB0; +_AMP1CON1 = 0x3AB0; +_AMP1CON1bits = 0x3AB0; + AMP1CON2 = 0x3AB4; +_AMP1CON2 = 0x3AB4; +_AMP1CON2bits = 0x3AB4; + AMP2CON1 = 0x3AB8; +_AMP2CON1 = 0x3AB8; +_AMP2CON1bits = 0x3AB8; + AMP2CON2 = 0x3ABC; +_AMP2CON2 = 0x3ABC; +_AMP2CON2bits = 0x3ABC; + AMP3CON1 = 0x3AC0; +_AMP3CON1 = 0x3AC0; +_AMP3CON1bits = 0x3AC0; + AMP3CON2 = 0x3AC4; +_AMP3CON2 = 0x3AC4; +_AMP3CON2bits = 0x3AC4; +/* +** ======= Base Addresses for Various Peripherals and ACC ====== +*/ + + SPI1 = 0x1808; +_SPI1 = 0x1808; + SPI2 = 0x1828; +_SPI2 = 0x1828; + SPI3 = 0x1848; +_SPI3 = 0x1848; \ No newline at end of file diff --git a/soc/microchip/dspic33/dspic33a/p33ak512mps512_regs.ld b/soc/microchip/dspic33/dspic33a/p33ak512mps512_regs.ld new file mode 100644 index 0000000000000..06bea285bea44 --- /dev/null +++ b/soc/microchip/dspic33/dspic33a/p33ak512mps512_regs.ld @@ -0,0 +1,5682 @@ +/* +** ============== Equates for SFR Addresses ============= +*/ +PC = 0x0; +_PC = 0x0; +_PCbits = 0x0; + SPLIM = 0x4; +_SPLIM = 0x4; +_SPLIMbits = 0x4; + RCOUNT = 0x8; +_RCOUNT = 0x8; + DISIIPL = 0xC; +_DISIIPL = 0xC; +_DISIIPLbits = 0xC; + CORCON = 0x10; +_CORCON = 0x10; +_CORCONbits = 0x10; + MODCON = 0x14; +_MODCON = 0x14; +_MODCONbits = 0x14; + XMODSRT = 0x18; +_XMODSRT = 0x18; +_XMODSRTbits = 0x18; + XMODEND = 0x1C; +_XMODEND = 0x1C; +_XMODENDbits = 0x1C; + YMODSRT = 0x20; +_YMODSRT = 0x20; +_YMODSRTbits = 0x20; + YMODEND = 0x24; +_YMODEND = 0x24; +_YMODENDbits = 0x24; + XBREV = 0x28; +_XBREV = 0x28; +_XBREVbits = 0x28; + PCTRAP = 0x2C; +_PCTRAP = 0x2C; +_PCTRAPbits = 0x2C; + FEX = 0x30; +_FEX = 0x30; + FEX2 = 0x34; +_FEX2 = 0x34; + PCHOLD = 0x38; +_PCHOLD = 0x38; +_PCHOLDbits = 0x38; + VFA = 0x3C; +_VFA = 0x3C; +_VFAbits = 0x3C; + INTCON1 = 0x70; +_INTCON1 = 0x70; +_INTCON1bits = 0x70; + INTCON2 = 0x74; +_INTCON2 = 0x74; +_INTCON2bits = 0x74; + INTCON3 = 0x78; +_INTCON3 = 0x78; +_INTCON3bits = 0x78; + INTCON4 = 0x7C; +_INTCON4 = 0x7C; +_INTCON4bits = 0x7C; + INTCON5 = 0x80; +_INTCON5 = 0x80; +_INTCON5bits = 0x80; + INTTREG = 0x84; +_INTTREG = 0x84; +_INTTREGbits = 0x84; + IVTBASE = 0x88; +_IVTBASE = 0x88; +_IVTBASEbits = 0x88; + IVTCREG = 0x8C; +_IVTCREG = 0x8C; +_IVTCREGbits = 0x8C; + IFS0 = 0x90; +_IFS0 = 0x90; +_IFS0bits = 0x90; + IFS1 = 0x94; +_IFS1 = 0x94; +_IFS1bits = 0x94; + IFS2 = 0x98; +_IFS2 = 0x98; +_IFS2bits = 0x98; + IFS3 = 0x9C; +_IFS3 = 0x9C; +_IFS3bits = 0x9C; + IFS4 = 0xA0; +_IFS4 = 0xA0; +_IFS4bits = 0xA0; + IFS5 = 0xA4; +_IFS5 = 0xA4; +_IFS5bits = 0xA4; + IFS6 = 0xA8; +_IFS6 = 0xA8; +_IFS6bits = 0xA8; + IFS7 = 0xAC; +_IFS7 = 0xAC; +_IFS7bits = 0xAC; + IFS8 = 0xB0; +_IFS8 = 0xB0; +_IFS8bits = 0xB0; + IFS9 = 0xB4; +_IFS9 = 0xB4; +_IFS9bits = 0xB4; + IFS10 = 0xB8; +_IFS10 = 0xB8; +_IFS10bits = 0xB8; + IFS11 = 0xBC; +_IFS11 = 0xBC; +_IFS11bits = 0xBC; + IEC0 = 0xC0; +_IEC0 = 0xC0; +_IEC0bits = 0xC0; + IEC1 = 0xC4; +_IEC1 = 0xC4; +_IEC1bits = 0xC4; + IEC2 = 0xC8; +_IEC2 = 0xC8; +_IEC2bits = 0xC8; + IEC3 = 0xCC; +_IEC3 = 0xCC; +_IEC3bits = 0xCC; + IEC4 = 0xD0; +_IEC4 = 0xD0; +_IEC4bits = 0xD0; + IEC5 = 0xD4; +_IEC5 = 0xD4; +_IEC5bits = 0xD4; + IEC6 = 0xD8; +_IEC6 = 0xD8; +_IEC6bits = 0xD8; + IEC7 = 0xDC; +_IEC7 = 0xDC; +_IEC7bits = 0xDC; + IEC8 = 0xE0; +_IEC8 = 0xE0; +_IEC8bits = 0xE0; + IEC9 = 0xE4; +_IEC9 = 0xE4; +_IEC9bits = 0xE4; + IEC10 = 0xE8; +_IEC10 = 0xE8; +_IEC10bits = 0xE8; + IEC11 = 0xEC; +_IEC11 = 0xEC; +_IEC11bits = 0xEC; + IPC0 = 0xF0; +_IPC0 = 0xF0; +_IPC0bits = 0xF0; + IPC1 = 0xF4; +_IPC1 = 0xF4; +_IPC1bits = 0xF4; + IPC2 = 0xF8; +_IPC2 = 0xF8; +_IPC2bits = 0xF8; + IPC3 = 0xFC; +_IPC3 = 0xFC; +_IPC3bits = 0xFC; + IPC4 = 0x100; +_IPC4 = 0x100; +_IPC4bits = 0x100; + IPC5 = 0x104; +_IPC5 = 0x104; +_IPC5bits = 0x104; + IPC6 = 0x108; +_IPC6 = 0x108; +_IPC6bits = 0x108; + IPC7 = 0x10C; +_IPC7 = 0x10C; +_IPC7bits = 0x10C; + IPC8 = 0x110; +_IPC8 = 0x110; +_IPC8bits = 0x110; + IPC9 = 0x114; +_IPC9 = 0x114; +_IPC9bits = 0x114; + IPC10 = 0x118; +_IPC10 = 0x118; +_IPC10bits = 0x118; + IPC11 = 0x11C; +_IPC11 = 0x11C; +_IPC11bits = 0x11C; + IPC12 = 0x120; +_IPC12 = 0x120; +_IPC12bits = 0x120; + IPC13 = 0x124; +_IPC13 = 0x124; +_IPC13bits = 0x124; + IPC14 = 0x128; +_IPC14 = 0x128; +_IPC14bits = 0x128; + IPC15 = 0x12C; +_IPC15 = 0x12C; +_IPC15bits = 0x12C; + IPC16 = 0x130; +_IPC16 = 0x130; +_IPC16bits = 0x130; + IPC17 = 0x134; +_IPC17 = 0x134; +_IPC17bits = 0x134; + IPC18 = 0x138; +_IPC18 = 0x138; +_IPC18bits = 0x138; + IPC19 = 0x13C; +_IPC19 = 0x13C; +_IPC19bits = 0x13C; + IPC20 = 0x140; +_IPC20 = 0x140; +_IPC20bits = 0x140; + IPC21 = 0x144; +_IPC21 = 0x144; +_IPC21bits = 0x144; + IPC22 = 0x148; +_IPC22 = 0x148; +_IPC22bits = 0x148; + IPC23 = 0x14C; +_IPC23 = 0x14C; +_IPC23bits = 0x14C; + IPC24 = 0x150; +_IPC24 = 0x150; +_IPC24bits = 0x150; + IPC25 = 0x154; +_IPC25 = 0x154; +_IPC25bits = 0x154; + IPC26 = 0x158; +_IPC26 = 0x158; +_IPC26bits = 0x158; + IPC27 = 0x15C; +_IPC27 = 0x15C; +_IPC27bits = 0x15C; + IPC28 = 0x160; +_IPC28 = 0x160; +_IPC28bits = 0x160; + IPC29 = 0x164; +_IPC29 = 0x164; +_IPC29bits = 0x164; + IPC30 = 0x168; +_IPC30 = 0x168; +_IPC30bits = 0x168; + IPC31 = 0x16C; +_IPC31 = 0x16C; +_IPC31bits = 0x16C; + IPC32 = 0x170; +_IPC32 = 0x170; +_IPC32bits = 0x170; + IPC33 = 0x174; +_IPC33 = 0x174; +_IPC33bits = 0x174; + IPC34 = 0x178; +_IPC34 = 0x178; +_IPC34bits = 0x178; + IPC35 = 0x17C; +_IPC35 = 0x17C; +_IPC35bits = 0x17C; + IPC36 = 0x180; +_IPC36 = 0x180; +_IPC36bits = 0x180; + IPC37 = 0x184; +_IPC37 = 0x184; +_IPC37bits = 0x184; + IPC39 = 0x18C; +_IPC39 = 0x18C; +_IPC39bits = 0x18C; + IPC40 = 0x190; +_IPC40 = 0x190; +_IPC40bits = 0x190; + IPC41 = 0x194; +_IPC41 = 0x194; +_IPC41bits = 0x194; + IPC42 = 0x198; +_IPC42 = 0x198; +_IPC42bits = 0x198; + IPC43 = 0x19C; +_IPC43 = 0x19C; +_IPC43bits = 0x19C; + IPC44 = 0x1A0; +_IPC44 = 0x1A0; +_IPC44bits = 0x1A0; + PORTA = 0x200; +_PORTA = 0x200; +_PORTAbits = 0x200; + LATA = 0x204; +_LATA = 0x204; +_LATAbits = 0x204; + TRISA = 0x208; +_TRISA = 0x208; +_TRISAbits = 0x208; + CNSTATA = 0x20C; +_CNSTATA = 0x20C; +_CNSTATAbits = 0x20C; + CNFA = 0x210; +_CNFA = 0x210; +_CNFAbits = 0x210; + PORTB = 0x214; +_PORTB = 0x214; +_PORTBbits = 0x214; + LATB = 0x218; +_LATB = 0x218; +_LATBbits = 0x218; + TRISB = 0x21C; +_TRISB = 0x21C; +_TRISBbits = 0x21C; + CNSTATB = 0x220; +_CNSTATB = 0x220; +_CNSTATBbits = 0x220; + CNFB = 0x224; +_CNFB = 0x224; +_CNFBbits = 0x224; + PORTC = 0x228; +_PORTC = 0x228; +_PORTCbits = 0x228; + LATC = 0x22C; +_LATC = 0x22C; +_LATCbits = 0x22C; + TRISC = 0x230; +_TRISC = 0x230; +_TRISCbits = 0x230; + CNSTATC = 0x234; +_CNSTATC = 0x234; +_CNSTATCbits = 0x234; + CNFC = 0x238; +_CNFC = 0x238; +_CNFCbits = 0x238; + PORTD = 0x23C; +_PORTD = 0x23C; +_PORTDbits = 0x23C; + LATD = 0x240; +_LATD = 0x240; +_LATDbits = 0x240; + TRISD = 0x244; +_TRISD = 0x244; +_TRISDbits = 0x244; + CNSTATD = 0x248; +_CNSTATD = 0x248; +_CNSTATDbits = 0x248; + CNFD = 0x24C; +_CNFD = 0x24C; +_CNFDbits = 0x24C; + PORTE = 0x250; +_PORTE = 0x250; +_PORTEbits = 0x250; + LATE = 0x254; +_LATE = 0x254; +_LATEbits = 0x254; + TRISE = 0x258; +_TRISE = 0x258; +_TRISEbits = 0x258; + CNSTATE = 0x25C; +_CNSTATE = 0x25C; +_CNSTATEbits = 0x25C; + CNFE = 0x260; +_CNFE = 0x260; +_CNFEbits = 0x260; + PORTF = 0x264; +_PORTF = 0x264; +_PORTFbits = 0x264; + LATF = 0x268; +_LATF = 0x268; +_LATFbits = 0x268; + TRISF = 0x26C; +_TRISF = 0x26C; +_TRISFbits = 0x26C; + CNSTATF = 0x270; +_CNSTATF = 0x270; +_CNSTATFbits = 0x270; + CNFF = 0x274; +_CNFF = 0x274; +_CNFFbits = 0x274; + PORTG = 0x278; +_PORTG = 0x278; +_PORTGbits = 0x278; + LATG = 0x27C; +_LATG = 0x27C; +_LATGbits = 0x27C; + TRISG = 0x280; +_TRISG = 0x280; +_TRISGbits = 0x280; + CNSTATG = 0x284; +_CNSTATG = 0x284; +_CNSTATGbits = 0x284; + CNFG = 0x288; +_CNFG = 0x288; +_CNFGbits = 0x288; + PORTH = 0x28C; +_PORTH = 0x28C; +_PORTHbits = 0x28C; + LATH = 0x290; +_LATH = 0x290; +_LATHbits = 0x290; + TRISH = 0x294; +_TRISH = 0x294; +_TRISHbits = 0x294; + CNSTATH = 0x298; +_CNSTATH = 0x298; +_CNSTATHbits = 0x298; + CNFH = 0x29C; +_CNFH = 0x29C; +_CNFHbits = 0x29C; + CRCCON = 0x2C8; +_CRCCON = 0x2C8; +_CRCCONbits = 0x2C8; + CRCXOR = 0x2CC; +_CRCXOR = 0x2CC; +_CRCXORbits = 0x2CC; + CRCDAT = 0x2D0; +_CRCDAT = 0x2D0; + CRCWDAT = 0x2D4; +_CRCWDAT = 0x2D4; + UCPROT = 0x2E0; +_UCPROT = 0x2E0; +_UCPROTbits = 0x2E0; + IRTCTRL = 0x2E4; +_IRTCTRL = 0x2E4; +_IRTCTRLbits = 0x2E4; + IRTSTAT = 0x2E8; +_IRTSTAT = 0x2E8; + PR0CTRL = 0x300; +_PR0CTRL = 0x300; +_PR0CTRLbits = 0x300; + PR0ST = 0x304; +_PR0ST = 0x304; +_PR0STbits = 0x304; + PR0END = 0x308; +_PR0END = 0x308; +_PR0ENDbits = 0x308; + PR0LOCK = 0x30C; +_PR0LOCK = 0x30C; +_PR0LOCKbits = 0x30C; + PR1CTRL = 0x310; +_PR1CTRL = 0x310; +_PR1CTRLbits = 0x310; + PR1ST = 0x314; +_PR1ST = 0x314; +_PR1STbits = 0x314; + PR1END = 0x318; +_PR1END = 0x318; +_PR1ENDbits = 0x318; + PR1LOCK = 0x31C; +_PR1LOCK = 0x31C; +_PR1LOCKbits = 0x31C; + PR2CTRL = 0x320; +_PR2CTRL = 0x320; +_PR2CTRLbits = 0x320; + PR2ST = 0x324; +_PR2ST = 0x324; +_PR2STbits = 0x324; + PR2END = 0x328; +_PR2END = 0x328; +_PR2ENDbits = 0x328; + PR2LOCK = 0x32C; +_PR2LOCK = 0x32C; +_PR2LOCKbits = 0x32C; + PR3CTRL = 0x330; +_PR3CTRL = 0x330; +_PR3CTRLbits = 0x330; + PR3ST = 0x334; +_PR3ST = 0x334; +_PR3STbits = 0x334; + PR3END = 0x338; +_PR3END = 0x338; +_PR3ENDbits = 0x338; + PR3LOCK = 0x33C; +_PR3LOCK = 0x33C; +_PR3LOCKbits = 0x33C; + PR4CTRL = 0x340; +_PR4CTRL = 0x340; +_PR4CTRLbits = 0x340; + PR4ST = 0x344; +_PR4ST = 0x344; +_PR4STbits = 0x344; + PR4END = 0x348; +_PR4END = 0x348; +_PR4ENDbits = 0x348; + PR4LOCK = 0x34C; +_PR4LOCK = 0x34C; +_PR4LOCKbits = 0x34C; + PR5CTRL = 0x350; +_PR5CTRL = 0x350; +_PR5CTRLbits = 0x350; + PR5ST = 0x354; +_PR5ST = 0x354; +_PR5STbits = 0x354; + PR5END = 0x358; +_PR5END = 0x358; +_PR5ENDbits = 0x358; + PR5LOCK = 0x35C; +_PR5LOCK = 0x35C; +_PR5LOCKbits = 0x35C; + PR6CTRL = 0x360; +_PR6CTRL = 0x360; +_PR6CTRLbits = 0x360; + PR6ST = 0x364; +_PR6ST = 0x364; +_PR6STbits = 0x364; + PR6END = 0x368; +_PR6END = 0x368; +_PR6ENDbits = 0x368; + PR6LOCK = 0x36C; +_PR6LOCK = 0x36C; +_PR6LOCKbits = 0x36C; + PR7CTRL = 0x370; +_PR7CTRL = 0x370; +_PR7CTRLbits = 0x370; + PR7ST = 0x374; +_PR7ST = 0x374; +_PR7STbits = 0x374; + PR7END = 0x378; +_PR7END = 0x378; +_PR7ENDbits = 0x378; + PR7LOCK = 0x37C; +_PR7LOCK = 0x37C; +_PR7LOCKbits = 0x37C; + ITCCON1 = 0x380; +_ITCCON1 = 0x380; +_ITCCON1bits = 0x380; + ITCCON2 = 0x384; +_ITCCON2 = 0x384; +_ITCCON2bits = 0x384; + ITCSTAT = 0x388; +_ITCSTAT = 0x388; +_ITCSTATbits = 0x388; + ITCTXA = 0x38C; +_ITCTXA = 0x38C; +_ITCTXAbits = 0x38C; + ITCTXB = 0x390; +_ITCTXB = 0x390; +_ITCTXBbits = 0x390; + ITCTXC = 0x394; +_ITCTXC = 0x394; +_ITCTXCbits = 0x394; + ADHIT = 0x398; +_ADHIT = 0x398; +_ADHITbits = 0x398; + ITCLS0CON = 0x39C; +_ITCLS0CON = 0x39C; +_ITCLS0CONbits = 0x39C; + ITCLS0STAT = 0x3A0; +_ITCLS0STAT = 0x3A0; +_ITCLS0STATbits = 0x3A0; + ITCLS0CMPHI = 0x3A4; +_ITCLS0CMPHI = 0x3A4; + ITCLS0CMPLO = 0x3A8; +_ITCLS0CMPLO = 0x3A8; + ITCLS0MUL = 0x3AC; +_ITCLS0MUL = 0x3AC; +_ITCLS0MULbits = 0x3AC; + ITCLS0SEQ = 0x3B0; +_ITCLS0SEQ = 0x3B0; +_ITCLS0SEQbits = 0x3B0; + ITCLS0TMR = 0x3B4; +_ITCLS0TMR = 0x3B4; +_ITCLS0TMRbits = 0x3B4; + ITCLS1CON = 0x3B8; +_ITCLS1CON = 0x3B8; +_ITCLS1CONbits = 0x3B8; + ITCLS1STAT = 0x3BC; +_ITCLS1STAT = 0x3BC; +_ITCLS1STATbits = 0x3BC; + ITCLS1CMPHI = 0x3C0; +_ITCLS1CMPHI = 0x3C0; + ITCLS1CMPLO = 0x3C4; +_ITCLS1CMPLO = 0x3C4; + ITCLS1MUL = 0x3C8; +_ITCLS1MUL = 0x3C8; +_ITCLS1MULbits = 0x3C8; + ITCLS1SEQ = 0x3CC; +_ITCLS1SEQ = 0x3CC; +_ITCLS1SEQbits = 0x3CC; + ITCLS1TMR = 0x3D0; +_ITCLS1TMR = 0x3D0; +_ITCLS1TMRbits = 0x3D0; + ITCLS2CON = 0x3D4; +_ITCLS2CON = 0x3D4; +_ITCLS2CONbits = 0x3D4; + ITCLS2STAT = 0x3D8; +_ITCLS2STAT = 0x3D8; +_ITCLS2STATbits = 0x3D8; + ITCLS2CMPHI = 0x3DC; +_ITCLS2CMPHI = 0x3DC; + ITCLS2CMPLO = 0x3E0; +_ITCLS2CMPLO = 0x3E0; + ITCLS2MUL = 0x3E4; +_ITCLS2MUL = 0x3E4; +_ITCLS2MULbits = 0x3E4; + ITCLS2SEQ = 0x3E8; +_ITCLS2SEQ = 0x3E8; +_ITCLS2SEQbits = 0x3E8; + ITCLS2TMR = 0x3EC; +_ITCLS2TMR = 0x3EC; +_ITCLS2TMRbits = 0x3EC; + ITCREC0 = 0x3F0; +_ITCREC0 = 0x3F0; +_ITCREC0bits = 0x3F0; + ITCREC1 = 0x3F4; +_ITCREC1 = 0x3F4; +_ITCREC1bits = 0x3F4; + ITCREC2 = 0x3F8; +_ITCREC2 = 0x3F8; +_ITCREC2bits = 0x3F8; + ITCREC3 = 0x3FC; +_ITCREC3 = 0x3FC; +_ITCREC3bits = 0x3FC; + ITCREC4 = 0x400; +_ITCREC4 = 0x400; +_ITCREC4bits = 0x400; + ITCREC5 = 0x404; +_ITCREC5 = 0x404; +_ITCREC5bits = 0x404; + ITCREC6 = 0x408; +_ITCREC6 = 0x408; +_ITCREC6bits = 0x408; + ITCREC7 = 0x40C; +_ITCREC7 = 0x40C; +_ITCREC7bits = 0x40C; + ITCREC8 = 0x410; +_ITCREC8 = 0x410; +_ITCREC8bits = 0x410; + ITCREC9 = 0x414; +_ITCREC9 = 0x414; +_ITCREC9bits = 0x414; + ITCREC10 = 0x418; +_ITCREC10 = 0x418; +_ITCREC10bits = 0x418; + ITCREC11 = 0x41C; +_ITCREC11 = 0x41C; +_ITCREC11bits = 0x41C; + ITCREC12 = 0x420; +_ITCREC12 = 0x420; +_ITCREC12bits = 0x420; + ITCREC13 = 0x424; +_ITCREC13 = 0x424; +_ITCREC13bits = 0x424; + ITCREC14 = 0x428; +_ITCREC14 = 0x428; +_ITCREC14bits = 0x428; + ITCREC15 = 0x42C; +_ITCREC15 = 0x42C; +_ITCREC15bits = 0x42C; + ITCRES0 = 0x430; +_ITCRES0 = 0x430; + ITCRES1 = 0x434; +_ITCRES1 = 0x434; + ITCRES2 = 0x438; +_ITCRES2 = 0x438; + ITCRES3 = 0x43C; +_ITCRES3 = 0x43C; + ITCRES4 = 0x440; +_ITCRES4 = 0x440; + ITCRES5 = 0x444; +_ITCRES5 = 0x444; + ITCRES6 = 0x448; +_ITCRES6 = 0x448; + ITCRES7 = 0x44C; +_ITCRES7 = 0x44C; + ITCRES8 = 0x450; +_ITCRES8 = 0x450; + ITCRES9 = 0x454; +_ITCRES9 = 0x454; + ITCRES10 = 0x458; +_ITCRES10 = 0x458; + ITCRES11 = 0x45C; +_ITCRES11 = 0x45C; + ITCRES12 = 0x460; +_ITCRES12 = 0x460; + ITCRES13 = 0x464; +_ITCRES13 = 0x464; + ITCRES14 = 0x468; +_ITCRES14 = 0x468; + ITCRES15 = 0x46C; +_ITCRES15 = 0x46C; + ITCRES16 = 0x470; +_ITCRES16 = 0x470; + ITCRES17 = 0x474; +_ITCRES17 = 0x474; + ITCRES18 = 0x478; +_ITCRES18 = 0x478; + ITCRES19 = 0x47C; +_ITCRES19 = 0x47C; + ITCRES20 = 0x480; +_ITCRES20 = 0x480; + ITCRES21 = 0x484; +_ITCRES21 = 0x484; + ITCRES22 = 0x488; +_ITCRES22 = 0x488; + ITCRES23 = 0x48C; +_ITCRES23 = 0x48C; + ITCRES24 = 0x490; +_ITCRES24 = 0x490; + ITCRES25 = 0x494; +_ITCRES25 = 0x494; + ITCRES26 = 0x498; +_ITCRES26 = 0x498; + ITCRES27 = 0x49C; +_ITCRES27 = 0x49C; + ITCRES28 = 0x4A0; +_ITCRES28 = 0x4A0; + ITCRES29 = 0x4A4; +_ITCRES29 = 0x4A4; + ITCRES30 = 0x4A8; +_ITCRES30 = 0x4A8; + ITCRES31 = 0x4AC; +_ITCRES31 = 0x4AC; + ITCCURRES = 0x4B0; +_ITCCURRES = 0x4B0; + BMXINITPR = 0x770; +_BMXINITPR = 0x770; +_BMXINITPRbits = 0x770; + BMXIRAML = 0x774; +_BMXIRAML = 0x774; + BMXIRAMH = 0x778; +_BMXIRAMH = 0x778; + BMXXDATERR = 0x77C; +_BMXXDATERR = 0x77C; +_BMXXDATERRbits = 0x77C; + BMXYDATERR = 0x780; +_BMXYDATERR = 0x780; +_BMXYDATERRbits = 0x780; + BMXDMAERR = 0x784; +_BMXDMAERR = 0x784; +_BMXDMAERRbits = 0x784; + BMXCPUERR = 0x788; +_BMXCPUERR = 0x788; +_BMXCPUERRbits = 0x788; + BMXCRYPTERR = 0x78C; +_BMXCRYPTERR = 0x78C; +_BMXCRYPTERRbits = 0x78C; + BMXCAN1ERR = 0x790; +_BMXCAN1ERR = 0x790; +_BMXCAN1ERRbits = 0x790; + BMXCAN2ERR = 0x794; +_BMXCAN2ERR = 0x794; +_BMXCAN2ERRbits = 0x794; + BMXNVMERR = 0x798; +_BMXNVMERR = 0x798; +_BMXNVMERRbits = 0x798; + BMXICDERR = 0x79C; +_BMXICDERR = 0x79C; +_BMXICDERRbits = 0x79C; + AD1CON = 0x800; +_AD1CON = 0x800; +_AD1CONbits = 0x800; + AD1DATAOVR = 0x804; +_AD1DATAOVR = 0x804; + AD1STAT = 0x808; +_AD1STAT = 0x808; +_AD1STATbits = 0x808; + AD1RSTAT = 0x80C; +_AD1RSTAT = 0x80C; +_AD1RSTATbits = 0x80C; + AD1CMPSTAT = 0x810; +_AD1CMPSTAT = 0x810; +_AD1CMPSTATbits = 0x810; + AD1SWTRG = 0x814; +_AD1SWTRG = 0x814; +_AD1SWTRGbits = 0x814; + AD1CH0CON1 = 0x818; +_AD1CH0CON1 = 0x818; +_AD1CH0CON1bits = 0x818; + AD1CH0CON2 = 0x81C; +_AD1CH0CON2 = 0x81C; +_AD1CH0CON2bits = 0x81C; + AD1CH0DATA = 0x820; +_AD1CH0DATA = 0x820; + AD1CH0RES = 0x824; +_AD1CH0RES = 0x824; +_AD1CH0RESbits = 0x824; + AD1CH0CNT = 0x828; +_AD1CH0CNT = 0x828; +_AD1CH0CNTbits = 0x828; + AD1CH0CMPLO = 0x82C; +_AD1CH0CMPLO = 0x82C; + AD1CH0CMPHI = 0x830; +_AD1CH0CMPHI = 0x830; + AD1CH1CON1 = 0x838; +_AD1CH1CON1 = 0x838; +_AD1CH1CON1bits = 0x838; + AD1CH1CON2 = 0x83C; +_AD1CH1CON2 = 0x83C; +_AD1CH1CON2bits = 0x83C; + AD1CH1DATA = 0x840; +_AD1CH1DATA = 0x840; + AD1CH1RES = 0x844; +_AD1CH1RES = 0x844; +_AD1CH1RESbits = 0x844; + AD1CH1CNT = 0x848; +_AD1CH1CNT = 0x848; +_AD1CH1CNTbits = 0x848; + AD1CH1CMPLO = 0x84C; +_AD1CH1CMPLO = 0x84C; + AD1CH1CMPHI = 0x850; +_AD1CH1CMPHI = 0x850; + AD1CH2CON1 = 0x858; +_AD1CH2CON1 = 0x858; +_AD1CH2CON1bits = 0x858; + AD1CH2CON2 = 0x85C; +_AD1CH2CON2 = 0x85C; +_AD1CH2CON2bits = 0x85C; + AD1CH2DATA = 0x860; +_AD1CH2DATA = 0x860; + AD1CH2RES = 0x864; +_AD1CH2RES = 0x864; +_AD1CH2RESbits = 0x864; + AD1CH2CNT = 0x868; +_AD1CH2CNT = 0x868; +_AD1CH2CNTbits = 0x868; + AD1CH2CMPLO = 0x86C; +_AD1CH2CMPLO = 0x86C; + AD1CH2CMPHI = 0x870; +_AD1CH2CMPHI = 0x870; + AD1CH3CON1 = 0x878; +_AD1CH3CON1 = 0x878; +_AD1CH3CON1bits = 0x878; + AD1CH3CON2 = 0x87C; +_AD1CH3CON2 = 0x87C; +_AD1CH3CON2bits = 0x87C; + AD1CH3DATA = 0x880; +_AD1CH3DATA = 0x880; + AD1CH3RES = 0x884; +_AD1CH3RES = 0x884; +_AD1CH3RESbits = 0x884; + AD1CH3CNT = 0x888; +_AD1CH3CNT = 0x888; +_AD1CH3CNTbits = 0x888; + AD1CH3CMPLO = 0x88C; +_AD1CH3CMPLO = 0x88C; + AD1CH3CMPHI = 0x890; +_AD1CH3CMPHI = 0x890; + AD1CH4CON1 = 0x898; +_AD1CH4CON1 = 0x898; +_AD1CH4CON1bits = 0x898; + AD1CH4CON2 = 0x89C; +_AD1CH4CON2 = 0x89C; +_AD1CH4CON2bits = 0x89C; + AD1CH4DATA = 0x8A0; +_AD1CH4DATA = 0x8A0; + AD1CH4RES = 0x8A4; +_AD1CH4RES = 0x8A4; +_AD1CH4RESbits = 0x8A4; + AD1CH4CNT = 0x8A8; +_AD1CH4CNT = 0x8A8; +_AD1CH4CNTbits = 0x8A8; + AD1CH4CMPLO = 0x8AC; +_AD1CH4CMPLO = 0x8AC; + AD1CH4CMPHI = 0x8B0; +_AD1CH4CMPHI = 0x8B0; + AD1CH5CON1 = 0x8B8; +_AD1CH5CON1 = 0x8B8; +_AD1CH5CON1bits = 0x8B8; + AD1CH5CON2 = 0x8BC; +_AD1CH5CON2 = 0x8BC; +_AD1CH5CON2bits = 0x8BC; + AD1CH5DATA = 0x8C0; +_AD1CH5DATA = 0x8C0; + AD1CH5RES = 0x8C4; +_AD1CH5RES = 0x8C4; +_AD1CH5RESbits = 0x8C4; + AD1CH5CNT = 0x8C8; +_AD1CH5CNT = 0x8C8; +_AD1CH5CNTbits = 0x8C8; + AD1CH5CMPLO = 0x8CC; +_AD1CH5CMPLO = 0x8CC; + AD1CH5CMPHI = 0x8D0; +_AD1CH5CMPHI = 0x8D0; + AD1CH6CON1 = 0x8D8; +_AD1CH6CON1 = 0x8D8; +_AD1CH6CON1bits = 0x8D8; + AD1CH6CON2 = 0x8DC; +_AD1CH6CON2 = 0x8DC; +_AD1CH6CON2bits = 0x8DC; + AD1CH6DATA = 0x8E0; +_AD1CH6DATA = 0x8E0; + AD1CH6RES = 0x8E4; +_AD1CH6RES = 0x8E4; +_AD1CH6RESbits = 0x8E4; + AD1CH6CNT = 0x8E8; +_AD1CH6CNT = 0x8E8; +_AD1CH6CNTbits = 0x8E8; + AD1CH6CMPLO = 0x8EC; +_AD1CH6CMPLO = 0x8EC; + AD1CH6CMPHI = 0x8F0; +_AD1CH6CMPHI = 0x8F0; + AD1CH6ACC = 0x8F4; +_AD1CH6ACC = 0x8F4; + AD1CH7CON1 = 0x8F8; +_AD1CH7CON1 = 0x8F8; +_AD1CH7CON1bits = 0x8F8; + AD1CH7CON2 = 0x8FC; +_AD1CH7CON2 = 0x8FC; +_AD1CH7CON2bits = 0x8FC; + AD1CH7DATA = 0x900; +_AD1CH7DATA = 0x900; + AD1CH7RES = 0x904; +_AD1CH7RES = 0x904; +_AD1CH7RESbits = 0x904; + AD1CH7CNT = 0x908; +_AD1CH7CNT = 0x908; +_AD1CH7CNTbits = 0x908; + AD1CH7CMPLO = 0x90C; +_AD1CH7CMPLO = 0x90C; + AD1CH7CMPHI = 0x910; +_AD1CH7CMPHI = 0x910; + AD1CH7ACC = 0x914; +_AD1CH7ACC = 0x914; + AD2CON = 0xA00; +_AD2CON = 0xA00; +_AD2CONbits = 0xA00; + AD2DATAOVR = 0xA04; +_AD2DATAOVR = 0xA04; + AD2STAT = 0xA08; +_AD2STAT = 0xA08; +_AD2STATbits = 0xA08; + AD2RSTAT = 0xA0C; +_AD2RSTAT = 0xA0C; +_AD2RSTATbits = 0xA0C; + AD2CMPSTAT = 0xA10; +_AD2CMPSTAT = 0xA10; +_AD2CMPSTATbits = 0xA10; + AD2SWTRG = 0xA14; +_AD2SWTRG = 0xA14; +_AD2SWTRGbits = 0xA14; + AD2CH0CON1 = 0xA18; +_AD2CH0CON1 = 0xA18; +_AD2CH0CON1bits = 0xA18; + AD2CH0CON2 = 0xA1C; +_AD2CH0CON2 = 0xA1C; +_AD2CH0CON2bits = 0xA1C; + AD2CH0DATA = 0xA20; +_AD2CH0DATA = 0xA20; + AD2CH0RES = 0xA24; +_AD2CH0RES = 0xA24; +_AD2CH0RESbits = 0xA24; + AD2CH0CNT = 0xA28; +_AD2CH0CNT = 0xA28; +_AD2CH0CNTbits = 0xA28; + AD2CH0CMPLO = 0xA2C; +_AD2CH0CMPLO = 0xA2C; + AD2CH0CMPHI = 0xA30; +_AD2CH0CMPHI = 0xA30; + AD2CH1CON1 = 0xA38; +_AD2CH1CON1 = 0xA38; +_AD2CH1CON1bits = 0xA38; + AD2CH1CON2 = 0xA3C; +_AD2CH1CON2 = 0xA3C; +_AD2CH1CON2bits = 0xA3C; + AD2CH1DATA = 0xA40; +_AD2CH1DATA = 0xA40; + AD2CH1RES = 0xA44; +_AD2CH1RES = 0xA44; +_AD2CH1RESbits = 0xA44; + AD2CH1CNT = 0xA48; +_AD2CH1CNT = 0xA48; +_AD2CH1CNTbits = 0xA48; + AD2CH1CMPLO = 0xA4C; +_AD2CH1CMPLO = 0xA4C; + AD2CH1CMPHI = 0xA50; +_AD2CH1CMPHI = 0xA50; + AD2CH2CON1 = 0xA58; +_AD2CH2CON1 = 0xA58; +_AD2CH2CON1bits = 0xA58; + AD2CH2CON2 = 0xA5C; +_AD2CH2CON2 = 0xA5C; +_AD2CH2CON2bits = 0xA5C; + AD2CH2DATA = 0xA60; +_AD2CH2DATA = 0xA60; + AD2CH2RES = 0xA64; +_AD2CH2RES = 0xA64; +_AD2CH2RESbits = 0xA64; + AD2CH2CNT = 0xA68; +_AD2CH2CNT = 0xA68; +_AD2CH2CNTbits = 0xA68; + AD2CH2CMPLO = 0xA6C; +_AD2CH2CMPLO = 0xA6C; + AD2CH2CMPHI = 0xA70; +_AD2CH2CMPHI = 0xA70; + AD2CH3CON1 = 0xA78; +_AD2CH3CON1 = 0xA78; +_AD2CH3CON1bits = 0xA78; + AD2CH3CON2 = 0xA7C; +_AD2CH3CON2 = 0xA7C; +_AD2CH3CON2bits = 0xA7C; + AD2CH3DATA = 0xA80; +_AD2CH3DATA = 0xA80; + AD2CH3RES = 0xA84; +_AD2CH3RES = 0xA84; +_AD2CH3RESbits = 0xA84; + AD2CH3CNT = 0xA88; +_AD2CH3CNT = 0xA88; +_AD2CH3CNTbits = 0xA88; + AD2CH3CMPLO = 0xA8C; +_AD2CH3CMPLO = 0xA8C; + AD2CH3CMPHI = 0xA90; +_AD2CH3CMPHI = 0xA90; + AD2CH4CON1 = 0xA98; +_AD2CH4CON1 = 0xA98; +_AD2CH4CON1bits = 0xA98; + AD2CH4CON2 = 0xA9C; +_AD2CH4CON2 = 0xA9C; +_AD2CH4CON2bits = 0xA9C; + AD2CH4DATA = 0xAA0; +_AD2CH4DATA = 0xAA0; + AD2CH4RES = 0xAA4; +_AD2CH4RES = 0xAA4; +_AD2CH4RESbits = 0xAA4; + AD2CH4CNT = 0xAA8; +_AD2CH4CNT = 0xAA8; +_AD2CH4CNTbits = 0xAA8; + AD2CH4CMPLO = 0xAAC; +_AD2CH4CMPLO = 0xAAC; + AD2CH4CMPHI = 0xAB0; +_AD2CH4CMPHI = 0xAB0; + AD2CH5CON1 = 0xAB8; +_AD2CH5CON1 = 0xAB8; +_AD2CH5CON1bits = 0xAB8; + AD2CH5CON2 = 0xABC; +_AD2CH5CON2 = 0xABC; +_AD2CH5CON2bits = 0xABC; + AD2CH5DATA = 0xAC0; +_AD2CH5DATA = 0xAC0; + AD2CH5RES = 0xAC4; +_AD2CH5RES = 0xAC4; +_AD2CH5RESbits = 0xAC4; + AD2CH5CNT = 0xAC8; +_AD2CH5CNT = 0xAC8; +_AD2CH5CNTbits = 0xAC8; + AD2CH5CMPLO = 0xACC; +_AD2CH5CMPLO = 0xACC; + AD2CH5CMPHI = 0xAD0; +_AD2CH5CMPHI = 0xAD0; + AD2CH6CON1 = 0xAD8; +_AD2CH6CON1 = 0xAD8; +_AD2CH6CON1bits = 0xAD8; + AD2CH6CON2 = 0xADC; +_AD2CH6CON2 = 0xADC; +_AD2CH6CON2bits = 0xADC; + AD2CH6DATA = 0xAE0; +_AD2CH6DATA = 0xAE0; + AD2CH6RES = 0xAE4; +_AD2CH6RES = 0xAE4; +_AD2CH6RESbits = 0xAE4; + AD2CH6CNT = 0xAE8; +_AD2CH6CNT = 0xAE8; +_AD2CH6CNTbits = 0xAE8; + AD2CH6CMPLO = 0xAEC; +_AD2CH6CMPLO = 0xAEC; + AD2CH6CMPHI = 0xAF0; +_AD2CH6CMPHI = 0xAF0; + AD2CH6ACC = 0xAF4; +_AD2CH6ACC = 0xAF4; + AD2CH7CON1 = 0xAF8; +_AD2CH7CON1 = 0xAF8; +_AD2CH7CON1bits = 0xAF8; + AD2CH7CON2 = 0xAFC; +_AD2CH7CON2 = 0xAFC; +_AD2CH7CON2bits = 0xAFC; + AD2CH7DATA = 0xB00; +_AD2CH7DATA = 0xB00; + AD2CH7RES = 0xB04; +_AD2CH7RES = 0xB04; +_AD2CH7RESbits = 0xB04; + AD2CH7CNT = 0xB08; +_AD2CH7CNT = 0xB08; +_AD2CH7CNTbits = 0xB08; + AD2CH7CMPLO = 0xB0C; +_AD2CH7CMPLO = 0xB0C; + AD2CH7CMPHI = 0xB10; +_AD2CH7CMPHI = 0xB10; + AD2CH7ACC = 0xB14; +_AD2CH7ACC = 0xB14; + AD3CON = 0xB40; +_AD3CON = 0xB40; +_AD3CONbits = 0xB40; + AD3DATAOVR = 0xB44; +_AD3DATAOVR = 0xB44; + AD3STAT = 0xB48; +_AD3STAT = 0xB48; +_AD3STATbits = 0xB48; + AD3RSTAT = 0xB4C; +_AD3RSTAT = 0xB4C; +_AD3RSTATbits = 0xB4C; + AD3CMPSTAT = 0xB50; +_AD3CMPSTAT = 0xB50; +_AD3CMPSTATbits = 0xB50; + AD3SWTRG = 0xB54; +_AD3SWTRG = 0xB54; +_AD3SWTRGbits = 0xB54; + AD3CH0CON1 = 0xB58; +_AD3CH0CON1 = 0xB58; +_AD3CH0CON1bits = 0xB58; + AD3CH0CON2 = 0xB5C; +_AD3CH0CON2 = 0xB5C; +_AD3CH0CON2bits = 0xB5C; + AD3CH0DATA = 0xB60; +_AD3CH0DATA = 0xB60; + AD3CH0RES = 0xB64; +_AD3CH0RES = 0xB64; +_AD3CH0RESbits = 0xB64; + AD3CH0CNT = 0xB68; +_AD3CH0CNT = 0xB68; +_AD3CH0CNTbits = 0xB68; + AD3CH0CMPLO = 0xB6C; +_AD3CH0CMPLO = 0xB6C; + AD3CH0CMPHI = 0xB70; +_AD3CH0CMPHI = 0xB70; + AD3CH1CON1 = 0xB78; +_AD3CH1CON1 = 0xB78; +_AD3CH1CON1bits = 0xB78; + AD3CH1CON2 = 0xB7C; +_AD3CH1CON2 = 0xB7C; +_AD3CH1CON2bits = 0xB7C; + AD3CH1DATA = 0xB80; +_AD3CH1DATA = 0xB80; + AD3CH1RES = 0xB84; +_AD3CH1RES = 0xB84; +_AD3CH1RESbits = 0xB84; + AD3CH1CNT = 0xB88; +_AD3CH1CNT = 0xB88; +_AD3CH1CNTbits = 0xB88; + AD3CH1CMPLO = 0xB8C; +_AD3CH1CMPLO = 0xB8C; + AD3CH1CMPHI = 0xB90; +_AD3CH1CMPHI = 0xB90; + AD3CH2CON1 = 0xB98; +_AD3CH2CON1 = 0xB98; +_AD3CH2CON1bits = 0xB98; + AD3CH2CON2 = 0xB9C; +_AD3CH2CON2 = 0xB9C; +_AD3CH2CON2bits = 0xB9C; + AD3CH2DATA = 0xBA0; +_AD3CH2DATA = 0xBA0; + AD3CH2RES = 0xBA4; +_AD3CH2RES = 0xBA4; +_AD3CH2RESbits = 0xBA4; + AD3CH2CNT = 0xBA8; +_AD3CH2CNT = 0xBA8; +_AD3CH2CNTbits = 0xBA8; + AD3CH2CMPLO = 0xBAC; +_AD3CH2CMPLO = 0xBAC; + AD3CH2CMPHI = 0xBB0; +_AD3CH2CMPHI = 0xBB0; + AD3CH3CON1 = 0xBB8; +_AD3CH3CON1 = 0xBB8; +_AD3CH3CON1bits = 0xBB8; + AD3CH3CON2 = 0xBBC; +_AD3CH3CON2 = 0xBBC; +_AD3CH3CON2bits = 0xBBC; + AD3CH3DATA = 0xBC0; +_AD3CH3DATA = 0xBC0; + AD3CH3RES = 0xBC4; +_AD3CH3RES = 0xBC4; +_AD3CH3RESbits = 0xBC4; + AD3CH3CNT = 0xBC8; +_AD3CH3CNT = 0xBC8; +_AD3CH3CNTbits = 0xBC8; + AD3CH3CMPLO = 0xBCC; +_AD3CH3CMPLO = 0xBCC; + AD3CH3CMPHI = 0xBD0; +_AD3CH3CMPHI = 0xBD0; + AD3CH4CON1 = 0xBD8; +_AD3CH4CON1 = 0xBD8; +_AD3CH4CON1bits = 0xBD8; + AD3CH4CON2 = 0xBDC; +_AD3CH4CON2 = 0xBDC; +_AD3CH4CON2bits = 0xBDC; + AD3CH4DATA = 0xBE0; +_AD3CH4DATA = 0xBE0; + AD3CH4RES = 0xBE4; +_AD3CH4RES = 0xBE4; +_AD3CH4RESbits = 0xBE4; + AD3CH4CNT = 0xBE8; +_AD3CH4CNT = 0xBE8; +_AD3CH4CNTbits = 0xBE8; + AD3CH4CMPLO = 0xBEC; +_AD3CH4CMPLO = 0xBEC; + AD3CH4CMPHI = 0xBF0; +_AD3CH4CMPHI = 0xBF0; + AD3CH5CON1 = 0xBF8; +_AD3CH5CON1 = 0xBF8; +_AD3CH5CON1bits = 0xBF8; + AD3CH5CON2 = 0xBFC; +_AD3CH5CON2 = 0xBFC; +_AD3CH5CON2bits = 0xBFC; + AD3CH5DATA = 0xC00; +_AD3CH5DATA = 0xC00; + AD3CH5RES = 0xC04; +_AD3CH5RES = 0xC04; +_AD3CH5RESbits = 0xC04; + AD3CH5CNT = 0xC08; +_AD3CH5CNT = 0xC08; +_AD3CH5CNTbits = 0xC08; + AD3CH5CMPLO = 0xC0C; +_AD3CH5CMPLO = 0xC0C; + AD3CH5CMPHI = 0xC10; +_AD3CH5CMPHI = 0xC10; + AD3CH6CON1 = 0xC18; +_AD3CH6CON1 = 0xC18; +_AD3CH6CON1bits = 0xC18; + AD3CH6CON2 = 0xC1C; +_AD3CH6CON2 = 0xC1C; +_AD3CH6CON2bits = 0xC1C; + AD3CH6DATA = 0xC20; +_AD3CH6DATA = 0xC20; + AD3CH6RES = 0xC24; +_AD3CH6RES = 0xC24; +_AD3CH6RESbits = 0xC24; + AD3CH6CNT = 0xC28; +_AD3CH6CNT = 0xC28; +_AD3CH6CNTbits = 0xC28; + AD3CH6CMPLO = 0xC2C; +_AD3CH6CMPLO = 0xC2C; + AD3CH6CMPHI = 0xC30; +_AD3CH6CMPHI = 0xC30; + AD3CH6ACC = 0xC34; +_AD3CH6ACC = 0xC34; + AD3CH7CON1 = 0xC38; +_AD3CH7CON1 = 0xC38; +_AD3CH7CON1bits = 0xC38; + AD3CH7CON2 = 0xC3C; +_AD3CH7CON2 = 0xC3C; +_AD3CH7CON2bits = 0xC3C; + AD3CH7DATA = 0xC40; +_AD3CH7DATA = 0xC40; + AD3CH7RES = 0xC44; +_AD3CH7RES = 0xC44; +_AD3CH7RESbits = 0xC44; + AD3CH7CNT = 0xC48; +_AD3CH7CNT = 0xC48; +_AD3CH7CNTbits = 0xC48; + AD3CH7CMPLO = 0xC4C; +_AD3CH7CMPLO = 0xC4C; + AD3CH7CMPHI = 0xC50; +_AD3CH7CMPHI = 0xC50; + AD3CH7ACC = 0xC54; +_AD3CH7ACC = 0xC54; + AD4CON = 0xC60; +_AD4CON = 0xC60; +_AD4CONbits = 0xC60; + AD4DATAOVR = 0xC64; +_AD4DATAOVR = 0xC64; + AD4STAT = 0xC68; +_AD4STAT = 0xC68; +_AD4STATbits = 0xC68; + AD4RSTAT = 0xC6C; +_AD4RSTAT = 0xC6C; +_AD4RSTATbits = 0xC6C; + AD4CMPSTAT = 0xC70; +_AD4CMPSTAT = 0xC70; +_AD4CMPSTATbits = 0xC70; + AD4SWTRG = 0xC74; +_AD4SWTRG = 0xC74; +_AD4SWTRGbits = 0xC74; + AD4CH0CON1 = 0xC78; +_AD4CH0CON1 = 0xC78; +_AD4CH0CON1bits = 0xC78; + AD4CH0CON2 = 0xC7C; +_AD4CH0CON2 = 0xC7C; +_AD4CH0CON2bits = 0xC7C; + AD4CH0DATA = 0xC80; +_AD4CH0DATA = 0xC80; + AD4CH0RES = 0xC84; +_AD4CH0RES = 0xC84; +_AD4CH0RESbits = 0xC84; + AD4CH0CNT = 0xC88; +_AD4CH0CNT = 0xC88; +_AD4CH0CNTbits = 0xC88; + AD4CH0CMPLO = 0xC8C; +_AD4CH0CMPLO = 0xC8C; + AD4CH0CMPHI = 0xC90; +_AD4CH0CMPHI = 0xC90; + AD4CH1CON1 = 0xC98; +_AD4CH1CON1 = 0xC98; +_AD4CH1CON1bits = 0xC98; + AD4CH1CON2 = 0xC9C; +_AD4CH1CON2 = 0xC9C; +_AD4CH1CON2bits = 0xC9C; + AD4CH1DATA = 0xCA0; +_AD4CH1DATA = 0xCA0; + AD4CH1RES = 0xCA4; +_AD4CH1RES = 0xCA4; +_AD4CH1RESbits = 0xCA4; + AD4CH1CNT = 0xCA8; +_AD4CH1CNT = 0xCA8; +_AD4CH1CNTbits = 0xCA8; + AD4CH1CMPLO = 0xCAC; +_AD4CH1CMPLO = 0xCAC; + AD4CH1CMPHI = 0xCB0; +_AD4CH1CMPHI = 0xCB0; + AD4CH2CON1 = 0xCB8; +_AD4CH2CON1 = 0xCB8; +_AD4CH2CON1bits = 0xCB8; + AD4CH2CON2 = 0xCBC; +_AD4CH2CON2 = 0xCBC; +_AD4CH2CON2bits = 0xCBC; + AD4CH2DATA = 0xCC0; +_AD4CH2DATA = 0xCC0; + AD4CH2RES = 0xCC4; +_AD4CH2RES = 0xCC4; +_AD4CH2RESbits = 0xCC4; + AD4CH2CNT = 0xCC8; +_AD4CH2CNT = 0xCC8; +_AD4CH2CNTbits = 0xCC8; + AD4CH2CMPLO = 0xCCC; +_AD4CH2CMPLO = 0xCCC; + AD4CH2CMPHI = 0xCD0; +_AD4CH2CMPHI = 0xCD0; + AD4CH3CON1 = 0xCD8; +_AD4CH3CON1 = 0xCD8; +_AD4CH3CON1bits = 0xCD8; + AD4CH3CON2 = 0xCDC; +_AD4CH3CON2 = 0xCDC; +_AD4CH3CON2bits = 0xCDC; + AD4CH3DATA = 0xCE0; +_AD4CH3DATA = 0xCE0; + AD4CH3RES = 0xCE4; +_AD4CH3RES = 0xCE4; +_AD4CH3RESbits = 0xCE4; + AD4CH3CNT = 0xCE8; +_AD4CH3CNT = 0xCE8; +_AD4CH3CNTbits = 0xCE8; + AD4CH3CMPLO = 0xCEC; +_AD4CH3CMPLO = 0xCEC; + AD4CH3CMPHI = 0xCF0; +_AD4CH3CMPHI = 0xCF0; + AD4CH4CON1 = 0xCF8; +_AD4CH4CON1 = 0xCF8; +_AD4CH4CON1bits = 0xCF8; + AD4CH4CON2 = 0xCFC; +_AD4CH4CON2 = 0xCFC; +_AD4CH4CON2bits = 0xCFC; + AD4CH4DATA = 0xD00; +_AD4CH4DATA = 0xD00; + AD4CH4RES = 0xD04; +_AD4CH4RES = 0xD04; +_AD4CH4RESbits = 0xD04; + AD4CH4CNT = 0xD08; +_AD4CH4CNT = 0xD08; +_AD4CH4CNTbits = 0xD08; + AD4CH4CMPLO = 0xD0C; +_AD4CH4CMPLO = 0xD0C; + AD4CH4CMPHI = 0xD10; +_AD4CH4CMPHI = 0xD10; + AD4CH5CON1 = 0xD18; +_AD4CH5CON1 = 0xD18; +_AD4CH5CON1bits = 0xD18; + AD4CH5CON2 = 0xD1C; +_AD4CH5CON2 = 0xD1C; +_AD4CH5CON2bits = 0xD1C; + AD4CH5DATA = 0xD20; +_AD4CH5DATA = 0xD20; + AD4CH5RES = 0xD24; +_AD4CH5RES = 0xD24; +_AD4CH5RESbits = 0xD24; + AD4CH5CNT = 0xD28; +_AD4CH5CNT = 0xD28; +_AD4CH5CNTbits = 0xD28; + AD4CH5CMPLO = 0xD2C; +_AD4CH5CMPLO = 0xD2C; + AD4CH5CMPHI = 0xD30; +_AD4CH5CMPHI = 0xD30; + AD4CH6CON1 = 0xD38; +_AD4CH6CON1 = 0xD38; +_AD4CH6CON1bits = 0xD38; + AD4CH6CON2 = 0xD3C; +_AD4CH6CON2 = 0xD3C; +_AD4CH6CON2bits = 0xD3C; + AD4CH6DATA = 0xD40; +_AD4CH6DATA = 0xD40; + AD4CH6RES = 0xD44; +_AD4CH6RES = 0xD44; +_AD4CH6RESbits = 0xD44; + AD4CH6CNT = 0xD48; +_AD4CH6CNT = 0xD48; +_AD4CH6CNTbits = 0xD48; + AD4CH6CMPLO = 0xD4C; +_AD4CH6CMPLO = 0xD4C; + AD4CH6CMPHI = 0xD50; +_AD4CH6CMPHI = 0xD50; + AD4CH6ACC = 0xD54; +_AD4CH6ACC = 0xD54; + AD4CH7CON1 = 0xD58; +_AD4CH7CON1 = 0xD58; +_AD4CH7CON1bits = 0xD58; + AD4CH7CON2 = 0xD5C; +_AD4CH7CON2 = 0xD5C; +_AD4CH7CON2bits = 0xD5C; + AD4CH7DATA = 0xD60; +_AD4CH7DATA = 0xD60; + AD4CH7RES = 0xD64; +_AD4CH7RES = 0xD64; +_AD4CH7RESbits = 0xD64; + AD4CH7CNT = 0xD68; +_AD4CH7CNT = 0xD68; +_AD4CH7CNTbits = 0xD68; + AD4CH7CMPLO = 0xD6C; +_AD4CH7CMPLO = 0xD6C; + AD4CH7CMPHI = 0xD70; +_AD4CH7CMPHI = 0xD70; + AD4CH7ACC = 0xD74; +_AD4CH7ACC = 0xD74; + AD5CON = 0xD80; +_AD5CON = 0xD80; +_AD5CONbits = 0xD80; + AD5DATAOVR = 0xD84; +_AD5DATAOVR = 0xD84; + AD5STAT = 0xD88; +_AD5STAT = 0xD88; +_AD5STATbits = 0xD88; + AD5RSTAT = 0xD8C; +_AD5RSTAT = 0xD8C; +_AD5RSTATbits = 0xD8C; + AD5CMPSTAT = 0xD90; +_AD5CMPSTAT = 0xD90; +_AD5CMPSTATbits = 0xD90; + AD5SWTRG = 0xD94; +_AD5SWTRG = 0xD94; +_AD5SWTRGbits = 0xD94; + AD5CH0CON1 = 0xD98; +_AD5CH0CON1 = 0xD98; +_AD5CH0CON1bits = 0xD98; + AD5CH0CON2 = 0xD9C; +_AD5CH0CON2 = 0xD9C; +_AD5CH0CON2bits = 0xD9C; + AD5CH0DATA = 0xDA0; +_AD5CH0DATA = 0xDA0; + AD5CH0RES = 0xDA4; +_AD5CH0RES = 0xDA4; +_AD5CH0RESbits = 0xDA4; + AD5CH0CNT = 0xDA8; +_AD5CH0CNT = 0xDA8; +_AD5CH0CNTbits = 0xDA8; + AD5CH0CMPLO = 0xDAC; +_AD5CH0CMPLO = 0xDAC; + AD5CH0CMPHI = 0xDB0; +_AD5CH0CMPHI = 0xDB0; + AD5CH1CON1 = 0xDB8; +_AD5CH1CON1 = 0xDB8; +_AD5CH1CON1bits = 0xDB8; + AD5CH1CON2 = 0xDBC; +_AD5CH1CON2 = 0xDBC; +_AD5CH1CON2bits = 0xDBC; + AD5CH1DATA = 0xDC0; +_AD5CH1DATA = 0xDC0; + AD5CH1RES = 0xDC4; +_AD5CH1RES = 0xDC4; +_AD5CH1RESbits = 0xDC4; + AD5CH1CNT = 0xDC8; +_AD5CH1CNT = 0xDC8; +_AD5CH1CNTbits = 0xDC8; + AD5CH1CMPLO = 0xDCC; +_AD5CH1CMPLO = 0xDCC; + AD5CH1CMPHI = 0xDD0; +_AD5CH1CMPHI = 0xDD0; + AD5CH2CON1 = 0xDD8; +_AD5CH2CON1 = 0xDD8; +_AD5CH2CON1bits = 0xDD8; + AD5CH2CON2 = 0xDDC; +_AD5CH2CON2 = 0xDDC; +_AD5CH2CON2bits = 0xDDC; + AD5CH2DATA = 0xDE0; +_AD5CH2DATA = 0xDE0; + AD5CH2RES = 0xDE4; +_AD5CH2RES = 0xDE4; +_AD5CH2RESbits = 0xDE4; + AD5CH2CNT = 0xDE8; +_AD5CH2CNT = 0xDE8; +_AD5CH2CNTbits = 0xDE8; + AD5CH2CMPLO = 0xDEC; +_AD5CH2CMPLO = 0xDEC; + AD5CH2CMPHI = 0xDF0; +_AD5CH2CMPHI = 0xDF0; + AD5CH3CON1 = 0xDF8; +_AD5CH3CON1 = 0xDF8; +_AD5CH3CON1bits = 0xDF8; + AD5CH3CON2 = 0xDFC; +_AD5CH3CON2 = 0xDFC; +_AD5CH3CON2bits = 0xDFC; + AD5CH3DATA = 0xE00; +_AD5CH3DATA = 0xE00; + AD5CH3RES = 0xE04; +_AD5CH3RES = 0xE04; +_AD5CH3RESbits = 0xE04; + AD5CH3CNT = 0xE08; +_AD5CH3CNT = 0xE08; +_AD5CH3CNTbits = 0xE08; + AD5CH3CMPLO = 0xE0C; +_AD5CH3CMPLO = 0xE0C; + AD5CH3CMPHI = 0xE10; +_AD5CH3CMPHI = 0xE10; + AD5CH4CON1 = 0xE18; +_AD5CH4CON1 = 0xE18; +_AD5CH4CON1bits = 0xE18; + AD5CH4CON2 = 0xE1C; +_AD5CH4CON2 = 0xE1C; +_AD5CH4CON2bits = 0xE1C; + AD5CH4DATA = 0xE20; +_AD5CH4DATA = 0xE20; + AD5CH4RES = 0xE24; +_AD5CH4RES = 0xE24; +_AD5CH4RESbits = 0xE24; + AD5CH4CNT = 0xE28; +_AD5CH4CNT = 0xE28; +_AD5CH4CNTbits = 0xE28; + AD5CH4CMPLO = 0xE2C; +_AD5CH4CMPLO = 0xE2C; + AD5CH4CMPHI = 0xE30; +_AD5CH4CMPHI = 0xE30; + AD5CH5CON1 = 0xE38; +_AD5CH5CON1 = 0xE38; +_AD5CH5CON1bits = 0xE38; + AD5CH5CON2 = 0xE3C; +_AD5CH5CON2 = 0xE3C; +_AD5CH5CON2bits = 0xE3C; + AD5CH5DATA = 0xE40; +_AD5CH5DATA = 0xE40; + AD5CH5RES = 0xE44; +_AD5CH5RES = 0xE44; +_AD5CH5RESbits = 0xE44; + AD5CH5CNT = 0xE48; +_AD5CH5CNT = 0xE48; +_AD5CH5CNTbits = 0xE48; + AD5CH5CMPLO = 0xE4C; +_AD5CH5CMPLO = 0xE4C; + AD5CH5CMPHI = 0xE50; +_AD5CH5CMPHI = 0xE50; + AD5CH6CON1 = 0xE58; +_AD5CH6CON1 = 0xE58; +_AD5CH6CON1bits = 0xE58; + AD5CH6CON2 = 0xE5C; +_AD5CH6CON2 = 0xE5C; +_AD5CH6CON2bits = 0xE5C; + AD5CH6DATA = 0xE60; +_AD5CH6DATA = 0xE60; + AD5CH6RES = 0xE64; +_AD5CH6RES = 0xE64; +_AD5CH6RESbits = 0xE64; + AD5CH6CNT = 0xE68; +_AD5CH6CNT = 0xE68; +_AD5CH6CNTbits = 0xE68; + AD5CH6CMPLO = 0xE6C; +_AD5CH6CMPLO = 0xE6C; + AD5CH6CMPHI = 0xE70; +_AD5CH6CMPHI = 0xE70; + AD5CH7CON1 = 0xE78; +_AD5CH7CON1 = 0xE78; +_AD5CH7CON1bits = 0xE78; + AD5CH7CON2 = 0xE7C; +_AD5CH7CON2 = 0xE7C; +_AD5CH7CON2bits = 0xE7C; + AD5CH7DATA = 0xE80; +_AD5CH7DATA = 0xE80; + AD5CH7RES = 0xE84; +_AD5CH7RES = 0xE84; +_AD5CH7RESbits = 0xE84; + AD5CH7CNT = 0xE88; +_AD5CH7CNT = 0xE88; +_AD5CH7CNTbits = 0xE88; + AD5CH7CMPLO = 0xE8C; +_AD5CH7CMPLO = 0xE8C; + AD5CH7CMPHI = 0xE90; +_AD5CH7CMPHI = 0xE90; + AD5CH8CON1 = 0xE98; +_AD5CH8CON1 = 0xE98; +_AD5CH8CON1bits = 0xE98; + AD5CH8CON2 = 0xE9C; +_AD5CH8CON2 = 0xE9C; +_AD5CH8CON2bits = 0xE9C; + AD5CH8DATA = 0xEA0; +_AD5CH8DATA = 0xEA0; + AD5CH8RES = 0xEA4; +_AD5CH8RES = 0xEA4; +_AD5CH8RESbits = 0xEA4; + AD5CH8CNT = 0xEA8; +_AD5CH8CNT = 0xEA8; +_AD5CH8CNTbits = 0xEA8; + AD5CH8CMPLO = 0xEAC; +_AD5CH8CMPLO = 0xEAC; + AD5CH8CMPHI = 0xEB0; +_AD5CH8CMPHI = 0xEB0; + AD5CH9CON1 = 0xEB8; +_AD5CH9CON1 = 0xEB8; +_AD5CH9CON1bits = 0xEB8; + AD5CH9CON2 = 0xEBC; +_AD5CH9CON2 = 0xEBC; +_AD5CH9CON2bits = 0xEBC; + AD5CH9DATA = 0xEC0; +_AD5CH9DATA = 0xEC0; + AD5CH9RES = 0xEC4; +_AD5CH9RES = 0xEC4; +_AD5CH9RESbits = 0xEC4; + AD5CH9CNT = 0xEC8; +_AD5CH9CNT = 0xEC8; +_AD5CH9CNTbits = 0xEC8; + AD5CH9CMPLO = 0xECC; +_AD5CH9CMPLO = 0xECC; + AD5CH9CMPHI = 0xED0; +_AD5CH9CMPHI = 0xED0; + AD5CH10CON1 = 0xED8; +_AD5CH10CON1 = 0xED8; +_AD5CH10CON1bits = 0xED8; + AD5CH10CON2 = 0xEDC; +_AD5CH10CON2 = 0xEDC; +_AD5CH10CON2bits = 0xEDC; + AD5CH10DATA = 0xEE0; +_AD5CH10DATA = 0xEE0; + AD5CH10RES = 0xEE4; +_AD5CH10RES = 0xEE4; +_AD5CH10RESbits = 0xEE4; + AD5CH10CNT = 0xEE8; +_AD5CH10CNT = 0xEE8; +_AD5CH10CNTbits = 0xEE8; + AD5CH10CMPLO = 0xEEC; +_AD5CH10CMPLO = 0xEEC; + AD5CH10CMPHI = 0xEF0; +_AD5CH10CMPHI = 0xEF0; + AD5CH11CON1 = 0xEF8; +_AD5CH11CON1 = 0xEF8; +_AD5CH11CON1bits = 0xEF8; + AD5CH11CON2 = 0xEFC; +_AD5CH11CON2 = 0xEFC; +_AD5CH11CON2bits = 0xEFC; + AD5CH11DATA = 0xF00; +_AD5CH11DATA = 0xF00; + AD5CH11RES = 0xF04; +_AD5CH11RES = 0xF04; +_AD5CH11RESbits = 0xF04; + AD5CH11CNT = 0xF08; +_AD5CH11CNT = 0xF08; +_AD5CH11CNTbits = 0xF08; + AD5CH11CMPLO = 0xF0C; +_AD5CH11CMPLO = 0xF0C; + AD5CH11CMPHI = 0xF10; +_AD5CH11CMPHI = 0xF10; + AD5CH12CON1 = 0xF18; +_AD5CH12CON1 = 0xF18; +_AD5CH12CON1bits = 0xF18; + AD5CH12CON2 = 0xF1C; +_AD5CH12CON2 = 0xF1C; +_AD5CH12CON2bits = 0xF1C; + AD5CH12DATA = 0xF20; +_AD5CH12DATA = 0xF20; + AD5CH12RES = 0xF24; +_AD5CH12RES = 0xF24; +_AD5CH12RESbits = 0xF24; + AD5CH12CNT = 0xF28; +_AD5CH12CNT = 0xF28; +_AD5CH12CNTbits = 0xF28; + AD5CH12CMPLO = 0xF2C; +_AD5CH12CMPLO = 0xF2C; + AD5CH12CMPHI = 0xF30; +_AD5CH12CMPHI = 0xF30; + AD5CH13CON1 = 0xF38; +_AD5CH13CON1 = 0xF38; +_AD5CH13CON1bits = 0xF38; + AD5CH13CON2 = 0xF3C; +_AD5CH13CON2 = 0xF3C; +_AD5CH13CON2bits = 0xF3C; + AD5CH13DATA = 0xF40; +_AD5CH13DATA = 0xF40; + AD5CH13RES = 0xF44; +_AD5CH13RES = 0xF44; +_AD5CH13RESbits = 0xF44; + AD5CH13CNT = 0xF48; +_AD5CH13CNT = 0xF48; +_AD5CH13CNTbits = 0xF48; + AD5CH13CMPLO = 0xF4C; +_AD5CH13CMPLO = 0xF4C; + AD5CH13CMPHI = 0xF50; +_AD5CH13CMPHI = 0xF50; + AD5CH14CON1 = 0xF58; +_AD5CH14CON1 = 0xF58; +_AD5CH14CON1bits = 0xF58; + AD5CH14CON2 = 0xF5C; +_AD5CH14CON2 = 0xF5C; +_AD5CH14CON2bits = 0xF5C; + AD5CH14DATA = 0xF60; +_AD5CH14DATA = 0xF60; + AD5CH14RES = 0xF64; +_AD5CH14RES = 0xF64; +_AD5CH14RESbits = 0xF64; + AD5CH14CNT = 0xF68; +_AD5CH14CNT = 0xF68; +_AD5CH14CNTbits = 0xF68; + AD5CH14CMPLO = 0xF6C; +_AD5CH14CMPLO = 0xF6C; + AD5CH14CMPHI = 0xF70; +_AD5CH14CMPHI = 0xF70; + AD5CH14ACC = 0xF74; +_AD5CH14ACC = 0xF74; + AD5CH15CON1 = 0xF78; +_AD5CH15CON1 = 0xF78; +_AD5CH15CON1bits = 0xF78; + AD5CH15CON2 = 0xF7C; +_AD5CH15CON2 = 0xF7C; +_AD5CH15CON2bits = 0xF7C; + AD5CH15DATA = 0xF80; +_AD5CH15DATA = 0xF80; + AD5CH15RES = 0xF84; +_AD5CH15RES = 0xF84; +_AD5CH15RESbits = 0xF84; + AD5CH15CNT = 0xF88; +_AD5CH15CNT = 0xF88; +_AD5CH15CNTbits = 0xF88; + AD5CH15CMPLO = 0xF8C; +_AD5CH15CMPLO = 0xF8C; + AD5CH15CMPHI = 0xF90; +_AD5CH15CMPHI = 0xF90; + AD5CH15ACC = 0xF94; +_AD5CH15ACC = 0xF94; + PCLKCON = 0x1000; +_PCLKCON = 0x1000; +_PCLKCONbits = 0x1000; + FSCL = 0x1004; +_FSCL = 0x1004; +_FSCLbits = 0x1004; + FSMINPER = 0x1008; +_FSMINPER = 0x1008; +_FSMINPERbits = 0x1008; + MPHASE = 0x100C; +_MPHASE = 0x100C; +_MPHASEbits = 0x100C; + MDC = 0x1010; +_MDC = 0x1010; +_MDCbits = 0x1010; + MPER = 0x1014; +_MPER = 0x1014; +_MPERbits = 0x1014; + LFSR = 0x1018; +_LFSR = 0x1018; +_LFSRbits = 0x1018; + CMBTRIG = 0x101C; +_CMBTRIG = 0x101C; +_CMBTRIGbits = 0x101C; + LOGCONA = 0x1020; +_LOGCONA = 0x1020; +_LOGCONAbits = 0x1020; + LOGCONB = 0x1024; +_LOGCONB = 0x1024; +_LOGCONBbits = 0x1024; + LOGCONC = 0x1028; +_LOGCONC = 0x1028; +_LOGCONCbits = 0x1028; + LOGCOND = 0x102C; +_LOGCOND = 0x102C; +_LOGCONDbits = 0x102C; + LOGCONE = 0x1030; +_LOGCONE = 0x1030; +_LOGCONEbits = 0x1030; + LOGCONF = 0x1034; +_LOGCONF = 0x1034; +_LOGCONFbits = 0x1034; + PWMEVTA = 0x1038; +_PWMEVTA = 0x1038; +_PWMEVTAbits = 0x1038; + PWMEVTB = 0x103C; +_PWMEVTB = 0x103C; +_PWMEVTBbits = 0x103C; + PWMEVTC = 0x1040; +_PWMEVTC = 0x1040; +_PWMEVTCbits = 0x1040; + PWMEVTD = 0x1044; +_PWMEVTD = 0x1044; +_PWMEVTDbits = 0x1044; + PWMEVTE = 0x1048; +_PWMEVTE = 0x1048; +_PWMEVTEbits = 0x1048; + PWMEVTF = 0x104C; +_PWMEVTF = 0x104C; +_PWMEVTFbits = 0x104C; + PG1CON = 0x1050; +_PG1CON = 0x1050; +_PG1CONbits = 0x1050; + PG1STAT = 0x1054; +_PG1STAT = 0x1054; +_PG1STATbits = 0x1054; + PG1IOCON1 = 0x1058; +_PG1IOCON1 = 0x1058; +_PG1IOCON1bits = 0x1058; + PG1IOCON2 = 0x105C; +_PG1IOCON2 = 0x105C; +_PG1IOCON2bits = 0x105C; + PG1EVT1 = 0x1060; +_PG1EVT1 = 0x1060; +_PG1EVT1bits = 0x1060; + PG1EVT2 = 0x1064; +_PG1EVT2 = 0x1064; +_PG1EVT2bits = 0x1064; + PG1F1PCI1 = 0x1068; +_PG1F1PCI1 = 0x1068; +_PG1F1PCI1bits = 0x1068; + PG1F1PCI2 = 0x106C; +_PG1F1PCI2 = 0x106C; + PG1F2PCI1 = 0x1070; +_PG1F2PCI1 = 0x1070; +_PG1F2PCI1bits = 0x1070; + PG1F2PCI2 = 0x1074; +_PG1F2PCI2 = 0x1074; + PG1CLPCI1 = 0x1078; +_PG1CLPCI1 = 0x1078; +_PG1CLPCI1bits = 0x1078; + PG1CLPCI2 = 0x107C; +_PG1CLPCI2 = 0x107C; + PG1FFPCI1 = 0x1080; +_PG1FFPCI1 = 0x1080; +_PG1FFPCI1bits = 0x1080; + PG1FFPCI2 = 0x1084; +_PG1FFPCI2 = 0x1084; + PG1SPCI1 = 0x1088; +_PG1SPCI1 = 0x1088; +_PG1SPCI1bits = 0x1088; + PG1SPCI2 = 0x108C; +_PG1SPCI2 = 0x108C; + PG1LEB = 0x1090; +_PG1LEB = 0x1090; +_PG1LEBbits = 0x1090; + PG1PHASE = 0x1094; +_PG1PHASE = 0x1094; +_PG1PHASEbits = 0x1094; + PG1DC = 0x1098; +_PG1DC = 0x1098; +_PG1DCbits = 0x1098; + PG1DCA = 0x109C; +_PG1DCA = 0x109C; +_PG1DCAbits = 0x109C; + PG1PER = 0x10A0; +_PG1PER = 0x10A0; +_PG1PERbits = 0x10A0; + PG1TRIGA = 0x10A4; +_PG1TRIGA = 0x10A4; +_PG1TRIGAbits = 0x10A4; + PG1TRIGB = 0x10A8; +_PG1TRIGB = 0x10A8; +_PG1TRIGBbits = 0x10A8; + PG1TRIGC = 0x10AC; +_PG1TRIGC = 0x10AC; +_PG1TRIGCbits = 0x10AC; + PG1TRIGD = 0x10B0; +_PG1TRIGD = 0x10B0; +_PG1TRIGDbits = 0x10B0; + PG1TRIGE = 0x10B4; +_PG1TRIGE = 0x10B4; +_PG1TRIGEbits = 0x10B4; + PG1TRIGF = 0x10B8; +_PG1TRIGF = 0x10B8; +_PG1TRIGFbits = 0x10B8; + PG1DT = 0x10BC; +_PG1DT = 0x10BC; +_PG1DTbits = 0x10BC; + PG1CAP = 0x10C0; +_PG1CAP = 0x10C0; +_PG1CAPbits = 0x10C0; + PG2CON = 0x10C4; +_PG2CON = 0x10C4; +_PG2CONbits = 0x10C4; + PG2STAT = 0x10C8; +_PG2STAT = 0x10C8; +_PG2STATbits = 0x10C8; + PG2IOCON1 = 0x10CC; +_PG2IOCON1 = 0x10CC; +_PG2IOCON1bits = 0x10CC; + PG2IOCON2 = 0x10D0; +_PG2IOCON2 = 0x10D0; +_PG2IOCON2bits = 0x10D0; + PG2EVT1 = 0x10D4; +_PG2EVT1 = 0x10D4; +_PG2EVT1bits = 0x10D4; + PG2EVT2 = 0x10D8; +_PG2EVT2 = 0x10D8; +_PG2EVT2bits = 0x10D8; + PG2F1PCI1 = 0x10DC; +_PG2F1PCI1 = 0x10DC; +_PG2F1PCI1bits = 0x10DC; + PG2F1PCI2 = 0x10E0; +_PG2F1PCI2 = 0x10E0; + PG2F2PCI1 = 0x10E4; +_PG2F2PCI1 = 0x10E4; +_PG2F2PCI1bits = 0x10E4; + PG2F2PCI2 = 0x10E8; +_PG2F2PCI2 = 0x10E8; + PG2CLPCI1 = 0x10EC; +_PG2CLPCI1 = 0x10EC; +_PG2CLPCI1bits = 0x10EC; + PG2CLPCI2 = 0x10F0; +_PG2CLPCI2 = 0x10F0; + PG2FFPCI1 = 0x10F4; +_PG2FFPCI1 = 0x10F4; +_PG2FFPCI1bits = 0x10F4; + PG2FFPCI2 = 0x10F8; +_PG2FFPCI2 = 0x10F8; + PG2SPCI1 = 0x10FC; +_PG2SPCI1 = 0x10FC; +_PG2SPCI1bits = 0x10FC; + PG2SPCI2 = 0x1100; +_PG2SPCI2 = 0x1100; + PG2LEB = 0x1104; +_PG2LEB = 0x1104; +_PG2LEBbits = 0x1104; + PG2PHASE = 0x1108; +_PG2PHASE = 0x1108; +_PG2PHASEbits = 0x1108; + PG2DC = 0x110C; +_PG2DC = 0x110C; +_PG2DCbits = 0x110C; + PG2DCA = 0x1110; +_PG2DCA = 0x1110; +_PG2DCAbits = 0x1110; + PG2PER = 0x1114; +_PG2PER = 0x1114; +_PG2PERbits = 0x1114; + PG2TRIGA = 0x1118; +_PG2TRIGA = 0x1118; +_PG2TRIGAbits = 0x1118; + PG2TRIGB = 0x111C; +_PG2TRIGB = 0x111C; +_PG2TRIGBbits = 0x111C; + PG2TRIGC = 0x1120; +_PG2TRIGC = 0x1120; +_PG2TRIGCbits = 0x1120; + PG2TRIGD = 0x1124; +_PG2TRIGD = 0x1124; +_PG2TRIGDbits = 0x1124; + PG2TRIGE = 0x1128; +_PG2TRIGE = 0x1128; +_PG2TRIGEbits = 0x1128; + PG2TRIGF = 0x112C; +_PG2TRIGF = 0x112C; +_PG2TRIGFbits = 0x112C; + PG2DT = 0x1130; +_PG2DT = 0x1130; +_PG2DTbits = 0x1130; + PG2CAP = 0x1134; +_PG2CAP = 0x1134; +_PG2CAPbits = 0x1134; + PG3CON = 0x1138; +_PG3CON = 0x1138; +_PG3CONbits = 0x1138; + PG3STAT = 0x113C; +_PG3STAT = 0x113C; +_PG3STATbits = 0x113C; + PG3IOCON1 = 0x1140; +_PG3IOCON1 = 0x1140; +_PG3IOCON1bits = 0x1140; + PG3IOCON2 = 0x1144; +_PG3IOCON2 = 0x1144; +_PG3IOCON2bits = 0x1144; + PG3EVT1 = 0x1148; +_PG3EVT1 = 0x1148; +_PG3EVT1bits = 0x1148; + PG3EVT2 = 0x114C; +_PG3EVT2 = 0x114C; +_PG3EVT2bits = 0x114C; + PG3F1PCI1 = 0x1150; +_PG3F1PCI1 = 0x1150; +_PG3F1PCI1bits = 0x1150; + PG3F1PCI2 = 0x1154; +_PG3F1PCI2 = 0x1154; + PG3F2PCI1 = 0x1158; +_PG3F2PCI1 = 0x1158; +_PG3F2PCI1bits = 0x1158; + PG3F2PCI2 = 0x115C; +_PG3F2PCI2 = 0x115C; + PG3CLPCI1 = 0x1160; +_PG3CLPCI1 = 0x1160; +_PG3CLPCI1bits = 0x1160; + PG3CLPCI2 = 0x1164; +_PG3CLPCI2 = 0x1164; + PG3FFPCI1 = 0x1168; +_PG3FFPCI1 = 0x1168; +_PG3FFPCI1bits = 0x1168; + PG3FFPCI2 = 0x116C; +_PG3FFPCI2 = 0x116C; + PG3SPCI1 = 0x1170; +_PG3SPCI1 = 0x1170; +_PG3SPCI1bits = 0x1170; + PG3SPCI2 = 0x1174; +_PG3SPCI2 = 0x1174; + PG3LEB = 0x1178; +_PG3LEB = 0x1178; +_PG3LEBbits = 0x1178; + PG3PHASE = 0x117C; +_PG3PHASE = 0x117C; +_PG3PHASEbits = 0x117C; + PG3DC = 0x1180; +_PG3DC = 0x1180; +_PG3DCbits = 0x1180; + PG3DCA = 0x1184; +_PG3DCA = 0x1184; +_PG3DCAbits = 0x1184; + PG3PER = 0x1188; +_PG3PER = 0x1188; +_PG3PERbits = 0x1188; + PG3TRIGA = 0x118C; +_PG3TRIGA = 0x118C; +_PG3TRIGAbits = 0x118C; + PG3TRIGB = 0x1190; +_PG3TRIGB = 0x1190; +_PG3TRIGBbits = 0x1190; + PG3TRIGC = 0x1194; +_PG3TRIGC = 0x1194; +_PG3TRIGCbits = 0x1194; + PG3TRIGD = 0x1198; +_PG3TRIGD = 0x1198; +_PG3TRIGDbits = 0x1198; + PG3TRIGE = 0x119C; +_PG3TRIGE = 0x119C; +_PG3TRIGEbits = 0x119C; + PG3TRIGF = 0x11A0; +_PG3TRIGF = 0x11A0; +_PG3TRIGFbits = 0x11A0; + PG3DT = 0x11A4; +_PG3DT = 0x11A4; +_PG3DTbits = 0x11A4; + PG3CAP = 0x11A8; +_PG3CAP = 0x11A8; +_PG3CAPbits = 0x11A8; + PG4CON = 0x11AC; +_PG4CON = 0x11AC; +_PG4CONbits = 0x11AC; + PG4STAT = 0x11B0; +_PG4STAT = 0x11B0; +_PG4STATbits = 0x11B0; + PG4IOCON1 = 0x11B4; +_PG4IOCON1 = 0x11B4; +_PG4IOCON1bits = 0x11B4; + PG4IOCON2 = 0x11B8; +_PG4IOCON2 = 0x11B8; +_PG4IOCON2bits = 0x11B8; + PG4EVT1 = 0x11BC; +_PG4EVT1 = 0x11BC; +_PG4EVT1bits = 0x11BC; + PG4EVT2 = 0x11C0; +_PG4EVT2 = 0x11C0; +_PG4EVT2bits = 0x11C0; + PG4F1PCI1 = 0x11C4; +_PG4F1PCI1 = 0x11C4; +_PG4F1PCI1bits = 0x11C4; + PG4F1PCI2 = 0x11C8; +_PG4F1PCI2 = 0x11C8; + PG4F2PCI1 = 0x11CC; +_PG4F2PCI1 = 0x11CC; +_PG4F2PCI1bits = 0x11CC; + PG4F2PCI2 = 0x11D0; +_PG4F2PCI2 = 0x11D0; + PG4CLPCI1 = 0x11D4; +_PG4CLPCI1 = 0x11D4; +_PG4CLPCI1bits = 0x11D4; + PG4CLPCI2 = 0x11D8; +_PG4CLPCI2 = 0x11D8; + PG4FFPCI1 = 0x11DC; +_PG4FFPCI1 = 0x11DC; +_PG4FFPCI1bits = 0x11DC; + PG4FFPCI2 = 0x11E0; +_PG4FFPCI2 = 0x11E0; + PG4SPCI1 = 0x11E4; +_PG4SPCI1 = 0x11E4; +_PG4SPCI1bits = 0x11E4; + PG4SPCI2 = 0x11E8; +_PG4SPCI2 = 0x11E8; + PG4LEB = 0x11EC; +_PG4LEB = 0x11EC; +_PG4LEBbits = 0x11EC; + PG4PHASE = 0x11F0; +_PG4PHASE = 0x11F0; +_PG4PHASEbits = 0x11F0; + PG4DC = 0x11F4; +_PG4DC = 0x11F4; +_PG4DCbits = 0x11F4; + PG4DCA = 0x11F8; +_PG4DCA = 0x11F8; +_PG4DCAbits = 0x11F8; + PG4PER = 0x11FC; +_PG4PER = 0x11FC; +_PG4PERbits = 0x11FC; + PG4TRIGA = 0x1200; +_PG4TRIGA = 0x1200; +_PG4TRIGAbits = 0x1200; + PG4TRIGB = 0x1204; +_PG4TRIGB = 0x1204; +_PG4TRIGBbits = 0x1204; + PG4TRIGC = 0x1208; +_PG4TRIGC = 0x1208; +_PG4TRIGCbits = 0x1208; + PG4TRIGD = 0x120C; +_PG4TRIGD = 0x120C; +_PG4TRIGDbits = 0x120C; + PG4TRIGE = 0x1210; +_PG4TRIGE = 0x1210; +_PG4TRIGEbits = 0x1210; + PG4TRIGF = 0x1214; +_PG4TRIGF = 0x1214; +_PG4TRIGFbits = 0x1214; + PG4DT = 0x1218; +_PG4DT = 0x1218; +_PG4DTbits = 0x1218; + PG4CAP = 0x121C; +_PG4CAP = 0x121C; +_PG4CAPbits = 0x121C; + PG5CON = 0x1220; +_PG5CON = 0x1220; +_PG5CONbits = 0x1220; + PG5STAT = 0x1224; +_PG5STAT = 0x1224; +_PG5STATbits = 0x1224; + PG5IOCON1 = 0x1228; +_PG5IOCON1 = 0x1228; +_PG5IOCON1bits = 0x1228; + PG5IOCON2 = 0x122C; +_PG5IOCON2 = 0x122C; +_PG5IOCON2bits = 0x122C; + PG5EVT1 = 0x1230; +_PG5EVT1 = 0x1230; +_PG5EVT1bits = 0x1230; + PG5EVT2 = 0x1234; +_PG5EVT2 = 0x1234; +_PG5EVT2bits = 0x1234; + PG5F1PCI1 = 0x1238; +_PG5F1PCI1 = 0x1238; +_PG5F1PCI1bits = 0x1238; + PG5F1PCI2 = 0x123C; +_PG5F1PCI2 = 0x123C; + PG5F2PCI1 = 0x1240; +_PG5F2PCI1 = 0x1240; +_PG5F2PCI1bits = 0x1240; + PG5F2PCI2 = 0x1244; +_PG5F2PCI2 = 0x1244; + PG5CLPCI1 = 0x1248; +_PG5CLPCI1 = 0x1248; +_PG5CLPCI1bits = 0x1248; + PG5CLPCI2 = 0x124C; +_PG5CLPCI2 = 0x124C; + PG5FFPCI1 = 0x1250; +_PG5FFPCI1 = 0x1250; +_PG5FFPCI1bits = 0x1250; + PG5FFPCI2 = 0x1254; +_PG5FFPCI2 = 0x1254; + PG5SPCI1 = 0x1258; +_PG5SPCI1 = 0x1258; +_PG5SPCI1bits = 0x1258; + PG5SPCI2 = 0x125C; +_PG5SPCI2 = 0x125C; + PG5LEB = 0x1260; +_PG5LEB = 0x1260; +_PG5LEBbits = 0x1260; + PG5PHASE = 0x1264; +_PG5PHASE = 0x1264; +_PG5PHASEbits = 0x1264; + PG5DC = 0x1268; +_PG5DC = 0x1268; +_PG5DCbits = 0x1268; + PG5DCA = 0x126C; +_PG5DCA = 0x126C; +_PG5DCAbits = 0x126C; + PG5PER = 0x1270; +_PG5PER = 0x1270; +_PG5PERbits = 0x1270; + PG5TRIGA = 0x1274; +_PG5TRIGA = 0x1274; +_PG5TRIGAbits = 0x1274; + PG5TRIGB = 0x1278; +_PG5TRIGB = 0x1278; +_PG5TRIGBbits = 0x1278; + PG5TRIGC = 0x127C; +_PG5TRIGC = 0x127C; +_PG5TRIGCbits = 0x127C; + PG5TRIGD = 0x1280; +_PG5TRIGD = 0x1280; +_PG5TRIGDbits = 0x1280; + PG5TRIGE = 0x1284; +_PG5TRIGE = 0x1284; +_PG5TRIGEbits = 0x1284; + PG5TRIGF = 0x1288; +_PG5TRIGF = 0x1288; +_PG5TRIGFbits = 0x1288; + PG5DT = 0x128C; +_PG5DT = 0x128C; +_PG5DTbits = 0x128C; + PG5CAP = 0x1290; +_PG5CAP = 0x1290; +_PG5CAPbits = 0x1290; + PG6CON = 0x1294; +_PG6CON = 0x1294; +_PG6CONbits = 0x1294; + PG6STAT = 0x1298; +_PG6STAT = 0x1298; +_PG6STATbits = 0x1298; + PG6IOCON1 = 0x129C; +_PG6IOCON1 = 0x129C; +_PG6IOCON1bits = 0x129C; + PG6IOCON2 = 0x12A0; +_PG6IOCON2 = 0x12A0; +_PG6IOCON2bits = 0x12A0; + PG6EVT1 = 0x12A4; +_PG6EVT1 = 0x12A4; +_PG6EVT1bits = 0x12A4; + PG6EVT2 = 0x12A8; +_PG6EVT2 = 0x12A8; +_PG6EVT2bits = 0x12A8; + PG6F1PCI1 = 0x12AC; +_PG6F1PCI1 = 0x12AC; +_PG6F1PCI1bits = 0x12AC; + PG6F1PCI2 = 0x12B0; +_PG6F1PCI2 = 0x12B0; + PG6F2PCI1 = 0x12B4; +_PG6F2PCI1 = 0x12B4; +_PG6F2PCI1bits = 0x12B4; + PG6F2PCI2 = 0x12B8; +_PG6F2PCI2 = 0x12B8; + PG6CLPCI1 = 0x12BC; +_PG6CLPCI1 = 0x12BC; +_PG6CLPCI1bits = 0x12BC; + PG6CLPCI2 = 0x12C0; +_PG6CLPCI2 = 0x12C0; + PG6FFPCI1 = 0x12C4; +_PG6FFPCI1 = 0x12C4; +_PG6FFPCI1bits = 0x12C4; + PG6FFPCI2 = 0x12C8; +_PG6FFPCI2 = 0x12C8; + PG6SPCI1 = 0x12CC; +_PG6SPCI1 = 0x12CC; +_PG6SPCI1bits = 0x12CC; + PG6SPCI2 = 0x12D0; +_PG6SPCI2 = 0x12D0; + PG6LEB = 0x12D4; +_PG6LEB = 0x12D4; +_PG6LEBbits = 0x12D4; + PG6PHASE = 0x12D8; +_PG6PHASE = 0x12D8; +_PG6PHASEbits = 0x12D8; + PG6DC = 0x12DC; +_PG6DC = 0x12DC; +_PG6DCbits = 0x12DC; + PG6DCA = 0x12E0; +_PG6DCA = 0x12E0; +_PG6DCAbits = 0x12E0; + PG6PER = 0x12E4; +_PG6PER = 0x12E4; +_PG6PERbits = 0x12E4; + PG6TRIGA = 0x12E8; +_PG6TRIGA = 0x12E8; +_PG6TRIGAbits = 0x12E8; + PG6TRIGB = 0x12EC; +_PG6TRIGB = 0x12EC; +_PG6TRIGBbits = 0x12EC; + PG6TRIGC = 0x12F0; +_PG6TRIGC = 0x12F0; +_PG6TRIGCbits = 0x12F0; + PG6TRIGD = 0x12F4; +_PG6TRIGD = 0x12F4; +_PG6TRIGDbits = 0x12F4; + PG6TRIGE = 0x12F8; +_PG6TRIGE = 0x12F8; +_PG6TRIGEbits = 0x12F8; + PG6TRIGF = 0x12FC; +_PG6TRIGF = 0x12FC; +_PG6TRIGFbits = 0x12FC; + PG6DT = 0x1300; +_PG6DT = 0x1300; +_PG6DTbits = 0x1300; + PG6CAP = 0x1304; +_PG6CAP = 0x1304; +_PG6CAPbits = 0x1304; + PG7CON = 0x1308; +_PG7CON = 0x1308; +_PG7CONbits = 0x1308; + PG7STAT = 0x130C; +_PG7STAT = 0x130C; +_PG7STATbits = 0x130C; + PG7IOCON1 = 0x1310; +_PG7IOCON1 = 0x1310; +_PG7IOCON1bits = 0x1310; + PG7IOCON2 = 0x1314; +_PG7IOCON2 = 0x1314; +_PG7IOCON2bits = 0x1314; + PG7EVT1 = 0x1318; +_PG7EVT1 = 0x1318; +_PG7EVT1bits = 0x1318; + PG7EVT2 = 0x131C; +_PG7EVT2 = 0x131C; +_PG7EVT2bits = 0x131C; + PG7F1PCI1 = 0x1320; +_PG7F1PCI1 = 0x1320; +_PG7F1PCI1bits = 0x1320; + PG7F1PCI2 = 0x1324; +_PG7F1PCI2 = 0x1324; + PG7F2PCI1 = 0x1328; +_PG7F2PCI1 = 0x1328; +_PG7F2PCI1bits = 0x1328; + PG7F2PCI2 = 0x132C; +_PG7F2PCI2 = 0x132C; + PG7CLPCI1 = 0x1330; +_PG7CLPCI1 = 0x1330; +_PG7CLPCI1bits = 0x1330; + PG7CLPCI2 = 0x1334; +_PG7CLPCI2 = 0x1334; + PG7FFPCI1 = 0x1338; +_PG7FFPCI1 = 0x1338; +_PG7FFPCI1bits = 0x1338; + PG7FFPCI2 = 0x133C; +_PG7FFPCI2 = 0x133C; + PG7SPCI1 = 0x1340; +_PG7SPCI1 = 0x1340; +_PG7SPCI1bits = 0x1340; + PG7SPCI2 = 0x1344; +_PG7SPCI2 = 0x1344; + PG7LEB = 0x1348; +_PG7LEB = 0x1348; +_PG7LEBbits = 0x1348; + PG7PHASE = 0x134C; +_PG7PHASE = 0x134C; +_PG7PHASEbits = 0x134C; + PG7DC = 0x1350; +_PG7DC = 0x1350; +_PG7DCbits = 0x1350; + PG7DCA = 0x1354; +_PG7DCA = 0x1354; +_PG7DCAbits = 0x1354; + PG7PER = 0x1358; +_PG7PER = 0x1358; +_PG7PERbits = 0x1358; + PG7TRIGA = 0x135C; +_PG7TRIGA = 0x135C; +_PG7TRIGAbits = 0x135C; + PG7TRIGB = 0x1360; +_PG7TRIGB = 0x1360; +_PG7TRIGBbits = 0x1360; + PG7TRIGC = 0x1364; +_PG7TRIGC = 0x1364; +_PG7TRIGCbits = 0x1364; + PG7TRIGD = 0x1368; +_PG7TRIGD = 0x1368; +_PG7TRIGDbits = 0x1368; + PG7TRIGE = 0x136C; +_PG7TRIGE = 0x136C; +_PG7TRIGEbits = 0x136C; + PG7TRIGF = 0x1370; +_PG7TRIGF = 0x1370; +_PG7TRIGFbits = 0x1370; + PG7DT = 0x1374; +_PG7DT = 0x1374; +_PG7DTbits = 0x1374; + PG7CAP = 0x1378; +_PG7CAP = 0x1378; +_PG7CAPbits = 0x1378; + PG8CON = 0x137C; +_PG8CON = 0x137C; +_PG8CONbits = 0x137C; + PG8STAT = 0x1380; +_PG8STAT = 0x1380; +_PG8STATbits = 0x1380; + PG8IOCON1 = 0x1384; +_PG8IOCON1 = 0x1384; +_PG8IOCON1bits = 0x1384; + PG8IOCON2 = 0x1388; +_PG8IOCON2 = 0x1388; +_PG8IOCON2bits = 0x1388; + PG8EVT1 = 0x138C; +_PG8EVT1 = 0x138C; +_PG8EVT1bits = 0x138C; + PG8EVT2 = 0x1390; +_PG8EVT2 = 0x1390; +_PG8EVT2bits = 0x1390; + PG8F1PCI1 = 0x1394; +_PG8F1PCI1 = 0x1394; +_PG8F1PCI1bits = 0x1394; + PG8F1PCI2 = 0x1398; +_PG8F1PCI2 = 0x1398; + PG8F2PCI1 = 0x139C; +_PG8F2PCI1 = 0x139C; +_PG8F2PCI1bits = 0x139C; + PG8F2PCI2 = 0x13A0; +_PG8F2PCI2 = 0x13A0; + PG8CLPCI1 = 0x13A4; +_PG8CLPCI1 = 0x13A4; +_PG8CLPCI1bits = 0x13A4; + PG8CLPCI2 = 0x13A8; +_PG8CLPCI2 = 0x13A8; + PG8FFPCI1 = 0x13AC; +_PG8FFPCI1 = 0x13AC; +_PG8FFPCI1bits = 0x13AC; + PG8FFPCI2 = 0x13B0; +_PG8FFPCI2 = 0x13B0; + PG8SPCI1 = 0x13B4; +_PG8SPCI1 = 0x13B4; +_PG8SPCI1bits = 0x13B4; + PG8SPCI2 = 0x13B8; +_PG8SPCI2 = 0x13B8; + PG8LEB = 0x13BC; +_PG8LEB = 0x13BC; +_PG8LEBbits = 0x13BC; + PG8PHASE = 0x13C0; +_PG8PHASE = 0x13C0; +_PG8PHASEbits = 0x13C0; + PG8DC = 0x13C4; +_PG8DC = 0x13C4; +_PG8DCbits = 0x13C4; + PG8DCA = 0x13C8; +_PG8DCA = 0x13C8; +_PG8DCAbits = 0x13C8; + PG8PER = 0x13CC; +_PG8PER = 0x13CC; +_PG8PERbits = 0x13CC; + PG8TRIGA = 0x13D0; +_PG8TRIGA = 0x13D0; +_PG8TRIGAbits = 0x13D0; + PG8TRIGB = 0x13D4; +_PG8TRIGB = 0x13D4; +_PG8TRIGBbits = 0x13D4; + PG8TRIGC = 0x13D8; +_PG8TRIGC = 0x13D8; +_PG8TRIGCbits = 0x13D8; + PG8TRIGD = 0x13DC; +_PG8TRIGD = 0x13DC; +_PG8TRIGDbits = 0x13DC; + PG8TRIGE = 0x13E0; +_PG8TRIGE = 0x13E0; +_PG8TRIGEbits = 0x13E0; + PG8TRIGF = 0x13E4; +_PG8TRIGF = 0x13E4; +_PG8TRIGFbits = 0x13E4; + PG8DT = 0x13E8; +_PG8DT = 0x13E8; +_PG8DTbits = 0x13E8; + PG8CAP = 0x13EC; +_PG8CAP = 0x13EC; +_PG8CAPbits = 0x13EC; + APCLKCON = 0x1400; +_APCLKCON = 0x1400; +_APCLKCONbits = 0x1400; + AFSCL = 0x1404; +_AFSCL = 0x1404; +_AFSCLbits = 0x1404; + AFSMINPER = 0x1408; +_AFSMINPER = 0x1408; +_AFSMINPERbits = 0x1408; + AMPHASE = 0x140C; +_AMPHASE = 0x140C; +_AMPHASEbits = 0x140C; + AMDC = 0x1410; +_AMDC = 0x1410; +_AMDCbits = 0x1410; + AMPER = 0x1414; +_AMPER = 0x1414; +_AMPERbits = 0x1414; + ALFSR = 0x1418; +_ALFSR = 0x1418; +_ALFSRbits = 0x1418; + ACMBTRIG = 0x141C; +_ACMBTRIG = 0x141C; +_ACMBTRIGbits = 0x141C; + ALOGCONA = 0x1420; +_ALOGCONA = 0x1420; +_ALOGCONAbits = 0x1420; + ALOGCONB = 0x1424; +_ALOGCONB = 0x1424; +_ALOGCONBbits = 0x1424; + APWMEVTA = 0x1428; +_APWMEVTA = 0x1428; +_APWMEVTAbits = 0x1428; + APWMEVTB = 0x142C; +_APWMEVTB = 0x142C; +_APWMEVTBbits = 0x142C; + APWMEVTC = 0x1430; +_APWMEVTC = 0x1430; +_APWMEVTCbits = 0x1430; + APWMEVTD = 0x1434; +_APWMEVTD = 0x1434; +_APWMEVTDbits = 0x1434; + APG1CON = 0x1438; +_APG1CON = 0x1438; +_APG1CONbits = 0x1438; + APG1STAT = 0x143C; +_APG1STAT = 0x143C; +_APG1STATbits = 0x143C; + APG1IOCON1 = 0x1440; +_APG1IOCON1 = 0x1440; +_APG1IOCON1bits = 0x1440; + APG1IOCON2 = 0x1444; +_APG1IOCON2 = 0x1444; +_APG1IOCON2bits = 0x1444; + APG1EVT1 = 0x1448; +_APG1EVT1 = 0x1448; +_APG1EVT1bits = 0x1448; + APG1EVT2 = 0x144C; +_APG1EVT2 = 0x144C; +_APG1EVT2bits = 0x144C; + APG1F1PCI1 = 0x1450; +_APG1F1PCI1 = 0x1450; +_APG1F1PCI1bits = 0x1450; + APG1F1PCI2 = 0x1454; +_APG1F1PCI2 = 0x1454; + APG1F2PCI1 = 0x1458; +_APG1F2PCI1 = 0x1458; +_APG1F2PCI1bits = 0x1458; + APG1F2PCI2 = 0x145C; +_APG1F2PCI2 = 0x145C; + APG1CLPCI1 = 0x1460; +_APG1CLPCI1 = 0x1460; +_APG1CLPCI1bits = 0x1460; + APG1CLPCI2 = 0x1464; +_APG1CLPCI2 = 0x1464; + APG1FFPCI1 = 0x1468; +_APG1FFPCI1 = 0x1468; +_APG1FFPCI1bits = 0x1468; + APG1FFPCI2 = 0x146C; +_APG1FFPCI2 = 0x146C; + APG1SPCI1 = 0x1470; +_APG1SPCI1 = 0x1470; +_APG1SPCI1bits = 0x1470; + APG1SPCI2 = 0x1474; +_APG1SPCI2 = 0x1474; + APG1LEB = 0x1478; +_APG1LEB = 0x1478; +_APG1LEBbits = 0x1478; + APG1PHASE = 0x147C; +_APG1PHASE = 0x147C; +_APG1PHASEbits = 0x147C; + APG1DC = 0x1480; +_APG1DC = 0x1480; +_APG1DCbits = 0x1480; + APG1DCA = 0x1484; +_APG1DCA = 0x1484; +_APG1DCAbits = 0x1484; + APG1PER = 0x1488; +_APG1PER = 0x1488; +_APG1PERbits = 0x1488; + APG1TRIGA = 0x148C; +_APG1TRIGA = 0x148C; +_APG1TRIGAbits = 0x148C; + APG1TRIGB = 0x1490; +_APG1TRIGB = 0x1490; +_APG1TRIGBbits = 0x1490; + APG1TRIGC = 0x1494; +_APG1TRIGC = 0x1494; +_APG1TRIGCbits = 0x1494; + APG1TRIGD = 0x1498; +_APG1TRIGD = 0x1498; +_APG1TRIGDbits = 0x1498; + APG1TRIGE = 0x149C; +_APG1TRIGE = 0x149C; +_APG1TRIGEbits = 0x149C; + APG1TRIGF = 0x14A0; +_APG1TRIGF = 0x14A0; +_APG1TRIGFbits = 0x14A0; + APG1DT = 0x14A4; +_APG1DT = 0x14A4; +_APG1DTbits = 0x14A4; + APG1CAP = 0x14A8; +_APG1CAP = 0x14A8; +_APG1CAPbits = 0x14A8; + APG2CON = 0x14AC; +_APG2CON = 0x14AC; +_APG2CONbits = 0x14AC; + APG2STAT = 0x14B0; +_APG2STAT = 0x14B0; +_APG2STATbits = 0x14B0; + APG2IOCON1 = 0x14B4; +_APG2IOCON1 = 0x14B4; +_APG2IOCON1bits = 0x14B4; + APG2IOCON2 = 0x14B8; +_APG2IOCON2 = 0x14B8; +_APG2IOCON2bits = 0x14B8; + APG2EVT1 = 0x14BC; +_APG2EVT1 = 0x14BC; +_APG2EVT1bits = 0x14BC; + APG2EVT2 = 0x14C0; +_APG2EVT2 = 0x14C0; +_APG2EVT2bits = 0x14C0; + APG2F1PCI1 = 0x14C4; +_APG2F1PCI1 = 0x14C4; +_APG2F1PCI1bits = 0x14C4; + APG2F1PCI2 = 0x14C8; +_APG2F1PCI2 = 0x14C8; + APG2F2PCI1 = 0x14CC; +_APG2F2PCI1 = 0x14CC; +_APG2F2PCI1bits = 0x14CC; + APG2F2PCI2 = 0x14D0; +_APG2F2PCI2 = 0x14D0; + APG2CLPCI1 = 0x14D4; +_APG2CLPCI1 = 0x14D4; +_APG2CLPCI1bits = 0x14D4; + APG2CLPCI2 = 0x14D8; +_APG2CLPCI2 = 0x14D8; + APG2FFPCI1 = 0x14DC; +_APG2FFPCI1 = 0x14DC; +_APG2FFPCI1bits = 0x14DC; + APG2FFPCI2 = 0x14E0; +_APG2FFPCI2 = 0x14E0; + APG2SPCI1 = 0x14E4; +_APG2SPCI1 = 0x14E4; +_APG2SPCI1bits = 0x14E4; + APG2SPCI2 = 0x14E8; +_APG2SPCI2 = 0x14E8; + APG2LEB = 0x14EC; +_APG2LEB = 0x14EC; +_APG2LEBbits = 0x14EC; + APG2PHASE = 0x14F0; +_APG2PHASE = 0x14F0; +_APG2PHASEbits = 0x14F0; + APG2DC = 0x14F4; +_APG2DC = 0x14F4; +_APG2DCbits = 0x14F4; + APG2DCA = 0x14F8; +_APG2DCA = 0x14F8; +_APG2DCAbits = 0x14F8; + APG2PER = 0x14FC; +_APG2PER = 0x14FC; +_APG2PERbits = 0x14FC; + APG2TRIGA = 0x1500; +_APG2TRIGA = 0x1500; +_APG2TRIGAbits = 0x1500; + APG2TRIGB = 0x1504; +_APG2TRIGB = 0x1504; +_APG2TRIGBbits = 0x1504; + APG2TRIGC = 0x1508; +_APG2TRIGC = 0x1508; +_APG2TRIGCbits = 0x1508; + APG2TRIGD = 0x150C; +_APG2TRIGD = 0x150C; +_APG2TRIGDbits = 0x150C; + APG2TRIGE = 0x1510; +_APG2TRIGE = 0x1510; +_APG2TRIGEbits = 0x1510; + APG2TRIGF = 0x1514; +_APG2TRIGF = 0x1514; +_APG2TRIGFbits = 0x1514; + APG2DT = 0x1518; +_APG2DT = 0x1518; +_APG2DTbits = 0x1518; + APG2CAP = 0x151C; +_APG2CAP = 0x151C; +_APG2CAPbits = 0x151C; + APG3CON = 0x1520; +_APG3CON = 0x1520; +_APG3CONbits = 0x1520; + APG3STAT = 0x1524; +_APG3STAT = 0x1524; +_APG3STATbits = 0x1524; + APG3IOCON1 = 0x1528; +_APG3IOCON1 = 0x1528; +_APG3IOCON1bits = 0x1528; + APG3IOCON2 = 0x152C; +_APG3IOCON2 = 0x152C; +_APG3IOCON2bits = 0x152C; + APG3EVT1 = 0x1530; +_APG3EVT1 = 0x1530; +_APG3EVT1bits = 0x1530; + APG3EVT2 = 0x1534; +_APG3EVT2 = 0x1534; +_APG3EVT2bits = 0x1534; + APG3F1PCI1 = 0x1538; +_APG3F1PCI1 = 0x1538; +_APG3F1PCI1bits = 0x1538; + APG3F1PCI2 = 0x153C; +_APG3F1PCI2 = 0x153C; + APG3F2PCI1 = 0x1540; +_APG3F2PCI1 = 0x1540; +_APG3F2PCI1bits = 0x1540; + APG3F2PCI2 = 0x1544; +_APG3F2PCI2 = 0x1544; + APG3CLPCI1 = 0x1548; +_APG3CLPCI1 = 0x1548; +_APG3CLPCI1bits = 0x1548; + APG3CLPCI2 = 0x154C; +_APG3CLPCI2 = 0x154C; + APG3FFPCI1 = 0x1550; +_APG3FFPCI1 = 0x1550; +_APG3FFPCI1bits = 0x1550; + APG3FFPCI2 = 0x1554; +_APG3FFPCI2 = 0x1554; + APG3SPCI1 = 0x1558; +_APG3SPCI1 = 0x1558; +_APG3SPCI1bits = 0x1558; + APG3SPCI2 = 0x155C; +_APG3SPCI2 = 0x155C; + APG3LEB = 0x1560; +_APG3LEB = 0x1560; +_APG3LEBbits = 0x1560; + APG3PHASE = 0x1564; +_APG3PHASE = 0x1564; +_APG3PHASEbits = 0x1564; + APG3DC = 0x1568; +_APG3DC = 0x1568; +_APG3DCbits = 0x1568; + APG3DCA = 0x156C; +_APG3DCA = 0x156C; +_APG3DCAbits = 0x156C; + APG3PER = 0x1570; +_APG3PER = 0x1570; +_APG3PERbits = 0x1570; + APG3TRIGA = 0x1574; +_APG3TRIGA = 0x1574; +_APG3TRIGAbits = 0x1574; + APG3TRIGB = 0x1578; +_APG3TRIGB = 0x1578; +_APG3TRIGBbits = 0x1578; + APG3TRIGC = 0x157C; +_APG3TRIGC = 0x157C; +_APG3TRIGCbits = 0x157C; + APG3TRIGD = 0x1580; +_APG3TRIGD = 0x1580; +_APG3TRIGDbits = 0x1580; + APG3TRIGE = 0x1584; +_APG3TRIGE = 0x1584; +_APG3TRIGEbits = 0x1584; + APG3TRIGF = 0x1588; +_APG3TRIGF = 0x1588; +_APG3TRIGFbits = 0x1588; + APG3DT = 0x158C; +_APG3DT = 0x158C; +_APG3DTbits = 0x158C; + APG3CAP = 0x1590; +_APG3CAP = 0x1590; +_APG3CAPbits = 0x1590; + APG4CON = 0x1594; +_APG4CON = 0x1594; +_APG4CONbits = 0x1594; + APG4STAT = 0x1598; +_APG4STAT = 0x1598; +_APG4STATbits = 0x1598; + APG4IOCON1 = 0x159C; +_APG4IOCON1 = 0x159C; +_APG4IOCON1bits = 0x159C; + APG4IOCON2 = 0x15A0; +_APG4IOCON2 = 0x15A0; +_APG4IOCON2bits = 0x15A0; + APG4EVT1 = 0x15A4; +_APG4EVT1 = 0x15A4; +_APG4EVT1bits = 0x15A4; + APG4EVT2 = 0x15A8; +_APG4EVT2 = 0x15A8; +_APG4EVT2bits = 0x15A8; + APG4F1PCI1 = 0x15AC; +_APG4F1PCI1 = 0x15AC; +_APG4F1PCI1bits = 0x15AC; + APG4F1PCI2 = 0x15B0; +_APG4F1PCI2 = 0x15B0; + APG4F2PCI1 = 0x15B4; +_APG4F2PCI1 = 0x15B4; +_APG4F2PCI1bits = 0x15B4; + APG4F2PCI2 = 0x15B8; +_APG4F2PCI2 = 0x15B8; + APG4CLPCI1 = 0x15BC; +_APG4CLPCI1 = 0x15BC; +_APG4CLPCI1bits = 0x15BC; + APG4CLPCI2 = 0x15C0; +_APG4CLPCI2 = 0x15C0; + APG4FFPCI1 = 0x15C4; +_APG4FFPCI1 = 0x15C4; +_APG4FFPCI1bits = 0x15C4; + APG4FFPCI2 = 0x15C8; +_APG4FFPCI2 = 0x15C8; + APG4SPCI1 = 0x15CC; +_APG4SPCI1 = 0x15CC; +_APG4SPCI1bits = 0x15CC; + APG4SPCI2 = 0x15D0; +_APG4SPCI2 = 0x15D0; + APG4LEB = 0x15D4; +_APG4LEB = 0x15D4; +_APG4LEBbits = 0x15D4; + APG4PHASE = 0x15D8; +_APG4PHASE = 0x15D8; +_APG4PHASEbits = 0x15D8; + APG4DC = 0x15DC; +_APG4DC = 0x15DC; +_APG4DCbits = 0x15DC; + APG4DCA = 0x15E0; +_APG4DCA = 0x15E0; +_APG4DCAbits = 0x15E0; + APG4PER = 0x15E4; +_APG4PER = 0x15E4; +_APG4PERbits = 0x15E4; + APG4TRIGA = 0x15E8; +_APG4TRIGA = 0x15E8; +_APG4TRIGAbits = 0x15E8; + APG4TRIGB = 0x15EC; +_APG4TRIGB = 0x15EC; +_APG4TRIGBbits = 0x15EC; + APG4TRIGC = 0x15F0; +_APG4TRIGC = 0x15F0; +_APG4TRIGCbits = 0x15F0; + APG4TRIGD = 0x15F4; +_APG4TRIGD = 0x15F4; +_APG4TRIGDbits = 0x15F4; + APG4TRIGE = 0x15F8; +_APG4TRIGE = 0x15F8; +_APG4TRIGEbits = 0x15F8; + APG4TRIGF = 0x15FC; +_APG4TRIGF = 0x15FC; +_APG4TRIGFbits = 0x15FC; + APG4DT = 0x1600; +_APG4DT = 0x1600; +_APG4DTbits = 0x1600; + APG4CAP = 0x1604; +_APG4CAP = 0x1604; +_APG4CAPbits = 0x1604; + U1CON = 0x1700; +_U1CON = 0x1700; +_U1CONbits = 0x1700; + U1STAT = 0x1704; +_U1STAT = 0x1704; +_U1STATbits = 0x1704; + U1BRG = 0x1708; +_U1BRG = 0x1708; +_U1BRGbits = 0x1708; + U1RXB = 0x170C; +_U1RXB = 0x170C; +_U1RXBbits = 0x170C; + U1TXB = 0x1710; +_U1TXB = 0x1710; +_U1TXBbits = 0x1710; + U1PA = 0x1714; +_U1PA = 0x1714; +_U1PAbits = 0x1714; + U1PB = 0x1718; +_U1PB = 0x1718; +_U1PBbits = 0x1718; + U1CHK = 0x171C; +_U1CHK = 0x171C; +_U1CHKbits = 0x171C; + U1SCCON = 0x1720; +_U1SCCON = 0x1720; +_U1SCCONbits = 0x1720; + U1UIR = 0x1724; +_U1UIR = 0x1724; +_U1UIRbits = 0x1724; + U2CON = 0x1740; +_U2CON = 0x1740; +_U2CONbits = 0x1740; + U2STAT = 0x1744; +_U2STAT = 0x1744; +_U2STATbits = 0x1744; + U2BRG = 0x1748; +_U2BRG = 0x1748; +_U2BRGbits = 0x1748; + U2RXB = 0x174C; +_U2RXB = 0x174C; +_U2RXBbits = 0x174C; + U2TXB = 0x1750; +_U2TXB = 0x1750; +_U2TXBbits = 0x1750; + U2PA = 0x1754; +_U2PA = 0x1754; +_U2PAbits = 0x1754; + U2PB = 0x1758; +_U2PB = 0x1758; +_U2PBbits = 0x1758; + U2CHK = 0x175C; +_U2CHK = 0x175C; +_U2CHKbits = 0x175C; + U2SCCON = 0x1760; +_U2SCCON = 0x1760; +_U2SCCONbits = 0x1760; + U2UIR = 0x1764; +_U2UIR = 0x1764; +_U2UIRbits = 0x1764; + U3CON = 0x1780; +_U3CON = 0x1780; +_U3CONbits = 0x1780; + U3STAT = 0x1784; +_U3STAT = 0x1784; +_U3STATbits = 0x1784; + U3BRG = 0x1788; +_U3BRG = 0x1788; +_U3BRGbits = 0x1788; + U3RXB = 0x178C; +_U3RXB = 0x178C; +_U3RXBbits = 0x178C; + U3TXB = 0x1790; +_U3TXB = 0x1790; +_U3TXBbits = 0x1790; + U3PA = 0x1794; +_U3PA = 0x1794; +_U3PAbits = 0x1794; + U3PB = 0x1798; +_U3PB = 0x1798; +_U3PBbits = 0x1798; + U3CHK = 0x179C; +_U3CHK = 0x179C; +_U3CHKbits = 0x179C; + U3SCCON = 0x17A0; +_U3SCCON = 0x17A0; +_U3SCCONbits = 0x17A0; + U3UIR = 0x17A4; +_U3UIR = 0x17A4; +_U3UIRbits = 0x17A4; + SPI1CON1 = 0x1800; +_SPI1CON1 = 0x1800; +_SPI1CON1bits = 0x1800; + SPI1CON2 = 0x1804; +_SPI1CON2 = 0x1804; +_SPI1CON2bits = 0x1804; + SPI1STAT = 0x1808; +_SPI1STAT = 0x1808; +_SPI1STATbits = 0x1808; + SPI1BUF = 0x180C; +_SPI1BUF = 0x180C; + SPI1BRG = 0x1810; +_SPI1BRG = 0x1810; +_SPI1BRGbits = 0x1810; + SPI1IMSK = 0x1814; +_SPI1IMSK = 0x1814; +_SPI1IMSKbits = 0x1814; + SPI1URDT = 0x1818; +_SPI1URDT = 0x1818; + SPI2CON1 = 0x1820; +_SPI2CON1 = 0x1820; +_SPI2CON1bits = 0x1820; + SPI2CON2 = 0x1824; +_SPI2CON2 = 0x1824; +_SPI2CON2bits = 0x1824; + SPI2STAT = 0x1828; +_SPI2STAT = 0x1828; +_SPI2STATbits = 0x1828; + SPI2BUF = 0x182C; +_SPI2BUF = 0x182C; + SPI2BRG = 0x1830; +_SPI2BRG = 0x1830; +_SPI2BRGbits = 0x1830; + SPI2IMSK = 0x1834; +_SPI2IMSK = 0x1834; +_SPI2IMSKbits = 0x1834; + SPI2URDT = 0x1838; +_SPI2URDT = 0x1838; + SPI3CON1 = 0x1840; +_SPI3CON1 = 0x1840; +_SPI3CON1bits = 0x1840; + SPI3CON2 = 0x1844; +_SPI3CON2 = 0x1844; +_SPI3CON2bits = 0x1844; + SPI3STAT = 0x1848; +_SPI3STAT = 0x1848; +_SPI3STATbits = 0x1848; + SPI3BUF = 0x184C; +_SPI3BUF = 0x184C; + SPI3BRG = 0x1850; +_SPI3BRG = 0x1850; +_SPI3BRGbits = 0x1850; + SPI3IMSK = 0x1854; +_SPI3IMSK = 0x1854; +_SPI3IMSKbits = 0x1854; + SPI3URDT = 0x1858; +_SPI3URDT = 0x1858; + SPI4CON1 = 0x1860; +_SPI4CON1 = 0x1860; +_SPI4CON1bits = 0x1860; + SPI4CON2 = 0x1864; +_SPI4CON2 = 0x1864; +_SPI4CON2bits = 0x1864; + SPI4STAT = 0x1868; +_SPI4STAT = 0x1868; +_SPI4STATbits = 0x1868; + SPI4BUF = 0x186C; +_SPI4BUF = 0x186C; + SPI4BRG = 0x1870; +_SPI4BRG = 0x1870; +_SPI4BRGbits = 0x1870; + SPI4IMSK = 0x1874; +_SPI4IMSK = 0x1874; +_SPI4IMSKbits = 0x1874; + SPI4URDT = 0x1878; +_SPI4URDT = 0x1878; + I2C1CON1 = 0x1880; +_I2C1CON1 = 0x1880; +_I2C1CON1bits = 0x1880; + I2C1STAT1 = 0x1884; +_I2C1STAT1 = 0x1884; +_I2C1STAT1bits = 0x1884; + I2C1ADD = 0x1888; +_I2C1ADD = 0x1888; +_I2C1ADDbits = 0x1888; + I2C1MSK = 0x188C; +_I2C1MSK = 0x188C; +_I2C1MSKbits = 0x188C; + I2C1HBRG = 0x1890; +_I2C1HBRG = 0x1890; +_I2C1HBRGbits = 0x1890; + I2C1TRN = 0x1894; +_I2C1TRN = 0x1894; +_I2C1TRNbits = 0x1894; + I2C1RCV = 0x1898; +_I2C1RCV = 0x1898; +_I2C1RCVbits = 0x1898; + I2C1CON2 = 0x189C; +_I2C1CON2 = 0x189C; +_I2C1CON2bits = 0x189C; + I2C1LBRG = 0x18A0; +_I2C1LBRG = 0x18A0; +_I2C1LBRGbits = 0x18A0; + I2C1INTC = 0x18A4; +_I2C1INTC = 0x18A4; +_I2C1INTCbits = 0x18A4; + I2C1STAT2 = 0x18A8; +_I2C1STAT2 = 0x18A8; +_I2C1STAT2bits = 0x18A8; + I2C1PEC = 0x18AC; +_I2C1PEC = 0x18AC; +_I2C1PECbits = 0x18AC; + I2C1BTO = 0x18B0; +_I2C1BTO = 0x18B0; +_I2C1BTObits = 0x18B0; + I2C1HBCTO = 0x18B4; +_I2C1HBCTO = 0x18B4; +_I2C1HBCTObits = 0x18B4; + I2C1CBCTO = 0x18B8; +_I2C1CBCTO = 0x18B8; +_I2C1CBCTObits = 0x18B8; + I2C1BITO = 0x18BC; +_I2C1BITO = 0x18BC; +_I2C1BITObits = 0x18BC; + I2C1SDASUT = 0x18C0; +_I2C1SDASUT = 0x18C0; +_I2C1SDASUTbits = 0x18C0; + I2C1HDLYC = 0x18CC; +_I2C1HDLYC = 0x18CC; +_I2C1HDLYCbits = 0x18CC; + I2C2CON1 = 0x18D0; +_I2C2CON1 = 0x18D0; +_I2C2CON1bits = 0x18D0; + I2C2STAT1 = 0x18D4; +_I2C2STAT1 = 0x18D4; +_I2C2STAT1bits = 0x18D4; + I2C2ADD = 0x18D8; +_I2C2ADD = 0x18D8; +_I2C2ADDbits = 0x18D8; + I2C2MSK = 0x18DC; +_I2C2MSK = 0x18DC; +_I2C2MSKbits = 0x18DC; + I2C2HBRG = 0x18E0; +_I2C2HBRG = 0x18E0; +_I2C2HBRGbits = 0x18E0; + I2C2TRN = 0x18E4; +_I2C2TRN = 0x18E4; +_I2C2TRNbits = 0x18E4; + I2C2RCV = 0x18E8; +_I2C2RCV = 0x18E8; +_I2C2RCVbits = 0x18E8; + I2C2CON2 = 0x18EC; +_I2C2CON2 = 0x18EC; +_I2C2CON2bits = 0x18EC; + I2C2LBRG = 0x18F0; +_I2C2LBRG = 0x18F0; +_I2C2LBRGbits = 0x18F0; + I2C2INTC = 0x18F4; +_I2C2INTC = 0x18F4; +_I2C2INTCbits = 0x18F4; + I2C2STAT2 = 0x18F8; +_I2C2STAT2 = 0x18F8; +_I2C2STAT2bits = 0x18F8; + I2C2PEC = 0x18FC; +_I2C2PEC = 0x18FC; +_I2C2PECbits = 0x18FC; + I2C2BTO = 0x1900; +_I2C2BTO = 0x1900; +_I2C2BTObits = 0x1900; + I2C2HBCTO = 0x1904; +_I2C2HBCTO = 0x1904; +_I2C2HBCTObits = 0x1904; + I2C2CBCTO = 0x1908; +_I2C2CBCTO = 0x1908; +_I2C2CBCTObits = 0x1908; + I2C2BITO = 0x190C; +_I2C2BITO = 0x190C; +_I2C2BITObits = 0x190C; + I2C2SDASUT = 0x1910; +_I2C2SDASUT = 0x1910; +_I2C2SDASUTbits = 0x1910; + I2C2HDLYC = 0x191C; +_I2C2HDLYC = 0x191C; +_I2C2HDLYCbits = 0x191C; + I2C3CON1 = 0x1920; +_I2C3CON1 = 0x1920; +_I2C3CON1bits = 0x1920; + I2C3STAT1 = 0x1924; +_I2C3STAT1 = 0x1924; +_I2C3STAT1bits = 0x1924; + I2C3ADD = 0x1928; +_I2C3ADD = 0x1928; +_I2C3ADDbits = 0x1928; + I2C3MSK = 0x192C; +_I2C3MSK = 0x192C; +_I2C3MSKbits = 0x192C; + I2C3HBRG = 0x1930; +_I2C3HBRG = 0x1930; +_I2C3HBRGbits = 0x1930; + I2C3TRN = 0x1934; +_I2C3TRN = 0x1934; +_I2C3TRNbits = 0x1934; + I2C3RCV = 0x1938; +_I2C3RCV = 0x1938; +_I2C3RCVbits = 0x1938; + I2C3CON2 = 0x193C; +_I2C3CON2 = 0x193C; +_I2C3CON2bits = 0x193C; + I2C3LBRG = 0x1940; +_I2C3LBRG = 0x1940; +_I2C3LBRGbits = 0x1940; + I2C3INTC = 0x1944; +_I2C3INTC = 0x1944; +_I2C3INTCbits = 0x1944; + I2C3STAT2 = 0x1948; +_I2C3STAT2 = 0x1948; +_I2C3STAT2bits = 0x1948; + I2C3PEC = 0x194C; +_I2C3PEC = 0x194C; +_I2C3PECbits = 0x194C; + I2C3BTO = 0x1950; +_I2C3BTO = 0x1950; +_I2C3BTObits = 0x1950; + I2C3HBCTO = 0x1954; +_I2C3HBCTO = 0x1954; +_I2C3HBCTObits = 0x1954; + I2C3CBCTO = 0x1958; +_I2C3CBCTO = 0x1958; +_I2C3CBCTObits = 0x1958; + I2C3BITO = 0x195C; +_I2C3BITO = 0x195C; +_I2C3BITObits = 0x195C; + I2C3SDASUT = 0x1960; +_I2C3SDASUT = 0x1960; +_I2C3SDASUTbits = 0x1960; + I2C3HDLYC = 0x196C; +_I2C3HDLYC = 0x196C; +_I2C3HDLYCbits = 0x196C; + SENT1CON1 = 0x19C0; +_SENT1CON1 = 0x19C0; +_SENT1CON1bits = 0x19C0; + SENT1CON2 = 0x19C4; +_SENT1CON2 = 0x19C4; +_SENT1CON2bits = 0x19C4; + SENT1CON3 = 0x19C8; +_SENT1CON3 = 0x19C8; +_SENT1CON3bits = 0x19C8; + SENT1STAT = 0x19CC; +_SENT1STAT = 0x19CC; +_SENT1STATbits = 0x19CC; + SENT1SYNC = 0x19D0; +_SENT1SYNC = 0x19D0; +_SENT1SYNCbits = 0x19D0; + SENT1DAT = 0x19D4; +_SENT1DAT = 0x19D4; +_SENT1DATbits = 0x19D4; + SENT2CON1 = 0x19E0; +_SENT2CON1 = 0x19E0; +_SENT2CON1bits = 0x19E0; + SENT2CON2 = 0x19E4; +_SENT2CON2 = 0x19E4; +_SENT2CON2bits = 0x19E4; + SENT2CON3 = 0x19E8; +_SENT2CON3 = 0x19E8; +_SENT2CON3bits = 0x19E8; + SENT2STAT = 0x19EC; +_SENT2STAT = 0x19EC; +_SENT2STATbits = 0x19EC; + SENT2SYNC = 0x19F0; +_SENT2SYNC = 0x19F0; +_SENT2SYNCbits = 0x19F0; + SENT2DAT = 0x19F4; +_SENT2DAT = 0x19F4; +_SENT2DATbits = 0x19F4; + QEI1CON = 0x1A00; +_QEI1CON = 0x1A00; +_QEI1CONbits = 0x1A00; + QEI1IOC = 0x1A04; +_QEI1IOC = 0x1A04; +_QEI1IOCbits = 0x1A04; + QEI1STAT = 0x1A08; +_QEI1STAT = 0x1A08; +_QEI1STATbits = 0x1A08; + POS1CNT = 0x1A0C; +_POS1CNT = 0x1A0C; + POS1HLD = 0x1A10; +_POS1HLD = 0x1A10; + VEL1CNT = 0x1A14; +_VEL1CNT = 0x1A14; + VEL1HLD = 0x1A18; +_VEL1HLD = 0x1A18; + INT1TMR = 0x1A1C; +_INT1TMR = 0x1A1C; + INT1HLD = 0x1A20; +_INT1HLD = 0x1A20; + INDX1CNT = 0x1A24; +_INDX1CNT = 0x1A24; + INDX1HLD = 0x1A28; +_INDX1HLD = 0x1A28; + QEI1GEC = 0x1A2C; +_QEI1GEC = 0x1A2C; + QEI1LEC = 0x1A30; +_QEI1LEC = 0x1A30; + QEI2CON = 0x1A40; +_QEI2CON = 0x1A40; +_QEI2CONbits = 0x1A40; + QEI2IOC = 0x1A44; +_QEI2IOC = 0x1A44; +_QEI2IOCbits = 0x1A44; + QEI2STAT = 0x1A48; +_QEI2STAT = 0x1A48; +_QEI2STATbits = 0x1A48; + POS2CNT = 0x1A4C; +_POS2CNT = 0x1A4C; + POS2HLD = 0x1A50; +_POS2HLD = 0x1A50; + VEL2CNT = 0x1A54; +_VEL2CNT = 0x1A54; + VEL2HLD = 0x1A58; +_VEL2HLD = 0x1A58; + INT2TMR = 0x1A5C; +_INT2TMR = 0x1A5C; + INT2HLD = 0x1A60; +_INT2HLD = 0x1A60; + INDX2CNT = 0x1A64; +_INDX2CNT = 0x1A64; + INDX2HLD = 0x1A68; +_INDX2HLD = 0x1A68; + QEI2GEC = 0x1A6C; +_QEI2GEC = 0x1A6C; + QEI2LEC = 0x1A70; +_QEI2LEC = 0x1A70; + QEI3CON = 0x1A80; +_QEI3CON = 0x1A80; +_QEI3CONbits = 0x1A80; + QEI3IOC = 0x1A84; +_QEI3IOC = 0x1A84; +_QEI3IOCbits = 0x1A84; + QEI3STAT = 0x1A88; +_QEI3STAT = 0x1A88; +_QEI3STATbits = 0x1A88; + POS3CNT = 0x1A8C; +_POS3CNT = 0x1A8C; + POS3HLD = 0x1A90; +_POS3HLD = 0x1A90; + VEL3CNT = 0x1A94; +_VEL3CNT = 0x1A94; + VEL3HLD = 0x1A98; +_VEL3HLD = 0x1A98; + INT3TMR = 0x1A9C; +_INT3TMR = 0x1A9C; + INT3HLD = 0x1AA0; +_INT3HLD = 0x1AA0; + INDX3CNT = 0x1AA4; +_INDX3CNT = 0x1AA4; + INDX3HLD = 0x1AA8; +_INDX3HLD = 0x1AA8; + QEI3GEC = 0x1AAC; +_QEI3GEC = 0x1AAC; + QEI3LEC = 0x1AB0; +_QEI3LEC = 0x1AB0; + QEI4CON = 0x1AC0; +_QEI4CON = 0x1AC0; +_QEI4CONbits = 0x1AC0; + QEI4IOC = 0x1AC4; +_QEI4IOC = 0x1AC4; +_QEI4IOCbits = 0x1AC4; + QEI4STAT = 0x1AC8; +_QEI4STAT = 0x1AC8; +_QEI4STATbits = 0x1AC8; + POS4CNT = 0x1ACC; +_POS4CNT = 0x1ACC; + POS4HLD = 0x1AD0; +_POS4HLD = 0x1AD0; + VEL4CNT = 0x1AD4; +_VEL4CNT = 0x1AD4; + VEL4HLD = 0x1AD8; +_VEL4HLD = 0x1AD8; + INT4TMR = 0x1ADC; +_INT4TMR = 0x1ADC; + INT4HLD = 0x1AE0; +_INT4HLD = 0x1AE0; + INDX4CNT = 0x1AE4; +_INDX4CNT = 0x1AE4; + INDX4HLD = 0x1AE8; +_INDX4HLD = 0x1AE8; + QEI4GEC = 0x1AEC; +_QEI4GEC = 0x1AEC; + QEI4LEC = 0x1AF0; +_QEI4LEC = 0x1AF0; + CCP1CON1 = 0x1B00; +_CCP1CON1 = 0x1B00; +_CCP1CON1bits = 0x1B00; + CCP1CON2 = 0x1B04; +_CCP1CON2 = 0x1B04; +_CCP1CON2bits = 0x1B04; + CCP1CON3 = 0x1B08; +_CCP1CON3 = 0x1B08; +_CCP1CON3bits = 0x1B08; + CCP1STAT = 0x1B0C; +_CCP1STAT = 0x1B0C; +_CCP1STATbits = 0x1B0C; + CCP1TMR = 0x1B10; +_CCP1TMR = 0x1B10; +_CCP1TMRbits = 0x1B10; + CCP1PR = 0x1B14; +_CCP1PR = 0x1B14; +_CCP1PRbits = 0x1B14; + CCP1RA = 0x1B18; +_CCP1RA = 0x1B18; +_CCP1RAbits = 0x1B18; + CCP1RB = 0x1B1C; +_CCP1RB = 0x1B1C; +_CCP1RBbits = 0x1B1C; + CCP1BUF = 0x1B20; +_CCP1BUF = 0x1B20; +_CCP1BUFbits = 0x1B20; + CCP2CON1 = 0x1B30; +_CCP2CON1 = 0x1B30; +_CCP2CON1bits = 0x1B30; + CCP2CON2 = 0x1B34; +_CCP2CON2 = 0x1B34; +_CCP2CON2bits = 0x1B34; + CCP2CON3 = 0x1B38; +_CCP2CON3 = 0x1B38; +_CCP2CON3bits = 0x1B38; + CCP2STAT = 0x1B3C; +_CCP2STAT = 0x1B3C; +_CCP2STATbits = 0x1B3C; + CCP2TMR = 0x1B40; +_CCP2TMR = 0x1B40; +_CCP2TMRbits = 0x1B40; + CCP2PR = 0x1B44; +_CCP2PR = 0x1B44; +_CCP2PRbits = 0x1B44; + CCP2RA = 0x1B48; +_CCP2RA = 0x1B48; +_CCP2RAbits = 0x1B48; + CCP2RB = 0x1B4C; +_CCP2RB = 0x1B4C; +_CCP2RBbits = 0x1B4C; + CCP2BUF = 0x1B50; +_CCP2BUF = 0x1B50; +_CCP2BUFbits = 0x1B50; + CCP3CON1 = 0x1B60; +_CCP3CON1 = 0x1B60; +_CCP3CON1bits = 0x1B60; + CCP3CON2 = 0x1B64; +_CCP3CON2 = 0x1B64; +_CCP3CON2bits = 0x1B64; + CCP3CON3 = 0x1B68; +_CCP3CON3 = 0x1B68; +_CCP3CON3bits = 0x1B68; + CCP3STAT = 0x1B6C; +_CCP3STAT = 0x1B6C; +_CCP3STATbits = 0x1B6C; + CCP3TMR = 0x1B70; +_CCP3TMR = 0x1B70; +_CCP3TMRbits = 0x1B70; + CCP3PR = 0x1B74; +_CCP3PR = 0x1B74; +_CCP3PRbits = 0x1B74; + CCP3RA = 0x1B78; +_CCP3RA = 0x1B78; +_CCP3RAbits = 0x1B78; + CCP3RB = 0x1B7C; +_CCP3RB = 0x1B7C; +_CCP3RBbits = 0x1B7C; + CCP3BUF = 0x1B80; +_CCP3BUF = 0x1B80; +_CCP3BUFbits = 0x1B80; + CCP4CON1 = 0x1B90; +_CCP4CON1 = 0x1B90; +_CCP4CON1bits = 0x1B90; + CCP4CON2 = 0x1B94; +_CCP4CON2 = 0x1B94; +_CCP4CON2bits = 0x1B94; + CCP4CON3 = 0x1B98; +_CCP4CON3 = 0x1B98; +_CCP4CON3bits = 0x1B98; + CCP4STAT = 0x1B9C; +_CCP4STAT = 0x1B9C; +_CCP4STATbits = 0x1B9C; + CCP4TMR = 0x1BA0; +_CCP4TMR = 0x1BA0; +_CCP4TMRbits = 0x1BA0; + CCP4PR = 0x1BA4; +_CCP4PR = 0x1BA4; +_CCP4PRbits = 0x1BA4; + CCP4RA = 0x1BA8; +_CCP4RA = 0x1BA8; +_CCP4RAbits = 0x1BA8; + CCP4RB = 0x1BAC; +_CCP4RB = 0x1BAC; +_CCP4RBbits = 0x1BAC; + CCP4BUF = 0x1BB0; +_CCP4BUF = 0x1BB0; +_CCP4BUFbits = 0x1BB0; + CCP5CON1 = 0x1BC0; +_CCP5CON1 = 0x1BC0; +_CCP5CON1bits = 0x1BC0; + CCP5CON2 = 0x1BC4; +_CCP5CON2 = 0x1BC4; +_CCP5CON2bits = 0x1BC4; + CCP5CON3 = 0x1BC8; +_CCP5CON3 = 0x1BC8; +_CCP5CON3bits = 0x1BC8; + CCP5STAT = 0x1BCC; +_CCP5STAT = 0x1BCC; +_CCP5STATbits = 0x1BCC; + CCP5TMR = 0x1BD0; +_CCP5TMR = 0x1BD0; +_CCP5TMRbits = 0x1BD0; + CCP5PR = 0x1BD4; +_CCP5PR = 0x1BD4; +_CCP5PRbits = 0x1BD4; + CCP5RA = 0x1BD8; +_CCP5RA = 0x1BD8; +_CCP5RAbits = 0x1BD8; + CCP5RB = 0x1BDC; +_CCP5RB = 0x1BDC; +_CCP5RBbits = 0x1BDC; + CCP5BUF = 0x1BE0; +_CCP5BUF = 0x1BE0; +_CCP5BUFbits = 0x1BE0; + CCP6CON1 = 0x1BF0; +_CCP6CON1 = 0x1BF0; +_CCP6CON1bits = 0x1BF0; + CCP6CON2 = 0x1BF4; +_CCP6CON2 = 0x1BF4; +_CCP6CON2bits = 0x1BF4; + CCP6CON3 = 0x1BF8; +_CCP6CON3 = 0x1BF8; +_CCP6CON3bits = 0x1BF8; + CCP6STAT = 0x1BFC; +_CCP6STAT = 0x1BFC; +_CCP6STATbits = 0x1BFC; + CCP6TMR = 0x1C00; +_CCP6TMR = 0x1C00; +_CCP6TMRbits = 0x1C00; + CCP6PR = 0x1C04; +_CCP6PR = 0x1C04; +_CCP6PRbits = 0x1C04; + CCP6RA = 0x1C08; +_CCP6RA = 0x1C08; +_CCP6RAbits = 0x1C08; + CCP6RB = 0x1C0C; +_CCP6RB = 0x1C0C; +_CCP6RBbits = 0x1C0C; + CCP6BUF = 0x1C10; +_CCP6BUF = 0x1C10; +_CCP6BUFbits = 0x1C10; + CCP7CON1 = 0x1C20; +_CCP7CON1 = 0x1C20; +_CCP7CON1bits = 0x1C20; + CCP7CON2 = 0x1C24; +_CCP7CON2 = 0x1C24; +_CCP7CON2bits = 0x1C24; + CCP7CON3 = 0x1C28; +_CCP7CON3 = 0x1C28; +_CCP7CON3bits = 0x1C28; + CCP7STAT = 0x1C2C; +_CCP7STAT = 0x1C2C; +_CCP7STATbits = 0x1C2C; + CCP7TMR = 0x1C30; +_CCP7TMR = 0x1C30; +_CCP7TMRbits = 0x1C30; + CCP7PR = 0x1C34; +_CCP7PR = 0x1C34; +_CCP7PRbits = 0x1C34; + CCP7RA = 0x1C38; +_CCP7RA = 0x1C38; +_CCP7RAbits = 0x1C38; + CCP7RB = 0x1C3C; +_CCP7RB = 0x1C3C; +_CCP7RBbits = 0x1C3C; + CCP7BUF = 0x1C40; +_CCP7BUF = 0x1C40; +_CCP7BUFbits = 0x1C40; + CCP8CON1 = 0x1C50; +_CCP8CON1 = 0x1C50; +_CCP8CON1bits = 0x1C50; + CCP8CON2 = 0x1C54; +_CCP8CON2 = 0x1C54; +_CCP8CON2bits = 0x1C54; + CCP8CON3 = 0x1C58; +_CCP8CON3 = 0x1C58; +_CCP8CON3bits = 0x1C58; + CCP8STAT = 0x1C5C; +_CCP8STAT = 0x1C5C; +_CCP8STATbits = 0x1C5C; + CCP8TMR = 0x1C60; +_CCP8TMR = 0x1C60; +_CCP8TMRbits = 0x1C60; + CCP8PR = 0x1C64; +_CCP8PR = 0x1C64; +_CCP8PRbits = 0x1C64; + CCP8RA = 0x1C68; +_CCP8RA = 0x1C68; +_CCP8RAbits = 0x1C68; + CCP8RB = 0x1C6C; +_CCP8RB = 0x1C6C; +_CCP8RBbits = 0x1C6C; + CCP8BUF = 0x1C70; +_CCP8BUF = 0x1C70; +_CCP8BUFbits = 0x1C70; + CCP9CON1 = 0x1C80; +_CCP9CON1 = 0x1C80; +_CCP9CON1bits = 0x1C80; + CCP9CON2 = 0x1C84; +_CCP9CON2 = 0x1C84; +_CCP9CON2bits = 0x1C84; + CCP9CON3 = 0x1C88; +_CCP9CON3 = 0x1C88; +_CCP9CON3bits = 0x1C88; + CCP9STAT = 0x1C8C; +_CCP9STAT = 0x1C8C; +_CCP9STATbits = 0x1C8C; + CCP9TMR = 0x1C90; +_CCP9TMR = 0x1C90; +_CCP9TMRbits = 0x1C90; + CCP9PR = 0x1C94; +_CCP9PR = 0x1C94; +_CCP9PRbits = 0x1C94; + CCP9RA = 0x1C98; +_CCP9RA = 0x1C98; +_CCP9RAbits = 0x1C98; + CCP9RB = 0x1C9C; +_CCP9RB = 0x1C9C; +_CCP9RBbits = 0x1C9C; + CCP9BUF = 0x1CA0; +_CCP9BUF = 0x1CA0; +_CCP9BUFbits = 0x1CA0; + T1CON = 0x1CE0; +_T1CON = 0x1CE0; +_T1CONbits = 0x1CE0; + TMR1 = 0x1CE4; +_TMR1 = 0x1CE4; + PR1 = 0x1CE8; +_PR1 = 0x1CE8; + T2CON = 0x1CF0; +_T2CON = 0x1CF0; +_T2CONbits = 0x1CF0; + TMR2 = 0x1CF4; +_TMR2 = 0x1CF4; + PR2 = 0x1CF8; +_PR2 = 0x1CF8; + T3CON = 0x1D00; +_T3CON = 0x1D00; +_T3CONbits = 0x1D00; + TMR3 = 0x1D04; +_TMR3 = 0x1D04; + PR3 = 0x1D08; +_PR3 = 0x1D08; + DACCTRL1 = 0x1D40; +_DACCTRL1 = 0x1D40; +_DACCTRL1bits = 0x1D40; + DACCTRL2 = 0x1D44; +_DACCTRL2 = 0x1D44; +_DACCTRL2bits = 0x1D44; + DAC1CON = 0x1D48; +_DAC1CON = 0x1D48; +_DAC1CONbits = 0x1D48; + DAC1CMP = 0x1D4C; +_DAC1CMP = 0x1D4C; +_DAC1CMPbits = 0x1D4C; + DAC1DAT = 0x1D50; +_DAC1DAT = 0x1D50; +_DAC1DATbits = 0x1D50; + DAC1SLPCON = 0x1D54; +_DAC1SLPCON = 0x1D54; +_DAC1SLPCONbits = 0x1D54; + DAC1SLPDAT = 0x1D58; +_DAC1SLPDAT = 0x1D58; +_DAC1SLPDATbits = 0x1D58; + DAC2CON = 0x1D5C; +_DAC2CON = 0x1D5C; +_DAC2CONbits = 0x1D5C; + DAC2CMP = 0x1D60; +_DAC2CMP = 0x1D60; +_DAC2CMPbits = 0x1D60; + DAC2DAT = 0x1D64; +_DAC2DAT = 0x1D64; +_DAC2DATbits = 0x1D64; + DAC2SLPCON = 0x1D68; +_DAC2SLPCON = 0x1D68; +_DAC2SLPCONbits = 0x1D68; + DAC2SLPDAT = 0x1D6C; +_DAC2SLPDAT = 0x1D6C; +_DAC2SLPDATbits = 0x1D6C; + DAC3CON = 0x1D70; +_DAC3CON = 0x1D70; +_DAC3CONbits = 0x1D70; + DAC3CMP = 0x1D74; +_DAC3CMP = 0x1D74; +_DAC3CMPbits = 0x1D74; + DAC3DAT = 0x1D78; +_DAC3DAT = 0x1D78; +_DAC3DATbits = 0x1D78; + DAC3SLPCON = 0x1D7C; +_DAC3SLPCON = 0x1D7C; +_DAC3SLPCONbits = 0x1D7C; + DAC3SLPDAT = 0x1D80; +_DAC3SLPDAT = 0x1D80; +_DAC3SLPDATbits = 0x1D80; + DAC4CON = 0x1D84; +_DAC4CON = 0x1D84; +_DAC4CONbits = 0x1D84; + DAC4CMP = 0x1D88; +_DAC4CMP = 0x1D88; +_DAC4CMPbits = 0x1D88; + DAC4DAT = 0x1D8C; +_DAC4DAT = 0x1D8C; +_DAC4DATbits = 0x1D8C; + DAC4SLPCON = 0x1D90; +_DAC4SLPCON = 0x1D90; +_DAC4SLPCONbits = 0x1D90; + DAC4SLPDAT = 0x1D94; +_DAC4SLPDAT = 0x1D94; +_DAC4SLPDATbits = 0x1D94; + DAC5CON = 0x1D98; +_DAC5CON = 0x1D98; +_DAC5CONbits = 0x1D98; + DAC5CMP = 0x1D9C; +_DAC5CMP = 0x1D9C; +_DAC5CMPbits = 0x1D9C; + DAC5DAT = 0x1DA0; +_DAC5DAT = 0x1DA0; +_DAC5DATbits = 0x1DA0; + DAC5SLPCON = 0x1DA4; +_DAC5SLPCON = 0x1DA4; +_DAC5SLPCONbits = 0x1DA4; + DAC5SLPDAT = 0x1DA8; +_DAC5SLPDAT = 0x1DA8; +_DAC5SLPDATbits = 0x1DA8; + DAC6CON = 0x1DAC; +_DAC6CON = 0x1DAC; +_DAC6CONbits = 0x1DAC; + DAC6CMP = 0x1DB0; +_DAC6CMP = 0x1DB0; +_DAC6CMPbits = 0x1DB0; + DAC6DAT = 0x1DB4; +_DAC6DAT = 0x1DB4; +_DAC6DATbits = 0x1DB4; + DAC6SLPCON = 0x1DB8; +_DAC6SLPCON = 0x1DB8; +_DAC6SLPCONbits = 0x1DB8; + DAC6SLPDAT = 0x1DBC; +_DAC6SLPDAT = 0x1DBC; +_DAC6SLPDATbits = 0x1DBC; + DAC7CON = 0x1DC0; +_DAC7CON = 0x1DC0; +_DAC7CONbits = 0x1DC0; + DAC7CMP = 0x1DC4; +_DAC7CMP = 0x1DC4; +_DAC7CMPbits = 0x1DC4; + DAC7DAT = 0x1DC8; +_DAC7DAT = 0x1DC8; +_DAC7DATbits = 0x1DC8; + DAC7SLPCON = 0x1DCC; +_DAC7SLPCON = 0x1DCC; +_DAC7SLPCONbits = 0x1DCC; + DAC7SLPDAT = 0x1DD0; +_DAC7SLPDAT = 0x1DD0; +_DAC7SLPDATbits = 0x1DD0; + DAC8CON = 0x1DD4; +_DAC8CON = 0x1DD4; +_DAC8CONbits = 0x1DD4; + DAC8CMP = 0x1DD8; +_DAC8CMP = 0x1DD8; +_DAC8CMPbits = 0x1DD8; + DAC8DAT = 0x1DDC; +_DAC8DAT = 0x1DDC; +_DAC8DATbits = 0x1DDC; + DAC8SLPCON = 0x1DE0; +_DAC8SLPCON = 0x1DE0; +_DAC8SLPCONbits = 0x1DE0; + DAC8SLPDAT = 0x1DE4; +_DAC8SLPDAT = 0x1DE4; +_DAC8SLPDATbits = 0x1DE4; + HPCCON = 0x1E10; +_HPCCON = 0x1E10; +_HPCCONbits = 0x1E10; + HPSEL0 = 0x1E14; +_HPSEL0 = 0x1E14; +_HPSEL0bits = 0x1E14; + HPSEL1 = 0x1E18; +_HPSEL1 = 0x1E18; +_HPSEL1bits = 0x1E18; + HPCCNTL0 = 0x1E20; +_HPCCNTL0 = 0x1E20; + HPCCNTH0 = 0x1E24; +_HPCCNTH0 = 0x1E24; + HPCCNTL1 = 0x1E28; +_HPCCNTL1 = 0x1E28; + HPCCNTH1 = 0x1E2C; +_HPCCNTH1 = 0x1E2C; + HPCCNTL2 = 0x1E30; +_HPCCNTL2 = 0x1E30; + HPCCNTH2 = 0x1E34; +_HPCCNTH2 = 0x1E34; + HPCCNTL3 = 0x1E38; +_HPCCNTL3 = 0x1E38; + HPCCNTH3 = 0x1E3C; +_HPCCNTH3 = 0x1E3C; + HPCCNTL4 = 0x1E40; +_HPCCNTL4 = 0x1E40; + HPCCNTH4 = 0x1E44; +_HPCCNTH4 = 0x1E44; + HPCCNTL5 = 0x1E48; +_HPCCNTL5 = 0x1E48; + HPCCNTH5 = 0x1E4C; +_HPCCNTH5 = 0x1E4C; + HPCCNTL6 = 0x1E50; +_HPCCNTL6 = 0x1E50; + HPCCNTH6 = 0x1E54; +_HPCCNTH6 = 0x1E54; + HPCCNTL7 = 0x1E58; +_HPCCNTL7 = 0x1E58; + HPCCNTH7 = 0x1E5C; +_HPCCNTH7 = 0x1E5C; + CHECON = 0x1E60; +_CHECON = 0x1E60; +_CHECONbits = 0x1E60; + CHESTAT = 0x1E64; +_CHESTAT = 0x1E64; +_CHESTATbits = 0x1E64; + CHEFLTINJ = 0x1E68; +_CHEFLTINJ = 0x1E68; +_CHEFLTINJbits = 0x1E68; + PACCON1 = 0x1E80; +_PACCON1 = 0x1E80; +_PACCON1bits = 0x1E80; + PACCON2 = 0x1E84; +_PACCON2 = 0x1E84; +_PACCON2bits = 0x1E84; + PACCON3 = 0x1E88; +_PACCON3 = 0x1E88; +_PACCON3bits = 0x1E88; + IOIM1CON = 0x1E90; +_IOIM1CON = 0x1E90; +_IOIM1CONbits = 0x1E90; + IOIM1BCON = 0x1E94; +_IOIM1BCON = 0x1E94; +_IOIM1BCONbits = 0x1E94; + IOIM1STAT = 0x1E98; +_IOIM1STAT = 0x1E98; +_IOIM1STATbits = 0x1E98; + IOIM2CON = 0x1E9C; +_IOIM2CON = 0x1E9C; +_IOIM2CONbits = 0x1E9C; + IOIM2BCON = 0x1EA0; +_IOIM2BCON = 0x1EA0; +_IOIM2BCONbits = 0x1EA0; + IOIM2STAT = 0x1EA4; +_IOIM2STAT = 0x1EA4; +_IOIM2STATbits = 0x1EA4; + IOIM3CON = 0x1EA8; +_IOIM3CON = 0x1EA8; +_IOIM3CONbits = 0x1EA8; + IOIM3BCON = 0x1EAC; +_IOIM3BCON = 0x1EAC; +_IOIM3BCONbits = 0x1EAC; + IOIM3STAT = 0x1EB0; +_IOIM3STAT = 0x1EB0; +_IOIM3STATbits = 0x1EB0; + IOIM4CON = 0x1EB4; +_IOIM4CON = 0x1EB4; +_IOIM4CONbits = 0x1EB4; + IOIM4BCON = 0x1EB8; +_IOIM4BCON = 0x1EB8; +_IOIM4BCONbits = 0x1EB8; + IOIM4STAT = 0x1EBC; +_IOIM4STAT = 0x1EBC; +_IOIM4STATbits = 0x1EBC; + IOIM5CON = 0x1EC0; +_IOIM5CON = 0x1EC0; +_IOIM5CONbits = 0x1EC0; + IOIM5BCON = 0x1EC4; +_IOIM5BCON = 0x1EC4; +_IOIM5BCONbits = 0x1EC4; + IOIM5STAT = 0x1EC8; +_IOIM5STAT = 0x1EC8; +_IOIM5STATbits = 0x1EC8; + IOIM6CON = 0x1ECC; +_IOIM6CON = 0x1ECC; +_IOIM6CONbits = 0x1ECC; + IOIM6BCON = 0x1ED0; +_IOIM6BCON = 0x1ED0; +_IOIM6BCONbits = 0x1ED0; + IOIM6STAT = 0x1ED4; +_IOIM6STAT = 0x1ED4; +_IOIM6STATbits = 0x1ED4; + IOIM7CON = 0x1ED8; +_IOIM7CON = 0x1ED8; +_IOIM7CONbits = 0x1ED8; + IOIM7BCON = 0x1EDC; +_IOIM7BCON = 0x1EDC; +_IOIM7BCONbits = 0x1EDC; + IOIM7STAT = 0x1EE0; +_IOIM7STAT = 0x1EE0; +_IOIM7STATbits = 0x1EE0; + IOIM8CON = 0x1EE4; +_IOIM8CON = 0x1EE4; +_IOIM8CONbits = 0x1EE4; + IOIM8BCON = 0x1EE8; +_IOIM8BCON = 0x1EE8; +_IOIM8BCONbits = 0x1EE8; + IOIM8STAT = 0x1EEC; +_IOIM8STAT = 0x1EEC; +_IOIM8STATbits = 0x1EEC; + IOIM9CON = 0x1EF0; +_IOIM9CON = 0x1EF0; +_IOIM9CONbits = 0x1EF0; + IOIM9BCON = 0x1EF4; +_IOIM9BCON = 0x1EF4; +_IOIM9BCONbits = 0x1EF4; + IOIM9STAT = 0x1EF8; +_IOIM9STAT = 0x1EF8; +_IOIM9STATbits = 0x1EF8; + IOIM10CON = 0x1EFC; +_IOIM10CON = 0x1EFC; +_IOIM10CONbits = 0x1EFC; + IOIM10BCON = 0x1F00; +_IOIM10BCON = 0x1F00; +_IOIM10BCONbits = 0x1F00; + IOIM10STAT = 0x1F04; +_IOIM10STAT = 0x1F04; +_IOIM10STATbits = 0x1F04; + IOIM11CON = 0x1F08; +_IOIM11CON = 0x1F08; +_IOIM11CONbits = 0x1F08; + IOIM11BCON = 0x1F0C; +_IOIM11BCON = 0x1F0C; +_IOIM11BCONbits = 0x1F0C; + IOIM11STAT = 0x1F10; +_IOIM11STAT = 0x1F10; +_IOIM11STATbits = 0x1F10; + IOIM12CON = 0x1F14; +_IOIM12CON = 0x1F14; +_IOIM12CONbits = 0x1F14; + IOIM12BCON = 0x1F18; +_IOIM12BCON = 0x1F18; +_IOIM12BCONbits = 0x1F18; + IOIM12STAT = 0x1F1C; +_IOIM12STAT = 0x1F1C; +_IOIM12STATbits = 0x1F1C; + IOIM13CON = 0x1F20; +_IOIM13CON = 0x1F20; +_IOIM13CONbits = 0x1F20; + IOIM13BCON = 0x1F24; +_IOIM13BCON = 0x1F24; +_IOIM13BCONbits = 0x1F24; + IOIM13STAT = 0x1F28; +_IOIM13STAT = 0x1F28; +_IOIM13STATbits = 0x1F28; + IOIM14CON = 0x1F2C; +_IOIM14CON = 0x1F2C; +_IOIM14CONbits = 0x1F2C; + IOIM14BCON = 0x1F30; +_IOIM14BCON = 0x1F30; +_IOIM14BCONbits = 0x1F30; + IOIM14STAT = 0x1F34; +_IOIM14STAT = 0x1F34; +_IOIM14STATbits = 0x1F34; + IOIM15CON = 0x1F38; +_IOIM15CON = 0x1F38; +_IOIM15CONbits = 0x1F38; + IOIM15BCON = 0x1F3C; +_IOIM15BCON = 0x1F3C; +_IOIM15BCONbits = 0x1F3C; + IOIM15STAT = 0x1F40; +_IOIM15STAT = 0x1F40; +_IOIM15STATbits = 0x1F40; + IOIM16CON = 0x1F44; +_IOIM16CON = 0x1F44; +_IOIM16CONbits = 0x1F44; + IOIM16BCON = 0x1F48; +_IOIM16BCON = 0x1F48; +_IOIM16BCONbits = 0x1F48; + IOIM16STAT = 0x1F4C; +_IOIM16STAT = 0x1F4C; +_IOIM16STATbits = 0x1F4C; + B1SCDATA0L = 0x2100; +_B1SCDATA0L = 0x2100; + B1SCDATA0H = 0x2104; +_B1SCDATA0H = 0x2104; + B1SCDATA1L = 0x2108; +_B1SCDATA1L = 0x2108; + B1SCDATA1H = 0x210C; +_B1SCDATA1H = 0x210C; + B1SCDATA2L = 0x2110; +_B1SCDATA2L = 0x2110; + B1SCDATA2H = 0x2114; +_B1SCDATA2H = 0x2114; + B1SCDATA3L = 0x2118; +_B1SCDATA3L = 0x2118; + B1SCDATA3H = 0x211C; +_B1SCDATA3H = 0x211C; + B1IDS0 = 0x2180; +_B1IDS0 = 0x2180; +_B1IDS0bits = 0x2180; + B1RDATA0 = 0x2180; +_B1RDATA0 = 0x2180; +_B1RDATA0bits = 0x2180; + B1IDS1 = 0x2184; +_B1IDS1 = 0x2184; +_B1IDS1bits = 0x2184; + B1RDATA1 = 0x2184; +_B1RDATA1 = 0x2184; +_B1RDATA1bits = 0x2184; + B1IDS2 = 0x2188; +_B1IDS2 = 0x2188; +_B1IDS2bits = 0x2188; + B1RDATA2 = 0x2188; +_B1RDATA2 = 0x2188; +_B1RDATA2bits = 0x2188; + B1IDS3 = 0x218C; +_B1IDS3 = 0x218C; +_B1IDS3bits = 0x218C; + B1RDATA3 = 0x218C; +_B1RDATA3 = 0x218C; +_B1RDATA3bits = 0x218C; + B1IDS4 = 0x2190; +_B1IDS4 = 0x2190; +_B1IDS4bits = 0x2190; + B1RDATA4 = 0x2190; +_B1RDATA4 = 0x2190; +_B1RDATA4bits = 0x2190; + B1IDS5 = 0x2194; +_B1IDS5 = 0x2194; +_B1IDS5bits = 0x2194; + B1RDATA5 = 0x2194; +_B1RDATA5 = 0x2194; +_B1RDATA5bits = 0x2194; + B1IDS6 = 0x2198; +_B1IDS6 = 0x2198; +_B1IDS6bits = 0x2198; + B1RDATA6 = 0x2198; +_B1RDATA6 = 0x2198; +_B1RDATA6bits = 0x2198; + B1IDS7 = 0x219C; +_B1IDS7 = 0x219C; +_B1IDS7bits = 0x219C; + B1RDATA7 = 0x219C; +_B1RDATA7 = 0x219C; +_B1RDATA7bits = 0x219C; + B1CLTCON0 = 0x21C0; +_B1CLTCON0 = 0x21C0; +_B1CLTCON0bits = 0x21C0; + B1CLTCON1 = 0x21C4; +_B1CLTCON1 = 0x21C4; +_B1CLTCON1bits = 0x21C4; + B1CLTCON2 = 0x21C8; +_B1CLTCON2 = 0x21C8; +_B1CLTCON2bits = 0x21C8; + B1CLTCON3 = 0x21CC; +_B1CLTCON3 = 0x21CC; +_B1CLTCON3bits = 0x21CC; + B1RCCON = 0x21E0; +_B1RCCON = 0x21E0; +_B1RCCONbits = 0x21E0; + B1CTRLCON = 0x21E4; +_B1CTRLCON = 0x21E4; +_B1CTRLCONbits = 0x21E4; + B1CCON = 0x21E8; +_B1CCON = 0x21E8; +_B1CCONbits = 0x21E8; + B1CHCON = 0x21EC; +_B1CHCON = 0x21EC; +_B1CHCONbits = 0x21EC; + B1STAT = 0x21F0; +_B1STAT = 0x21F0; +_B1STATbits = 0x21F0; + B1INSTR = 0x21F4; +_B1INSTR = 0x21F4; +_B1INSTRbits = 0x21F4; + B1CHSTAT = 0x21F8; +_B1CHSTAT = 0x21F8; +_B1CHSTATbits = 0x21F8; + B1CON = 0x21FC; +_B1CON = 0x21FC; +_B1CONbits = 0x21FC; + DMACON = 0x2300; +_DMACON = 0x2300; +_DMACONbits = 0x2300; + DMABUF = 0x2304; +_DMABUF = 0x2304; + DMALOW = 0x2308; +_DMALOW = 0x2308; +_DMALOWbits = 0x2308; + DMAHIGH = 0x230C; +_DMAHIGH = 0x230C; +_DMAHIGHbits = 0x230C; + DMA0CH = 0x2310; +_DMA0CH = 0x2310; +_DMA0CHbits = 0x2310; + DMA0SEL = 0x2314; +_DMA0SEL = 0x2314; +_DMA0SELbits = 0x2314; + DMA0STAT = 0x2318; +_DMA0STAT = 0x2318; +_DMA0STATbits = 0x2318; + DMA0SRC = 0x231C; +_DMA0SRC = 0x231C; +_DMA0SRCbits = 0x231C; + DMA0DST = 0x2320; +_DMA0DST = 0x2320; +_DMA0DSTbits = 0x2320; + DMA0CNT = 0x2324; +_DMA0CNT = 0x2324; +_DMA0CNTbits = 0x2324; + DMA0CLR = 0x2328; +_DMA0CLR = 0x2328; + DMA0SET = 0x232C; +_DMA0SET = 0x232C; + DMA0INV = 0x2330; +_DMA0INV = 0x2330; + DMA0MSK = 0x2334; +_DMA0MSK = 0x2334; + DMA0PAT = 0x2338; +_DMA0PAT = 0x2338; + DMA1CH = 0x233C; +_DMA1CH = 0x233C; +_DMA1CHbits = 0x233C; + DMA1SEL = 0x2340; +_DMA1SEL = 0x2340; +_DMA1SELbits = 0x2340; + DMA1STAT = 0x2344; +_DMA1STAT = 0x2344; +_DMA1STATbits = 0x2344; + DMA1SRC = 0x2348; +_DMA1SRC = 0x2348; +_DMA1SRCbits = 0x2348; + DMA1DST = 0x234C; +_DMA1DST = 0x234C; +_DMA1DSTbits = 0x234C; + DMA1CNT = 0x2350; +_DMA1CNT = 0x2350; +_DMA1CNTbits = 0x2350; + DMA1CLR = 0x2354; +_DMA1CLR = 0x2354; + DMA1SET = 0x2358; +_DMA1SET = 0x2358; + DMA1INV = 0x235C; +_DMA1INV = 0x235C; + DMA1MSK = 0x2360; +_DMA1MSK = 0x2360; + DMA1PAT = 0x2364; +_DMA1PAT = 0x2364; + DMA2CH = 0x2368; +_DMA2CH = 0x2368; +_DMA2CHbits = 0x2368; + DMA2SEL = 0x236C; +_DMA2SEL = 0x236C; +_DMA2SELbits = 0x236C; + DMA2STAT = 0x2370; +_DMA2STAT = 0x2370; +_DMA2STATbits = 0x2370; + DMA2SRC = 0x2374; +_DMA2SRC = 0x2374; +_DMA2SRCbits = 0x2374; + DMA2DST = 0x2378; +_DMA2DST = 0x2378; +_DMA2DSTbits = 0x2378; + DMA2CNT = 0x237C; +_DMA2CNT = 0x237C; +_DMA2CNTbits = 0x237C; + DMA2CLR = 0x2380; +_DMA2CLR = 0x2380; + DMA2SET = 0x2384; +_DMA2SET = 0x2384; + DMA2INV = 0x2388; +_DMA2INV = 0x2388; + DMA2MSK = 0x238C; +_DMA2MSK = 0x238C; + DMA2PAT = 0x2390; +_DMA2PAT = 0x2390; + DMA3CH = 0x2394; +_DMA3CH = 0x2394; +_DMA3CHbits = 0x2394; + DMA3SEL = 0x2398; +_DMA3SEL = 0x2398; +_DMA3SELbits = 0x2398; + DMA3STAT = 0x239C; +_DMA3STAT = 0x239C; +_DMA3STATbits = 0x239C; + DMA3SRC = 0x23A0; +_DMA3SRC = 0x23A0; +_DMA3SRCbits = 0x23A0; + DMA3DST = 0x23A4; +_DMA3DST = 0x23A4; +_DMA3DSTbits = 0x23A4; + DMA3CNT = 0x23A8; +_DMA3CNT = 0x23A8; +_DMA3CNTbits = 0x23A8; + DMA3CLR = 0x23AC; +_DMA3CLR = 0x23AC; + DMA3SET = 0x23B0; +_DMA3SET = 0x23B0; + DMA3INV = 0x23B4; +_DMA3INV = 0x23B4; + DMA3MSK = 0x23B8; +_DMA3MSK = 0x23B8; + DMA3PAT = 0x23BC; +_DMA3PAT = 0x23BC; + DMA4CH = 0x23C0; +_DMA4CH = 0x23C0; +_DMA4CHbits = 0x23C0; + DMA4SEL = 0x23C4; +_DMA4SEL = 0x23C4; +_DMA4SELbits = 0x23C4; + DMA4STAT = 0x23C8; +_DMA4STAT = 0x23C8; +_DMA4STATbits = 0x23C8; + DMA4SRC = 0x23CC; +_DMA4SRC = 0x23CC; +_DMA4SRCbits = 0x23CC; + DMA4DST = 0x23D0; +_DMA4DST = 0x23D0; +_DMA4DSTbits = 0x23D0; + DMA4CNT = 0x23D4; +_DMA4CNT = 0x23D4; +_DMA4CNTbits = 0x23D4; + DMA4CLR = 0x23D8; +_DMA4CLR = 0x23D8; + DMA4SET = 0x23DC; +_DMA4SET = 0x23DC; + DMA4INV = 0x23E0; +_DMA4INV = 0x23E0; + DMA4MSK = 0x23E4; +_DMA4MSK = 0x23E4; + DMA4PAT = 0x23E8; +_DMA4PAT = 0x23E8; + DMA5CH = 0x23EC; +_DMA5CH = 0x23EC; +_DMA5CHbits = 0x23EC; + DMA5SEL = 0x23F0; +_DMA5SEL = 0x23F0; +_DMA5SELbits = 0x23F0; + DMA5STAT = 0x23F4; +_DMA5STAT = 0x23F4; +_DMA5STATbits = 0x23F4; + DMA5SRC = 0x23F8; +_DMA5SRC = 0x23F8; +_DMA5SRCbits = 0x23F8; + DMA5DST = 0x23FC; +_DMA5DST = 0x23FC; +_DMA5DSTbits = 0x23FC; + DMA5CNT = 0x2400; +_DMA5CNT = 0x2400; +_DMA5CNTbits = 0x2400; + DMA5CLR = 0x2404; +_DMA5CLR = 0x2404; + DMA5SET = 0x2408; +_DMA5SET = 0x2408; + DMA5INV = 0x240C; +_DMA5INV = 0x240C; + DMA5MSK = 0x2410; +_DMA5MSK = 0x2410; + DMA5PAT = 0x2414; +_DMA5PAT = 0x2414; + DMA6CH = 0x2418; +_DMA6CH = 0x2418; +_DMA6CHbits = 0x2418; + DMA6SEL = 0x241C; +_DMA6SEL = 0x241C; +_DMA6SELbits = 0x241C; + DMA6STAT = 0x2420; +_DMA6STAT = 0x2420; +_DMA6STATbits = 0x2420; + DMA6SRC = 0x2424; +_DMA6SRC = 0x2424; +_DMA6SRCbits = 0x2424; + DMA6DST = 0x2428; +_DMA6DST = 0x2428; +_DMA6DSTbits = 0x2428; + DMA6CNT = 0x242C; +_DMA6CNT = 0x242C; +_DMA6CNTbits = 0x242C; + DMA6CLR = 0x2430; +_DMA6CLR = 0x2430; + DMA6SET = 0x2434; +_DMA6SET = 0x2434; + DMA6INV = 0x2438; +_DMA6INV = 0x2438; + DMA6MSK = 0x243C; +_DMA6MSK = 0x243C; + DMA6PAT = 0x2440; +_DMA6PAT = 0x2440; + DMA7CH = 0x2444; +_DMA7CH = 0x2444; +_DMA7CHbits = 0x2444; + DMA7SEL = 0x2448; +_DMA7SEL = 0x2448; +_DMA7SELbits = 0x2448; + DMA7STAT = 0x244C; +_DMA7STAT = 0x244C; +_DMA7STATbits = 0x244C; + DMA7SRC = 0x2450; +_DMA7SRC = 0x2450; +_DMA7SRCbits = 0x2450; + DMA7DST = 0x2454; +_DMA7DST = 0x2454; +_DMA7DSTbits = 0x2454; + DMA7CNT = 0x2458; +_DMA7CNT = 0x2458; +_DMA7CNTbits = 0x2458; + DMA7CLR = 0x245C; +_DMA7CLR = 0x245C; + DMA7SET = 0x2460; +_DMA7SET = 0x2460; + DMA7INV = 0x2464; +_DMA7INV = 0x2464; + DMA7MSK = 0x2468; +_DMA7MSK = 0x2468; + DMA7PAT = 0x246C; +_DMA7PAT = 0x246C; + C1CON = 0x2600; +_C1CON = 0x2600; +_C1CONbits = 0x2600; + C1NBTCFG = 0x2604; +_C1NBTCFG = 0x2604; +_C1NBTCFGbits = 0x2604; + C1DBTCFG = 0x2608; +_C1DBTCFG = 0x2608; +_C1DBTCFGbits = 0x2608; + C1TDC = 0x260C; +_C1TDC = 0x260C; +_C1TDCbits = 0x260C; + C1TBC = 0x2610; +_C1TBC = 0x2610; + C1TSCON = 0x2614; +_C1TSCON = 0x2614; +_C1TSCONbits = 0x2614; + C1VEC = 0x2618; +_C1VEC = 0x2618; +_C1VECbits = 0x2618; + C1INT = 0x261C; +_C1INT = 0x261C; +_C1INTbits = 0x261C; + C1RXIF = 0x2620; +_C1RXIF = 0x2620; +_C1RXIFbits = 0x2620; + C1TXIF = 0x2624; +_C1TXIF = 0x2624; + C1RXOVIF = 0x2628; +_C1RXOVIF = 0x2628; +_C1RXOVIFbits = 0x2628; + C1TXATIF = 0x262C; +_C1TXATIF = 0x262C; + C1TXREQ = 0x2630; +_C1TXREQ = 0x2630; + C1TREC = 0x2634; +_C1TREC = 0x2634; +_C1TRECbits = 0x2634; + C1BDIAG0 = 0x2638; +_C1BDIAG0 = 0x2638; +_C1BDIAG0bits = 0x2638; + C1BDIAG1 = 0x263C; +_C1BDIAG1 = 0x263C; +_C1BDIAG1bits = 0x263C; + C1TEFCON = 0x2640; +_C1TEFCON = 0x2640; +_C1TEFCONbits = 0x2640; + C1TEFSTA = 0x2644; +_C1TEFSTA = 0x2644; +_C1TEFSTAbits = 0x2644; + C1TEFUA = 0x2648; +_C1TEFUA = 0x2648; + C1FIFOBA = 0x264C; +_C1FIFOBA = 0x264C; + C1TXQCON = 0x2650; +_C1TXQCON = 0x2650; +_C1TXQCONbits = 0x2650; + C1TXQSTA = 0x2654; +_C1TXQSTA = 0x2654; +_C1TXQSTAbits = 0x2654; + C1TXQUA = 0x2658; +_C1TXQUA = 0x2658; + C1FIFOCON1 = 0x265C; +_C1FIFOCON1 = 0x265C; +_C1FIFOCON1bits = 0x265C; + C1FIFOSTA1 = 0x2660; +_C1FIFOSTA1 = 0x2660; +_C1FIFOSTA1bits = 0x2660; + C1FIFOUA1 = 0x2664; +_C1FIFOUA1 = 0x2664; + C1FIFOCON2 = 0x2668; +_C1FIFOCON2 = 0x2668; +_C1FIFOCON2bits = 0x2668; + C1FIFOSTA2 = 0x266C; +_C1FIFOSTA2 = 0x266C; +_C1FIFOSTA2bits = 0x266C; + C1FIFOUA2 = 0x2670; +_C1FIFOUA2 = 0x2670; + C1FIFOCON3 = 0x2674; +_C1FIFOCON3 = 0x2674; +_C1FIFOCON3bits = 0x2674; + C1FIFOSTA3 = 0x2678; +_C1FIFOSTA3 = 0x2678; +_C1FIFOSTA3bits = 0x2678; + C1FIFOUA3 = 0x267C; +_C1FIFOUA3 = 0x267C; + C1FIFOCON4 = 0x2680; +_C1FIFOCON4 = 0x2680; +_C1FIFOCON4bits = 0x2680; + C1FIFOSTA4 = 0x2684; +_C1FIFOSTA4 = 0x2684; +_C1FIFOSTA4bits = 0x2684; + C1FIFOUA4 = 0x2688; +_C1FIFOUA4 = 0x2688; + C1FIFOCON5 = 0x268C; +_C1FIFOCON5 = 0x268C; +_C1FIFOCON5bits = 0x268C; + C1FIFOSTA5 = 0x2690; +_C1FIFOSTA5 = 0x2690; +_C1FIFOSTA5bits = 0x2690; + C1FIFOUA5 = 0x2694; +_C1FIFOUA5 = 0x2694; + C1FIFOCON6 = 0x2698; +_C1FIFOCON6 = 0x2698; +_C1FIFOCON6bits = 0x2698; + C1FIFOSTA6 = 0x269C; +_C1FIFOSTA6 = 0x269C; +_C1FIFOSTA6bits = 0x269C; + C1FIFOUA6 = 0x26A0; +_C1FIFOUA6 = 0x26A0; + C1FIFOCON7 = 0x26A4; +_C1FIFOCON7 = 0x26A4; +_C1FIFOCON7bits = 0x26A4; + C1FIFOSTA7 = 0x26A8; +_C1FIFOSTA7 = 0x26A8; +_C1FIFOSTA7bits = 0x26A8; + C1FIFOUA7 = 0x26AC; +_C1FIFOUA7 = 0x26AC; + C1FLTCON0 = 0x26B0; +_C1FLTCON0 = 0x26B0; +_C1FLTCON0bits = 0x26B0; + C1FLTCON1 = 0x26B4; +_C1FLTCON1 = 0x26B4; +_C1FLTCON1bits = 0x26B4; + C1FLTCON2 = 0x26B8; +_C1FLTCON2 = 0x26B8; +_C1FLTCON2bits = 0x26B8; + C1FLTCON3 = 0x26BC; +_C1FLTCON3 = 0x26BC; +_C1FLTCON3bits = 0x26BC; + C1FLTOBJ0 = 0x26C0; +_C1FLTOBJ0 = 0x26C0; +_C1FLTOBJ0bits = 0x26C0; + C1MASK0 = 0x26C4; +_C1MASK0 = 0x26C4; +_C1MASK0bits = 0x26C4; + C1FLTOBJ1 = 0x26C8; +_C1FLTOBJ1 = 0x26C8; +_C1FLTOBJ1bits = 0x26C8; + C1MASK1 = 0x26CC; +_C1MASK1 = 0x26CC; +_C1MASK1bits = 0x26CC; + C1FLTOBJ2 = 0x26D0; +_C1FLTOBJ2 = 0x26D0; +_C1FLTOBJ2bits = 0x26D0; + C1MASK2 = 0x26D4; +_C1MASK2 = 0x26D4; +_C1MASK2bits = 0x26D4; + C1FLTOBJ3 = 0x26D8; +_C1FLTOBJ3 = 0x26D8; +_C1FLTOBJ3bits = 0x26D8; + C1MASK3 = 0x26DC; +_C1MASK3 = 0x26DC; +_C1MASK3bits = 0x26DC; + C1FLTOBJ4 = 0x26E0; +_C1FLTOBJ4 = 0x26E0; +_C1FLTOBJ4bits = 0x26E0; + C1MASK4 = 0x26E4; +_C1MASK4 = 0x26E4; +_C1MASK4bits = 0x26E4; + C1FLTOBJ5 = 0x26E8; +_C1FLTOBJ5 = 0x26E8; +_C1FLTOBJ5bits = 0x26E8; + C1MASK5 = 0x26EC; +_C1MASK5 = 0x26EC; +_C1MASK5bits = 0x26EC; + C1FLTOBJ6 = 0x26F0; +_C1FLTOBJ6 = 0x26F0; +_C1FLTOBJ6bits = 0x26F0; + C1MASK6 = 0x26F4; +_C1MASK6 = 0x26F4; +_C1MASK6bits = 0x26F4; + C1FLTOBJ7 = 0x26F8; +_C1FLTOBJ7 = 0x26F8; +_C1FLTOBJ7bits = 0x26F8; + C1MASK7 = 0x26FC; +_C1MASK7 = 0x26FC; +_C1MASK7bits = 0x26FC; + C1FLTOBJ8 = 0x2700; +_C1FLTOBJ8 = 0x2700; +_C1FLTOBJ8bits = 0x2700; + C1MASK8 = 0x2704; +_C1MASK8 = 0x2704; +_C1MASK8bits = 0x2704; + C1FLTOBJ9 = 0x2708; +_C1FLTOBJ9 = 0x2708; +_C1FLTOBJ9bits = 0x2708; + C1MASK9 = 0x270C; +_C1MASK9 = 0x270C; +_C1MASK9bits = 0x270C; + C1FLTOBJ10 = 0x2710; +_C1FLTOBJ10 = 0x2710; +_C1FLTOBJ10bits = 0x2710; + C1MASK10 = 0x2714; +_C1MASK10 = 0x2714; +_C1MASK10bits = 0x2714; + C1FLTOBJ11 = 0x2718; +_C1FLTOBJ11 = 0x2718; +_C1FLTOBJ11bits = 0x2718; + C1MASK11 = 0x271C; +_C1MASK11 = 0x271C; +_C1MASK11bits = 0x271C; + C1FLTOBJ12 = 0x2720; +_C1FLTOBJ12 = 0x2720; +_C1FLTOBJ12bits = 0x2720; + C1MASK12 = 0x2724; +_C1MASK12 = 0x2724; +_C1MASK12bits = 0x2724; + C1FLTOBJ13 = 0x2728; +_C1FLTOBJ13 = 0x2728; +_C1FLTOBJ13bits = 0x2728; + C1MASK13 = 0x272C; +_C1MASK13 = 0x272C; +_C1MASK13bits = 0x272C; + C1FLTOBJ14 = 0x2730; +_C1FLTOBJ14 = 0x2730; +_C1FLTOBJ14bits = 0x2730; + C1MASK14 = 0x2734; +_C1MASK14 = 0x2734; +_C1MASK14bits = 0x2734; + C1FLTOBJ15 = 0x2738; +_C1FLTOBJ15 = 0x2738; +_C1FLTOBJ15bits = 0x2738; + C1MASK15 = 0x273C; +_C1MASK15 = 0x273C; +_C1MASK15bits = 0x273C; + C2CON = 0x28F0; +_C2CON = 0x28F0; +_C2CONbits = 0x28F0; + C2NBTCFG = 0x28F4; +_C2NBTCFG = 0x28F4; +_C2NBTCFGbits = 0x28F4; + C2DBTCFG = 0x28F8; +_C2DBTCFG = 0x28F8; +_C2DBTCFGbits = 0x28F8; + C2TDC = 0x28FC; +_C2TDC = 0x28FC; +_C2TDCbits = 0x28FC; + C2TBC = 0x2900; +_C2TBC = 0x2900; + C2TSCON = 0x2904; +_C2TSCON = 0x2904; +_C2TSCONbits = 0x2904; + C2VEC = 0x2908; +_C2VEC = 0x2908; +_C2VECbits = 0x2908; + C2INT = 0x290C; +_C2INT = 0x290C; +_C2INTbits = 0x290C; + C2RXIF = 0x2910; +_C2RXIF = 0x2910; +_C2RXIFbits = 0x2910; + C2TXIF = 0x2914; +_C2TXIF = 0x2914; + C2RXOVIF = 0x2918; +_C2RXOVIF = 0x2918; +_C2RXOVIFbits = 0x2918; + C2TXATIF = 0x291C; +_C2TXATIF = 0x291C; + C2TXREQ = 0x2920; +_C2TXREQ = 0x2920; + C2TREC = 0x2924; +_C2TREC = 0x2924; +_C2TRECbits = 0x2924; + C2BDIAG0 = 0x2928; +_C2BDIAG0 = 0x2928; +_C2BDIAG0bits = 0x2928; + C2BDIAG1 = 0x292C; +_C2BDIAG1 = 0x292C; +_C2BDIAG1bits = 0x292C; + C2TEFCON = 0x2930; +_C2TEFCON = 0x2930; +_C2TEFCONbits = 0x2930; + C2TEFSTA = 0x2934; +_C2TEFSTA = 0x2934; +_C2TEFSTAbits = 0x2934; + C2TEFUA = 0x2938; +_C2TEFUA = 0x2938; + C2FIFOBA = 0x293C; +_C2FIFOBA = 0x293C; + C2TXQCON = 0x2940; +_C2TXQCON = 0x2940; +_C2TXQCONbits = 0x2940; + C2TXQSTA = 0x2944; +_C2TXQSTA = 0x2944; +_C2TXQSTAbits = 0x2944; + C2TXQUA = 0x2948; +_C2TXQUA = 0x2948; + C2FIFOCON1 = 0x294C; +_C2FIFOCON1 = 0x294C; +_C2FIFOCON1bits = 0x294C; + C2FIFOSTA1 = 0x2950; +_C2FIFOSTA1 = 0x2950; +_C2FIFOSTA1bits = 0x2950; + C2FIFOUA1 = 0x2954; +_C2FIFOUA1 = 0x2954; + C2FIFOCON2 = 0x2958; +_C2FIFOCON2 = 0x2958; +_C2FIFOCON2bits = 0x2958; + C2FIFOSTA2 = 0x295C; +_C2FIFOSTA2 = 0x295C; +_C2FIFOSTA2bits = 0x295C; + C2FIFOUA2 = 0x2960; +_C2FIFOUA2 = 0x2960; + C2FIFOCON3 = 0x2964; +_C2FIFOCON3 = 0x2964; +_C2FIFOCON3bits = 0x2964; + C2FIFOSTA3 = 0x2968; +_C2FIFOSTA3 = 0x2968; +_C2FIFOSTA3bits = 0x2968; + C2FIFOUA3 = 0x296C; +_C2FIFOUA3 = 0x296C; + C2FIFOCON4 = 0x2970; +_C2FIFOCON4 = 0x2970; +_C2FIFOCON4bits = 0x2970; + C2FIFOSTA4 = 0x2974; +_C2FIFOSTA4 = 0x2974; +_C2FIFOSTA4bits = 0x2974; + C2FIFOUA4 = 0x2978; +_C2FIFOUA4 = 0x2978; + C2FIFOCON5 = 0x297C; +_C2FIFOCON5 = 0x297C; +_C2FIFOCON5bits = 0x297C; + C2FIFOSTA5 = 0x2980; +_C2FIFOSTA5 = 0x2980; +_C2FIFOSTA5bits = 0x2980; + C2FIFOUA5 = 0x2984; +_C2FIFOUA5 = 0x2984; + C2FIFOCON6 = 0x2988; +_C2FIFOCON6 = 0x2988; +_C2FIFOCON6bits = 0x2988; + C2FIFOSTA6 = 0x298C; +_C2FIFOSTA6 = 0x298C; +_C2FIFOSTA6bits = 0x298C; + C2FIFOUA6 = 0x2990; +_C2FIFOUA6 = 0x2990; + C2FIFOCON7 = 0x2994; +_C2FIFOCON7 = 0x2994; +_C2FIFOCON7bits = 0x2994; + C2FIFOSTA7 = 0x2998; +_C2FIFOSTA7 = 0x2998; +_C2FIFOSTA7bits = 0x2998; + C2FIFOUA7 = 0x299C; +_C2FIFOUA7 = 0x299C; + C2FLTCON0 = 0x29A0; +_C2FLTCON0 = 0x29A0; +_C2FLTCON0bits = 0x29A0; + C2FLTCON1 = 0x29A4; +_C2FLTCON1 = 0x29A4; +_C2FLTCON1bits = 0x29A4; + C2FLTCON2 = 0x29A8; +_C2FLTCON2 = 0x29A8; +_C2FLTCON2bits = 0x29A8; + C2FLTCON3 = 0x29AC; +_C2FLTCON3 = 0x29AC; +_C2FLTCON3bits = 0x29AC; + C2FLTOBJ0 = 0x29B0; +_C2FLTOBJ0 = 0x29B0; +_C2FLTOBJ0bits = 0x29B0; + C2MASK0 = 0x29B4; +_C2MASK0 = 0x29B4; +_C2MASK0bits = 0x29B4; + C2FLTOBJ1 = 0x29B8; +_C2FLTOBJ1 = 0x29B8; +_C2FLTOBJ1bits = 0x29B8; + C2MASK1 = 0x29BC; +_C2MASK1 = 0x29BC; +_C2MASK1bits = 0x29BC; + C2FLTOBJ2 = 0x29C0; +_C2FLTOBJ2 = 0x29C0; +_C2FLTOBJ2bits = 0x29C0; + C2MASK2 = 0x29C4; +_C2MASK2 = 0x29C4; +_C2MASK2bits = 0x29C4; + C2FLTOBJ3 = 0x29C8; +_C2FLTOBJ3 = 0x29C8; +_C2FLTOBJ3bits = 0x29C8; + C2MASK3 = 0x29CC; +_C2MASK3 = 0x29CC; +_C2MASK3bits = 0x29CC; + C2FLTOBJ4 = 0x29D0; +_C2FLTOBJ4 = 0x29D0; +_C2FLTOBJ4bits = 0x29D0; + C2MASK4 = 0x29D4; +_C2MASK4 = 0x29D4; +_C2MASK4bits = 0x29D4; + C2FLTOBJ5 = 0x29D8; +_C2FLTOBJ5 = 0x29D8; +_C2FLTOBJ5bits = 0x29D8; + C2MASK5 = 0x29DC; +_C2MASK5 = 0x29DC; +_C2MASK5bits = 0x29DC; + C2FLTOBJ6 = 0x29E0; +_C2FLTOBJ6 = 0x29E0; +_C2FLTOBJ6bits = 0x29E0; + C2MASK6 = 0x29E4; +_C2MASK6 = 0x29E4; +_C2MASK6bits = 0x29E4; + C2FLTOBJ7 = 0x29E8; +_C2FLTOBJ7 = 0x29E8; +_C2FLTOBJ7bits = 0x29E8; + C2MASK7 = 0x29EC; +_C2MASK7 = 0x29EC; +_C2MASK7bits = 0x29EC; + C2FLTOBJ8 = 0x29F0; +_C2FLTOBJ8 = 0x29F0; +_C2FLTOBJ8bits = 0x29F0; + C2MASK8 = 0x29F4; +_C2MASK8 = 0x29F4; +_C2MASK8bits = 0x29F4; + C2FLTOBJ9 = 0x29F8; +_C2FLTOBJ9 = 0x29F8; +_C2FLTOBJ9bits = 0x29F8; + C2MASK9 = 0x29FC; +_C2MASK9 = 0x29FC; +_C2MASK9bits = 0x29FC; + C2FLTOBJ10 = 0x2A00; +_C2FLTOBJ10 = 0x2A00; +_C2FLTOBJ10bits = 0x2A00; + C2MASK10 = 0x2A04; +_C2MASK10 = 0x2A04; +_C2MASK10bits = 0x2A04; + C2FLTOBJ11 = 0x2A08; +_C2FLTOBJ11 = 0x2A08; +_C2FLTOBJ11bits = 0x2A08; + C2MASK11 = 0x2A0C; +_C2MASK11 = 0x2A0C; +_C2MASK11bits = 0x2A0C; + C2FLTOBJ12 = 0x2A10; +_C2FLTOBJ12 = 0x2A10; +_C2FLTOBJ12bits = 0x2A10; + C2MASK12 = 0x2A14; +_C2MASK12 = 0x2A14; +_C2MASK12bits = 0x2A14; + C2FLTOBJ13 = 0x2A18; +_C2FLTOBJ13 = 0x2A18; +_C2FLTOBJ13bits = 0x2A18; + C2MASK13 = 0x2A1C; +_C2MASK13 = 0x2A1C; +_C2MASK13bits = 0x2A1C; + C2FLTOBJ14 = 0x2A20; +_C2FLTOBJ14 = 0x2A20; +_C2FLTOBJ14bits = 0x2A20; + C2MASK14 = 0x2A24; +_C2MASK14 = 0x2A24; +_C2MASK14bits = 0x2A24; + C2FLTOBJ15 = 0x2A28; +_C2FLTOBJ15 = 0x2A28; +_C2FLTOBJ15bits = 0x2A28; + C2MASK15 = 0x2A2C; +_C2MASK15 = 0x2A2C; +_C2MASK15bits = 0x2A2C; + NVMCON = 0x3000; +_NVMCON = 0x3000; +_NVMCONbits = 0x3000; + NVMADR = 0x3004; +_NVMADR = 0x3004; +_NVMADRbits = 0x3004; + NVMDATA0 = 0x3008; +_NVMDATA0 = 0x3008; + NVMDATA1 = 0x300C; +_NVMDATA1 = 0x300C; + NVMDATA2 = 0x3010; +_NVMDATA2 = 0x3010; + NVMDATA3 = 0x3014; +_NVMDATA3 = 0x3014; + NVMSRCADR = 0x3018; +_NVMSRCADR = 0x3018; +_NVMSRCADRbits = 0x3018; + NVMECCCON = 0x301C; +_NVMECCCON = 0x301C; +_NVMECCCONbits = 0x301C; + NVMECCSTAT = 0x3020; +_NVMECCSTAT = 0x3020; +_NVMECCSTATbits = 0x3020; + NVMECCFPTR = 0x3024; +_NVMECCFPTR = 0x3024; +_NVMECCFPTRbits = 0x3024; + NVMECCFADDR = 0x3028; +_NVMECCFADDR = 0x3028; +_NVMECCFADDRbits = 0x3028; + NVMECCEADDR = 0x302C; +_NVMECCEADDR = 0x302C; +_NVMECCEADDRbits = 0x302C; + NVMECCEDATA0 = 0x3030; +_NVMECCEDATA0 = 0x3030; + NVMECCEDATA1 = 0x3034; +_NVMECCEDATA1 = 0x3034; + NVMECCEDATA2 = 0x3038; +_NVMECCEDATA2 = 0x3038; + NVMECCEDATA3 = 0x303C; +_NVMECCEDATA3 = 0x303C; + NVMECCVAL = 0x3040; +_NVMECCVAL = 0x3040; +_NVMECCVALbits = 0x3040; + NVMECCSYND = 0x3044; +_NVMECCSYND = 0x3044; +_NVMECCSYNDbits = 0x3044; + NVMCRCCON = 0x3048; +_NVMCRCCON = 0x3048; +_NVMCRCCONbits = 0x3048; + NVMCRCST = 0x304C; +_NVMCRCST = 0x304C; +_NVMCRCSTbits = 0x304C; + NVMCRCEND = 0x3050; +_NVMCRCEND = 0x3050; +_NVMCRCENDbits = 0x3050; + NVMCRCSEED = 0x3054; +_NVMCRCSEED = 0x3054; + NVMCRCDATA = 0x3058; +_NVMCRCDATA = 0x3058; + OSCCTRL = 0x3100; +_OSCCTRL = 0x3100; +_OSCCTRLbits = 0x3100; + OSCCFG = 0x3104; +_OSCCFG = 0x3104; +_OSCCFGbits = 0x3104; + CLKFAIL = 0x3108; +_CLKFAIL = 0x3108; +_CLKFAILbits = 0x3108; + SCSFAIL = 0x310C; +_SCSFAIL = 0x310C; +_SCSFAILbits = 0x310C; + CLK1CON = 0x3118; +_CLK1CON = 0x3118; +_CLK1CONbits = 0x3118; + CLK1DIV = 0x311C; +_CLK1DIV = 0x311C; +_CLK1DIVbits = 0x311C; + CLK2CON = 0x3120; +_CLK2CON = 0x3120; +_CLK2CONbits = 0x3120; + CLK2DIV = 0x3124; +_CLK2DIV = 0x3124; +_CLK2DIVbits = 0x3124; + CLK3CON = 0x3128; +_CLK3CON = 0x3128; +_CLK3CONbits = 0x3128; + CLK3DIV = 0x312C; +_CLK3DIV = 0x312C; +_CLK3DIVbits = 0x312C; + CLK4CON = 0x3130; +_CLK4CON = 0x3130; +_CLK4CONbits = 0x3130; + CLK4DIV = 0x3134; +_CLK4DIV = 0x3134; +_CLK4DIVbits = 0x3134; + CLK5CON = 0x3138; +_CLK5CON = 0x3138; +_CLK5CONbits = 0x3138; + CLK5DIV = 0x313C; +_CLK5DIV = 0x313C; +_CLK5DIVbits = 0x313C; + CLK6CON = 0x3140; +_CLK6CON = 0x3140; +_CLK6CONbits = 0x3140; + CLK6DIV = 0x3144; +_CLK6DIV = 0x3144; +_CLK6DIVbits = 0x3144; + CLK7CON = 0x3148; +_CLK7CON = 0x3148; +_CLK7CONbits = 0x3148; + CLK7DIV = 0x314C; +_CLK7DIV = 0x314C; +_CLK7DIVbits = 0x314C; + CLK8CON = 0x3150; +_CLK8CON = 0x3150; +_CLK8CONbits = 0x3150; + CLK8DIV = 0x3154; +_CLK8DIV = 0x3154; +_CLK8DIVbits = 0x3154; + CLK9CON = 0x3158; +_CLK9CON = 0x3158; +_CLK9CONbits = 0x3158; + CLK9DIV = 0x315C; +_CLK9DIV = 0x315C; +_CLK9DIVbits = 0x315C; + CLK10CON = 0x3160; +_CLK10CON = 0x3160; +_CLK10CONbits = 0x3160; + CLK10DIV = 0x3164; +_CLK10DIV = 0x3164; +_CLK10DIVbits = 0x3164; + CLK11CON = 0x3168; +_CLK11CON = 0x3168; +_CLK11CONbits = 0x3168; + CLK11DIV = 0x316C; +_CLK11DIV = 0x316C; +_CLK11DIVbits = 0x316C; + CLK12CON = 0x3170; +_CLK12CON = 0x3170; +_CLK12CONbits = 0x3170; + CLK12DIV = 0x3174; +_CLK12DIV = 0x3174; +_CLK12DIVbits = 0x3174; + CLK13CON = 0x3178; +_CLK13CON = 0x3178; +_CLK13CONbits = 0x3178; + CLK13DIV = 0x317C; +_CLK13DIV = 0x317C; +_CLK13DIVbits = 0x317C; + CLK14CON = 0x3180; +_CLK14CON = 0x3180; +_CLK14CONbits = 0x3180; + CLK14DIV = 0x3184; +_CLK14DIV = 0x3184; +_CLK14DIVbits = 0x3184; + PLL1CON = 0x3188; +_PLL1CON = 0x3188; +_PLL1CONbits = 0x3188; + PLL1DIV = 0x318C; +_PLL1DIV = 0x318C; +_PLL1DIVbits = 0x318C; + VCO1DIV = 0x3190; +_VCO1DIV = 0x3190; +_VCO1DIVbits = 0x3190; + PLL2CON = 0x3194; +_PLL2CON = 0x3194; +_PLL2CONbits = 0x3194; + PLL2DIV = 0x3198; +_PLL2DIV = 0x3198; +_PLL2DIVbits = 0x3198; + VCO2DIV = 0x319C; +_VCO2DIV = 0x319C; +_VCO2DIVbits = 0x319C; + RCON = 0x31A0; +_RCON = 0x31A0; +_RCONbits = 0x31A0; + CLKDIAG = 0x31A4; +_CLKDIAG = 0x31A4; +_CLKDIAGbits = 0x31A4; + CM1CON = 0x3200; +_CM1CON = 0x3200; +_CM1CONbits = 0x3200; + CM1STAT = 0x3204; +_CM1STAT = 0x3204; +_CM1STATbits = 0x3204; + CM1WINPR = 0x3208; +_CM1WINPR = 0x3208; + CM1SEL = 0x320C; +_CM1SEL = 0x320C; +_CM1SELbits = 0x320C; + CM1BUF = 0x3210; +_CM1BUF = 0x3210; + CM1SAT = 0x3214; +_CM1SAT = 0x3214; + CM1HFAIL = 0x3218; +_CM1HFAIL = 0x3218; + CM1LFAIL = 0x321C; +_CM1LFAIL = 0x321C; + CM1HWARN = 0x3220; +_CM1HWARN = 0x3220; + CM1LWARN = 0x3224; +_CM1LWARN = 0x3224; + CM2CON = 0x3230; +_CM2CON = 0x3230; +_CM2CONbits = 0x3230; + CM2STAT = 0x3234; +_CM2STAT = 0x3234; +_CM2STATbits = 0x3234; + CM2WINPR = 0x3238; +_CM2WINPR = 0x3238; + CM2SEL = 0x323C; +_CM2SEL = 0x323C; +_CM2SELbits = 0x323C; + CM2BUF = 0x3240; +_CM2BUF = 0x3240; + CM2SAT = 0x3244; +_CM2SAT = 0x3244; + CM2HFAIL = 0x3248; +_CM2HFAIL = 0x3248; + CM2LFAIL = 0x324C; +_CM2LFAIL = 0x324C; + CM2HWARN = 0x3250; +_CM2HWARN = 0x3250; + CM2LWARN = 0x3254; +_CM2LWARN = 0x3254; + CM3CON = 0x3260; +_CM3CON = 0x3260; +_CM3CONbits = 0x3260; + CM3STAT = 0x3264; +_CM3STAT = 0x3264; +_CM3STATbits = 0x3264; + CM3WINPR = 0x3268; +_CM3WINPR = 0x3268; + CM3SEL = 0x326C; +_CM3SEL = 0x326C; +_CM3SELbits = 0x326C; + CM3BUF = 0x3270; +_CM3BUF = 0x3270; + CM3SAT = 0x3274; +_CM3SAT = 0x3274; + CM3HFAIL = 0x3278; +_CM3HFAIL = 0x3278; + CM3LFAIL = 0x327C; +_CM3LFAIL = 0x327C; + CM3HWARN = 0x3280; +_CM3HWARN = 0x3280; + CM3LWARN = 0x3284; +_CM3LWARN = 0x3284; + CM4CON = 0x3290; +_CM4CON = 0x3290; +_CM4CONbits = 0x3290; + CM4STAT = 0x3294; +_CM4STAT = 0x3294; +_CM4STATbits = 0x3294; + CM4WINPR = 0x3298; +_CM4WINPR = 0x3298; + CM4SEL = 0x329C; +_CM4SEL = 0x329C; +_CM4SELbits = 0x329C; + CM4BUF = 0x32A0; +_CM4BUF = 0x32A0; + CM4SAT = 0x32A4; +_CM4SAT = 0x32A4; + CM4HFAIL = 0x32A8; +_CM4HFAIL = 0x32A8; + CM4LFAIL = 0x32AC; +_CM4LFAIL = 0x32AC; + CM4HWARN = 0x32B0; +_CM4HWARN = 0x32B0; + CM4LWARN = 0x32B4; +_CM4LWARN = 0x32B4; + FRCTUN = 0x32C0; +_FRCTUN = 0x32C0; +_FRCTUNbits = 0x32C0; + BFRCTUN = 0x32C4; +_BFRCTUN = 0x32C4; +_BFRCTUNbits = 0x32C4; + WDTCON = 0x32C8; +_WDTCON = 0x32C8; +_WDTCONbits = 0x32C8; + RPCON = 0x32D0; +_RPCON = 0x32D0; +_RPCONbits = 0x32D0; + RPINR0 = 0x32D4; +_RPINR0 = 0x32D4; +_RPINR0bits = 0x32D4; + RPINR1 = 0x32D8; +_RPINR1 = 0x32D8; +_RPINR1bits = 0x32D8; + RPINR2 = 0x32DC; +_RPINR2 = 0x32DC; +_RPINR2bits = 0x32DC; + RPINR3 = 0x32E0; +_RPINR3 = 0x32E0; +_RPINR3bits = 0x32E0; + RPINR4 = 0x32E4; +_RPINR4 = 0x32E4; +_RPINR4bits = 0x32E4; + RPINR5 = 0x32E8; +_RPINR5 = 0x32E8; +_RPINR5bits = 0x32E8; + RPINR6 = 0x32EC; +_RPINR6 = 0x32EC; +_RPINR6bits = 0x32EC; + RPINR7 = 0x32F0; +_RPINR7 = 0x32F0; +_RPINR7bits = 0x32F0; + RPINR8 = 0x32F4; +_RPINR8 = 0x32F4; +_RPINR8bits = 0x32F4; + RPINR9 = 0x32F8; +_RPINR9 = 0x32F8; +_RPINR9bits = 0x32F8; + RPINR10 = 0x32FC; +_RPINR10 = 0x32FC; +_RPINR10bits = 0x32FC; + RPINR11 = 0x3300; +_RPINR11 = 0x3300; +_RPINR11bits = 0x3300; + RPINR12 = 0x3304; +_RPINR12 = 0x3304; +_RPINR12bits = 0x3304; + RPINR13 = 0x3308; +_RPINR13 = 0x3308; +_RPINR13bits = 0x3308; + RPINR14 = 0x330C; +_RPINR14 = 0x330C; +_RPINR14bits = 0x330C; + RPINR15 = 0x3310; +_RPINR15 = 0x3310; +_RPINR15bits = 0x3310; + RPINR16 = 0x3314; +_RPINR16 = 0x3314; +_RPINR16bits = 0x3314; + RPINR17 = 0x3318; +_RPINR17 = 0x3318; +_RPINR17bits = 0x3318; + RPINR18 = 0x331C; +_RPINR18 = 0x331C; +_RPINR18bits = 0x331C; + RPINR19 = 0x3320; +_RPINR19 = 0x3320; +_RPINR19bits = 0x3320; + RPINR20 = 0x3324; +_RPINR20 = 0x3324; +_RPINR20bits = 0x3324; + RPINR21 = 0x3328; +_RPINR21 = 0x3328; +_RPINR21bits = 0x3328; + RPINR22 = 0x332C; +_RPINR22 = 0x332C; +_RPINR22bits = 0x332C; + RPINR23 = 0x3330; +_RPINR23 = 0x3330; +_RPINR23bits = 0x3330; + RPINR24 = 0x3334; +_RPINR24 = 0x3334; +_RPINR24bits = 0x3334; + RPINR25 = 0x3338; +_RPINR25 = 0x3338; +_RPINR25bits = 0x3338; + RPINR26 = 0x333C; +_RPINR26 = 0x333C; +_RPINR26bits = 0x333C; + RPINR27 = 0x3340; +_RPINR27 = 0x3340; +_RPINR27bits = 0x3340; + RPOR0 = 0x3350; +_RPOR0 = 0x3350; +_RPOR0bits = 0x3350; + RPOR1 = 0x3354; +_RPOR1 = 0x3354; +_RPOR1bits = 0x3354; + RPOR2 = 0x3358; +_RPOR2 = 0x3358; +_RPOR2bits = 0x3358; + RPOR3 = 0x335C; +_RPOR3 = 0x335C; +_RPOR3bits = 0x335C; + RPOR4 = 0x3360; +_RPOR4 = 0x3360; +_RPOR4bits = 0x3360; + RPOR5 = 0x3364; +_RPOR5 = 0x3364; +_RPOR5bits = 0x3364; + RPOR6 = 0x3368; +_RPOR6 = 0x3368; +_RPOR6bits = 0x3368; + RPOR7 = 0x336C; +_RPOR7 = 0x336C; +_RPOR7bits = 0x336C; + RPOR8 = 0x3370; +_RPOR8 = 0x3370; +_RPOR8bits = 0x3370; + RPOR9 = 0x3374; +_RPOR9 = 0x3374; +_RPOR9bits = 0x3374; + RPOR10 = 0x3378; +_RPOR10 = 0x3378; +_RPOR10bits = 0x3378; + RPOR11 = 0x337C; +_RPOR11 = 0x337C; +_RPOR11bits = 0x337C; + RPOR12 = 0x3380; +_RPOR12 = 0x3380; +_RPOR12bits = 0x3380; + RPOR13 = 0x3384; +_RPOR13 = 0x3384; +_RPOR13bits = 0x3384; + RPOR14 = 0x3388; +_RPOR14 = 0x3388; +_RPOR14bits = 0x3388; + RPOR15 = 0x338C; +_RPOR15 = 0x338C; +_RPOR15bits = 0x338C; + RPOR16 = 0x3390; +_RPOR16 = 0x3390; +_RPOR16bits = 0x3390; + RPOR17 = 0x3394; +_RPOR17 = 0x3394; +_RPOR17bits = 0x3394; + RPOR18 = 0x3398; +_RPOR18 = 0x3398; +_RPOR18bits = 0x3398; + RPOR20 = 0x33A0; +_RPOR20 = 0x33A0; +_RPOR20bits = 0x33A0; + RPOR21 = 0x33A4; +_RPOR21 = 0x33A4; +_RPOR21bits = 0x33A4; + RPOR22 = 0x33A8; +_RPOR22 = 0x33A8; +_RPOR22bits = 0x33A8; + RPOR24 = 0x33B0; +_RPOR24 = 0x33B0; +_RPOR24bits = 0x33B0; + RPOR25 = 0x33B4; +_RPOR25 = 0x33B4; +_RPOR25bits = 0x33B4; + RPOR26 = 0x33B8; +_RPOR26 = 0x33B8; +_RPOR26bits = 0x33B8; + RPOR28 = 0x33C0; +_RPOR28 = 0x33C0; +_RPOR28bits = 0x33C0; + RPOR32 = 0x33D0; +_RPOR32 = 0x33D0; +_RPOR32bits = 0x33D0; + RPOR33 = 0x33D4; +_RPOR33 = 0x33D4; +_RPOR33bits = 0x33D4; + RPOR34 = 0x33D8; +_RPOR34 = 0x33D8; +_RPOR34bits = 0x33D8; + RPOR35 = 0x33DC; +_RPOR35 = 0x33DC; +_RPOR35bits = 0x33DC; + PTGCON = 0x3500; +_PTGCON = 0x3500; +_PTGCONbits = 0x3500; + PTGBTE = 0x3504; +_PTGBTE = 0x3504; + PTGHOLD = 0x3508; +_PTGHOLD = 0x3508; +_PTGHOLDbits = 0x3508; + PTGT0LIM = 0x350C; +_PTGT0LIM = 0x350C; +_PTGT0LIMbits = 0x350C; + PTGT1LIM = 0x3510; +_PTGT1LIM = 0x3510; +_PTGT1LIMbits = 0x3510; + PTGSDLIM = 0x3514; +_PTGSDLIM = 0x3514; +_PTGSDLIMbits = 0x3514; + PTGC0LIM = 0x3518; +_PTGC0LIM = 0x3518; +_PTGC0LIMbits = 0x3518; + PTGC1LIM = 0x351C; +_PTGC1LIM = 0x351C; +_PTGC1LIMbits = 0x351C; + PTGADJ = 0x3520; +_PTGADJ = 0x3520; +_PTGADJbits = 0x3520; + PTGL0 = 0x3524; +_PTGL0 = 0x3524; +_PTGL0bits = 0x3524; + PTGQPTR = 0x3528; +_PTGQPTR = 0x3528; +_PTGQPTRbits = 0x3528; + PTGQUE0 = 0x3530; +_PTGQUE0 = 0x3530; +_PTGQUE0bits = 0x3530; + PTGQUE1 = 0x3534; +_PTGQUE1 = 0x3534; +_PTGQUE1bits = 0x3534; + PTGQUE2 = 0x3538; +_PTGQUE2 = 0x3538; +_PTGQUE2bits = 0x3538; + PTGQUE3 = 0x353C; +_PTGQUE3 = 0x353C; +_PTGQUE3bits = 0x353C; + PTGQUE4 = 0x3540; +_PTGQUE4 = 0x3540; +_PTGQUE4bits = 0x3540; + PTGQUE5 = 0x3544; +_PTGQUE5 = 0x3544; +_PTGQUE5bits = 0x3544; + PTGQUE6 = 0x3548; +_PTGQUE6 = 0x3548; +_PTGQUE6bits = 0x3548; + PTGQUE7 = 0x354C; +_PTGQUE7 = 0x354C; +_PTGQUE7bits = 0x354C; + RAMXECCCON = 0x3580; +_RAMXECCCON = 0x3580; +_RAMXECCCONbits = 0x3580; + RAMXECCSTAT = 0x3584; +_RAMXECCSTAT = 0x3584; +_RAMXECCSTATbits = 0x3584; + RAMXECCFPTR = 0x3588; +_RAMXECCFPTR = 0x3588; +_RAMXECCFPTRbits = 0x3588; + RAMXECCFADDR = 0x358C; +_RAMXECCFADDR = 0x358C; + RAMXECCEADDR = 0x3590; +_RAMXECCEADDR = 0x3590; + RAMXECCEDATA = 0x3594; +_RAMXECCEDATA = 0x3594; + RAMXECCVAL = 0x3598; +_RAMXECCVAL = 0x3598; +_RAMXECCVALbits = 0x3598; + RAMXECCSYND = 0x359C; +_RAMXECCSYND = 0x359C; +_RAMXECCSYNDbits = 0x359C; + PWBXECCCON = 0x35A0; +_PWBXECCCON = 0x35A0; +_PWBXECCCONbits = 0x35A0; + PWBXECCSTAT = 0x35A4; +_PWBXECCSTAT = 0x35A4; +_PWBXECCSTATbits = 0x35A4; + PWBXECCFPTR = 0x35A8; +_PWBXECCFPTR = 0x35A8; +_PWBXECCFPTRbits = 0x35A8; + PWBXECCFADDR = 0x35AC; +_PWBXECCFADDR = 0x35AC; + PWBXECCEADDR = 0x35B0; +_PWBXECCEADDR = 0x35B0; + PWBXECCEDATA = 0x35B4; +_PWBXECCEDATA = 0x35B4; + PWBXECCVAL = 0x35B8; +_PWBXECCVAL = 0x35B8; +_PWBXECCVALbits = 0x35B8; + PWBXECCSYND = 0x35BC; +_PWBXECCSYND = 0x35BC; +_PWBXECCSYNDbits = 0x35BC; + RAMYECCCON = 0x35C0; +_RAMYECCCON = 0x35C0; +_RAMYECCCONbits = 0x35C0; + RAMYECCSTAT = 0x35C4; +_RAMYECCSTAT = 0x35C4; +_RAMYECCSTATbits = 0x35C4; + RAMYECCFPTR = 0x35C8; +_RAMYECCFPTR = 0x35C8; +_RAMYECCFPTRbits = 0x35C8; + RAMYECCFADDR = 0x35CC; +_RAMYECCFADDR = 0x35CC; + RAMYECCEADDR = 0x35D0; +_RAMYECCEADDR = 0x35D0; + RAMYECCEDATA = 0x35D4; +_RAMYECCEDATA = 0x35D4; + RAMYECCVAL = 0x35D8; +_RAMYECCVAL = 0x35D8; +_RAMYECCVALbits = 0x35D8; + RAMYECCSYND = 0x35DC; +_RAMYECCSYND = 0x35DC; +_RAMYECCSYNDbits = 0x35DC; + PWBYECCCON = 0x35E0; +_PWBYECCCON = 0x35E0; +_PWBYECCCONbits = 0x35E0; + PWBYECCSTAT = 0x35E4; +_PWBYECCSTAT = 0x35E4; +_PWBYECCSTATbits = 0x35E4; + PWBYECCFPTR = 0x35E8; +_PWBYECCFPTR = 0x35E8; +_PWBYECCFPTRbits = 0x35E8; + PWBYECCFADDR = 0x35EC; +_PWBYECCFADDR = 0x35EC; + PWBYECCEADDR = 0x35F0; +_PWBYECCEADDR = 0x35F0; + PWBYECCEDATA = 0x35F4; +_PWBYECCEDATA = 0x35F4; + PWBYECCVAL = 0x35F8; +_PWBYECCVAL = 0x35F8; +_PWBYECCVALbits = 0x35F8; + PWBYECCSYND = 0x35FC; +_PWBYECCSYND = 0x35FC; +_PWBYECCSYNDbits = 0x35FC; + ANSELA = 0x3640; +_ANSELA = 0x3640; +_ANSELAbits = 0x3640; + ODCA = 0x3644; +_ODCA = 0x3644; +_ODCAbits = 0x3644; + CNPUA = 0x3648; +_CNPUA = 0x3648; +_CNPUAbits = 0x3648; + CNPDA = 0x364C; +_CNPDA = 0x364C; +_CNPDAbits = 0x364C; + CNCONA = 0x3650; +_CNCONA = 0x3650; +_CNCONAbits = 0x3650; + CNEN0A = 0x3654; +_CNEN0A = 0x3654; +_CNEN0Abits = 0x3654; + CNEN1A = 0x3658; +_CNEN1A = 0x3658; +_CNEN1Abits = 0x3658; + ANSELB = 0x3664; +_ANSELB = 0x3664; +_ANSELBbits = 0x3664; + ODCB = 0x3668; +_ODCB = 0x3668; +_ODCBbits = 0x3668; + CNPUB = 0x366C; +_CNPUB = 0x366C; +_CNPUBbits = 0x366C; + CNPDB = 0x3670; +_CNPDB = 0x3670; +_CNPDBbits = 0x3670; + CNCONB = 0x3674; +_CNCONB = 0x3674; +_CNCONBbits = 0x3674; + CNEN0B = 0x3678; +_CNEN0B = 0x3678; +_CNEN0Bbits = 0x3678; + CNEN1B = 0x367C; +_CNEN1B = 0x367C; +_CNEN1Bbits = 0x367C; + ANSELC = 0x3688; +_ANSELC = 0x3688; + ODCC = 0x368C; +_ODCC = 0x368C; +_ODCCbits = 0x368C; + CNPUC = 0x3690; +_CNPUC = 0x3690; +_CNPUCbits = 0x3690; + CNPDC = 0x3694; +_CNPDC = 0x3694; +_CNPDCbits = 0x3694; + CNCONC = 0x3698; +_CNCONC = 0x3698; +_CNCONCbits = 0x3698; + CNEN0C = 0x369C; +_CNEN0C = 0x369C; +_CNEN0Cbits = 0x369C; + CNEN1C = 0x36A0; +_CNEN1C = 0x36A0; +_CNEN1Cbits = 0x36A0; + ANSELD = 0x36AC; +_ANSELD = 0x36AC; + ODCD = 0x36B0; +_ODCD = 0x36B0; +_ODCDbits = 0x36B0; + CNPUD = 0x36B4; +_CNPUD = 0x36B4; +_CNPUDbits = 0x36B4; + CNPDD = 0x36B8; +_CNPDD = 0x36B8; +_CNPDDbits = 0x36B8; + CNCOND = 0x36BC; +_CNCOND = 0x36BC; +_CNCONDbits = 0x36BC; + CNEN0D = 0x36C0; +_CNEN0D = 0x36C0; +_CNEN0Dbits = 0x36C0; + CNEN1D = 0x36C4; +_CNEN1D = 0x36C4; +_CNEN1Dbits = 0x36C4; + ANSELE = 0x36D0; +_ANSELE = 0x36D0; +_ANSELEbits = 0x36D0; + ODCE = 0x36D4; +_ODCE = 0x36D4; +_ODCEbits = 0x36D4; + CNPUE = 0x36D8; +_CNPUE = 0x36D8; +_CNPUEbits = 0x36D8; + CNPDE = 0x36DC; +_CNPDE = 0x36DC; +_CNPDEbits = 0x36DC; + CNCONE = 0x36E0; +_CNCONE = 0x36E0; +_CNCONEbits = 0x36E0; + CNEN0E = 0x36E4; +_CNEN0E = 0x36E4; +_CNEN0Ebits = 0x36E4; + CNEN1E = 0x36E8; +_CNEN1E = 0x36E8; +_CNEN1Ebits = 0x36E8; + ANSELF = 0x36F4; +_ANSELF = 0x36F4; +_ANSELFbits = 0x36F4; + ODCF = 0x36F8; +_ODCF = 0x36F8; +_ODCFbits = 0x36F8; + CNPUF = 0x36FC; +_CNPUF = 0x36FC; +_CNPUFbits = 0x36FC; + CNPDF = 0x3700; +_CNPDF = 0x3700; +_CNPDFbits = 0x3700; + CNCONF = 0x3704; +_CNCONF = 0x3704; +_CNCONFbits = 0x3704; + CNEN0F = 0x3708; +_CNEN0F = 0x3708; +_CNEN0Fbits = 0x3708; + CNEN1F = 0x370C; +_CNEN1F = 0x370C; +_CNEN1Fbits = 0x370C; + ANSELG = 0x3718; +_ANSELG = 0x3718; + ODCG = 0x371C; +_ODCG = 0x371C; +_ODCGbits = 0x371C; + CNPUG = 0x3720; +_CNPUG = 0x3720; +_CNPUGbits = 0x3720; + CNPDG = 0x3724; +_CNPDG = 0x3724; +_CNPDGbits = 0x3724; + CNCONG = 0x3728; +_CNCONG = 0x3728; +_CNCONGbits = 0x3728; + CNEN0G = 0x372C; +_CNEN0G = 0x372C; +_CNEN0Gbits = 0x372C; + CNEN1G = 0x3730; +_CNEN1G = 0x3730; +_CNEN1Gbits = 0x3730; + ANSELH = 0x373C; +_ANSELH = 0x373C; + ODCH = 0x3740; +_ODCH = 0x3740; +_ODCHbits = 0x3740; + CNPUH = 0x3744; +_CNPUH = 0x3744; +_CNPUHbits = 0x3744; + CNPDH = 0x3748; +_CNPDH = 0x3748; +_CNPDHbits = 0x3748; + CNCONH = 0x374C; +_CNCONH = 0x374C; +_CNCONHbits = 0x374C; + CNEN0H = 0x3750; +_CNEN0H = 0x3750; +_CNEN0Hbits = 0x3750; + CNEN1H = 0x3754; +_CNEN1H = 0x3754; +_CNEN1Hbits = 0x3754; + DMTCON = 0x3A00; +_DMTCON = 0x3A00; +_DMTCONbits = 0x3A00; + DMTPRECLR = 0x3A04; +_DMTPRECLR = 0x3A04; +_DMTPRECLRbits = 0x3A04; + DMTCLR = 0x3A08; +_DMTCLR = 0x3A08; +_DMTCLRbits = 0x3A08; + DMTSTAT = 0x3A0C; +_DMTSTAT = 0x3A0C; +_DMTSTATbits = 0x3A0C; + DMTCNT = 0x3A10; +_DMTCNT = 0x3A10; + PSCNT = 0x3A14; +_PSCNT = 0x3A14; + PSINTV = 0x3A18; +_PSINTV = 0x3A18; + PPPC = 0x3A1C; +_PPPC = 0x3A1C; +_PPPCbits = 0x3A1C; + PPC = 0x3A20; +_PPC = 0x3A20; +_PPCbits = 0x3A20; + PMD1 = 0x3A44; +_PMD1 = 0x3A44; +_PMD1bits = 0x3A44; + PMD2 = 0x3A48; +_PMD2 = 0x3A48; +_PMD2bits = 0x3A48; + PMD3 = 0x3A4C; +_PMD3 = 0x3A4C; +_PMD3bits = 0x3A4C; + PMD4 = 0x3A50; +_PMD4 = 0x3A50; +_PMD4bits = 0x3A50; + CLC1CON = 0x3A60; +_CLC1CON = 0x3A60; +_CLC1CONbits = 0x3A60; + CLC1SEL = 0x3A64; +_CLC1SEL = 0x3A64; +_CLC1SELbits = 0x3A64; + CLC1GLS = 0x3A68; +_CLC1GLS = 0x3A68; +_CLC1GLSbits = 0x3A68; + CLC2CON = 0x3A70; +_CLC2CON = 0x3A70; +_CLC2CONbits = 0x3A70; + CLC2SEL = 0x3A74; +_CLC2SEL = 0x3A74; +_CLC2SELbits = 0x3A74; + CLC2GLS = 0x3A78; +_CLC2GLS = 0x3A78; +_CLC2GLSbits = 0x3A78; + CLC3CON = 0x3A80; +_CLC3CON = 0x3A80; +_CLC3CONbits = 0x3A80; + CLC3SEL = 0x3A84; +_CLC3SEL = 0x3A84; +_CLC3SELbits = 0x3A84; + CLC3GLS = 0x3A88; +_CLC3GLS = 0x3A88; +_CLC3GLSbits = 0x3A88; + CLC4CON = 0x3A90; +_CLC4CON = 0x3A90; +_CLC4CONbits = 0x3A90; + CLC4SEL = 0x3A94; +_CLC4SEL = 0x3A94; +_CLC4SELbits = 0x3A94; + CLC4GLS = 0x3A98; +_CLC4GLS = 0x3A98; +_CLC4GLSbits = 0x3A98; + CLC5CON = 0x3AA0; +_CLC5CON = 0x3AA0; +_CLC5CONbits = 0x3AA0; + CLC5SEL = 0x3AA4; +_CLC5SEL = 0x3AA4; +_CLC5SELbits = 0x3AA4; + CLC5GLS = 0x3AA8; +_CLC5GLS = 0x3AA8; +_CLC5GLSbits = 0x3AA8; + CLC6CON = 0x3AB0; +_CLC6CON = 0x3AB0; +_CLC6CONbits = 0x3AB0; + CLC6SEL = 0x3AB4; +_CLC6SEL = 0x3AB4; +_CLC6SELbits = 0x3AB4; + CLC6GLS = 0x3AB8; +_CLC6GLS = 0x3AB8; +_CLC6GLSbits = 0x3AB8; + CLC7CON = 0x3AC0; +_CLC7CON = 0x3AC0; +_CLC7CONbits = 0x3AC0; + CLC7SEL = 0x3AC4; +_CLC7SEL = 0x3AC4; +_CLC7SELbits = 0x3AC4; + CLC7GLS = 0x3AC8; +_CLC7GLS = 0x3AC8; +_CLC7GLSbits = 0x3AC8; + CLC8CON = 0x3AD0; +_CLC8CON = 0x3AD0; +_CLC8CONbits = 0x3AD0; + CLC8SEL = 0x3AD4; +_CLC8SEL = 0x3AD4; +_CLC8SELbits = 0x3AD4; + CLC8GLS = 0x3AD8; +_CLC8GLS = 0x3AD8; +_CLC8GLSbits = 0x3AD8; + CLC9CON = 0x3AE0; +_CLC9CON = 0x3AE0; +_CLC9CONbits = 0x3AE0; + CLC9SEL = 0x3AE4; +_CLC9SEL = 0x3AE4; +_CLC9SELbits = 0x3AE4; + CLC9GLS = 0x3AE8; +_CLC9GLS = 0x3AE8; +_CLC9GLSbits = 0x3AE8; + CLC10CON = 0x3AF0; +_CLC10CON = 0x3AF0; +_CLC10CONbits = 0x3AF0; + CLC10SEL = 0x3AF4; +_CLC10SEL = 0x3AF4; +_CLC10SELbits = 0x3AF4; + CLC10GLS = 0x3AF8; +_CLC10GLS = 0x3AF8; +_CLC10GLSbits = 0x3AF8; + MBISTCON = 0x3B00; +_MBISTCON = 0x3B00; +_MBISTCONbits = 0x3B00; + IBIASCON = 0x3B04; +_IBIASCON = 0x3B04; +_IBIASCONbits = 0x3B04; + AMP1CON1 = 0x3B08; +_AMP1CON1 = 0x3B08; +_AMP1CON1bits = 0x3B08; + AMP1CON2 = 0x3B0C; +_AMP1CON2 = 0x3B0C; +_AMP1CON2bits = 0x3B0C; + AMP2CON1 = 0x3B10; +_AMP2CON1 = 0x3B10; +_AMP2CON1bits = 0x3B10; + AMP2CON2 = 0x3B14; +_AMP2CON2 = 0x3B14; +_AMP2CON2bits = 0x3B14; + AMP3CON1 = 0x3B18; +_AMP3CON1 = 0x3B18; +_AMP3CON1bits = 0x3B18; + AMP3CON2 = 0x3B1C; +_AMP3CON2 = 0x3B1C; +_AMP3CON2bits = 0x3B1C; + UREFCON = 0x3B20; +_UREFCON = 0x3B20; +_UREFCONbits = 0x3B20; + CAMCON = 0x7A8000; +_CAMCON = 0x7A8000; +_CAMCONbits = 0x7A8000; + SDATACMD0 = 0x7C3000; +_SDATACMD0 = 0x7C3000; +_SDATACMD0bits = 0x7C3000; + SDATACMD1 = 0x7C3004; +_SDATACMD1 = 0x7C3004; +_SDATACMD1bits = 0x7C3004; + SDATACMD2 = 0x7C3008; +_SDATACMD2 = 0x7C3008; +_SDATACMD2bits = 0x7C3008; + SDATACMD3 = 0x7C300C; +_SDATACMD3 = 0x7C300C; +_SDATACMD3bits = 0x7C300C; + SDATACMD4 = 0x7C3010; +_SDATACMD4 = 0x7C3010; +_SDATACMD4bits = 0x7C3010; + SDATACMD5 = 0x7C3014; +_SDATACMD5 = 0x7C3014; +_SDATACMD5bits = 0x7C3014; + SDATACMD6 = 0x7C3018; +_SDATACMD6 = 0x7C3018; +_SDATACMD6bits = 0x7C3018; + SDATACMD7 = 0x7C301C; +_SDATACMD7 = 0x7C301C; +_SDATACMD7bits = 0x7C301C; + SDATACMD8 = 0x7C3020; +_SDATACMD8 = 0x7C3020; +_SDATACMD8bits = 0x7C3020; + SDATACMD9 = 0x7C3024; +_SDATACMD9 = 0x7C3024; +_SDATACMD9bits = 0x7C3024; + SDATACMD10 = 0x7C3028; +_SDATACMD10 = 0x7C3028; +_SDATACMD10bits = 0x7C3028; + SDATACMD11 = 0x7C302C; +_SDATACMD11 = 0x7C302C; +_SDATACMD11bits = 0x7C302C; + SDATACMD12 = 0x7C3030; +_SDATACMD12 = 0x7C3030; +_SDATACMD12bits = 0x7C3030; + SDATACMD13 = 0x7C3034; +_SDATACMD13 = 0x7C3034; +_SDATACMD13bits = 0x7C3034; + SDATACMD14 = 0x7C3038; +_SDATACMD14 = 0x7C3038; +_SDATACMD14bits = 0x7C3038; + SDATACMD15 = 0x7C303C; +_SDATACMD15 = 0x7C303C; +_SDATACMD15bits = 0x7C303C; + SMATHCMD0 = 0x7C3040; +_SMATHCMD0 = 0x7C3040; +_SMATHCMD0bits = 0x7C3040; + SMATHCMD1 = 0x7C3044; +_SMATHCMD1 = 0x7C3044; +_SMATHCMD1bits = 0x7C3044; + SMATHCMD2 = 0x7C3048; +_SMATHCMD2 = 0x7C3048; +_SMATHCMD2bits = 0x7C3048; + SMATHCMD3 = 0x7C304C; +_SMATHCMD3 = 0x7C304C; +_SMATHCMD3bits = 0x7C304C; + SMATHCMD4 = 0x7C3050; +_SMATHCMD4 = 0x7C3050; +_SMATHCMD4bits = 0x7C3050; + SMATHCMD5 = 0x7C3054; +_SMATHCMD5 = 0x7C3054; +_SMATHCMD5bits = 0x7C3054; + SMATHCMD6 = 0x7C3058; +_SMATHCMD6 = 0x7C3058; +_SMATHCMD6bits = 0x7C3058; + SMATHCMD7 = 0x7C305C; +_SMATHCMD7 = 0x7C305C; +_SMATHCMD7bits = 0x7C305C; + SMATHCMD8 = 0x7C3060; +_SMATHCMD8 = 0x7C3060; +_SMATHCMD8bits = 0x7C3060; + SMATHCMD9 = 0x7C3064; +_SMATHCMD9 = 0x7C3064; +_SMATHCMD9bits = 0x7C3064; + SMATHCMD10 = 0x7C3068; +_SMATHCMD10 = 0x7C3068; +_SMATHCMD10bits = 0x7C3068; + SMATHCMD11 = 0x7C306C; +_SMATHCMD11 = 0x7C306C; +_SMATHCMD11bits = 0x7C306C; + SMATHCMD12 = 0x7C3070; +_SMATHCMD12 = 0x7C3070; +_SMATHCMD12bits = 0x7C3070; + SMATHCMD13 = 0x7C3074; +_SMATHCMD13 = 0x7C3074; +_SMATHCMD13bits = 0x7C3074; + SMATHCMD14 = 0x7C3078; +_SMATHCMD14 = 0x7C3078; +_SMATHCMD14bits = 0x7C3078; + SMATHCMD15 = 0x7C307C; +_SMATHCMD15 = 0x7C307C; +_SMATHCMD15bits = 0x7C307C; + SDATAMAP = 0x7C3080; +_SDATAMAP = 0x7C3080; +_SDATAMAPbits = 0x7C3080; + SMATHMAP = 0x7C3084; +_SMATHMAP = 0x7C3084; +_SMATHMAPbits = 0x7C3084; +/* +** ======= Base Addresses for Various Peripherals and ACC ====== +*/ + + SPI1 = 0x1808; +_SPI1 = 0x1808; + SPI2 = 0x1828; +_SPI2 = 0x1828; + SPI3 = 0x1848; +_SPI3 = 0x1848; + SPI4 = 0x1868; +_SPI4 = 0x1868; \ No newline at end of file diff --git a/soc/microchip/dspic33/dspic33a/pinctrl_soc.h b/soc/microchip/dspic33/dspic33a/pinctrl_soc.h new file mode 100644 index 0000000000000..9283dcdaed581 --- /dev/null +++ b/soc/microchip/dspic33/dspic33a/pinctrl_soc.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_DSPIC33A_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_DSPIC33A_PINCTRL_SOC_H_ + +#include +#include + +#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106) +#include +#elif defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512) +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct pinctrl_soc_pin { + uint32_t pinmux; +} pinctrl_soc_pin_t; + +/* Extract pinmux from DT */ +#define Z_PINCTRL_DSPIC33_PINMUX_INIT(node_id) (uint32_t)(DT_PROP(node_id, pinmux)) + +/* For dsPIC33, no extra config bits for now → only pinmux */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + {.pinmux = Z_PINCTRL_DSPIC33_PINMUX_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx))}, + +/* Expand each pin in the list */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)} + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_DSPIC33A_PINCTRL_SOC_H_ */ diff --git a/soc/microchip/dspic33/soc.yml b/soc/microchip/dspic33/soc.yml index 7df418defe8dc..560781a1dafe8 100644 --- a/soc/microchip/dspic33/soc.yml +++ b/soc/microchip/dspic33/soc.yml @@ -3,7 +3,6 @@ family: series: - name: dspic33a socs: + - name: p33ak512mps512 - name: p33ak128mc106 - name: p33ak256mc506 - cpuclusters: - - name: cpu0 diff --git a/subsys/debug/thread_info.c b/subsys/debug/thread_info.c index bcd58211e3bb8..b042e82e2e6cc 100644 --- a/subsys/debug/thread_info.c +++ b/subsys/debug/thread_info.c @@ -85,6 +85,9 @@ const size_t _kernel_thread_info_offsets[] = { #elif defined(CONFIG_ARCH_POSIX) [THREAD_INFO_OFFSET_T_STACK_PTR] = offsetof(struct k_thread, callee_saved.thread_status), +#elif defined(CONFIG_DSPIC) + [THREAD_INFO_OFFSET_T_STACK_PTR] = offsetof(struct k_thread, + callee_saved.stack), #elif defined(CONFIG_XTENSA) /* Xtensa does not store stack pointers inside thread objects. * The registers are saved in thread stack where there is diff --git a/subsys/testsuite/include/zephyr/interrupt_util.h b/subsys/testsuite/include/zephyr/interrupt_util.h index 78dba10f4f169..82f6d68af689b 100644 --- a/subsys/testsuite/include/zephyr/interrupt_util.h +++ b/subsys/testsuite/include/zephyr/interrupt_util.h @@ -233,6 +233,14 @@ static inline void trigger_irq(int irq) z_mips_enter_irq(irq); } +#elif defined(CONFIG_DSPIC) +extern void z_dspic_enter_irq(int); + +static inline void trigger_irq(int irq) +{ + z_dspic_enter_irq(irq); +} + #elif defined(CONFIG_CPU_CORTEX_R5) && defined(CONFIG_VIM) extern void z_vim_arm_enter_irq(int);