rp2xxx: Implement flashless flash hal (#705)

tact1m4n3 · web-flow · commit 38809864a6b4 · 2025-10-11T11:48:19.000-07:00
diff --git a/examples/raspberrypi/rp2xxx/build.zig b/examples/raspberrypi/rp2xxx/build.zig
@@ -25,11 +25,14 @@ pub fn build(b: *std.Build) void {
         .{ .target = raspberrypi.pico, .name = "pico_hd44780", .file = "src/rp2040_only/hd44780.zig" },
         .{ .target = raspberrypi.pico, .name = "pico_pcf8574", .file = "src/rp2040_only/pcf8574.zig" },
         .{ .target = raspberrypi.pico, .name = "pico_i2c_slave", .file = "src/rp2040_only/i2c_slave.zig" },
+
         .{ .target = raspberrypi.pico_flashless, .name = "pico_flashless_blinky", .file = "src/blinky.zig" },
+        .{ .target = raspberrypi.pico_flashless, .name = "pico_flashless_flash-program", .file = "src/rp2040_only/flash_program.zig" },
+
         .{ .target = raspberrypi.pico2_arm_flashless, .name = "pico2_arm_flashless_blinky", .file = "src/blinky.zig" },
         .{ .target = raspberrypi.pico2_riscv_flashless, .name = "pico2_riscv_flashless_blinky", .file = "src/blinky.zig" },
-        .{ .target = raspberrypi.pico2_arm_flashless, .name = "pico2_arm_flashless_system_timer", .file = "src/system_timer.zig" },
-        .{ .target = raspberrypi.pico2_riscv_flashless, .name = "pico2_riscv_flashless_system_timer", .file = "src/system_timer.zig" },
+        .{ .target = raspberrypi.pico2_arm_flashless, .name = "pico2_arm_flashless_system-timer", .file = "src/system_timer.zig" },
+        .{ .target = raspberrypi.pico2_riscv_flashless, .name = "pico2_riscv_flashless_system-timer", .file = "src/system_timer.zig" },
 
         .{ .target = raspberrypi.pico2_arm, .name = "pico2_arm_random_data", .file = "src/rp2350_only/random_data.zig" },
         .{ .target = raspberrypi.pico2_riscv, .name = "pico2_riscv_random_data", .file = "src/rp2350_only/random_data.zig" },
diff --git a/port/raspberrypi/rp2xxx/build.zig b/port/raspberrypi/rp2xxx/build.zig
@@ -197,6 +197,8 @@ pub fn init(dep: *std.Build.Dependency) Self {
                         .name = "RaspberryPi Pico (ram image)",
                         .url = "https://www.raspberrypi.com/products/raspberry-pi-pico/",
                         .root_source_file = b.path("src/boards/raspberry_pi_pico.zig"),
+                        // needed by the flash hal
+                        .imports = rp2040_bootrom_imports,
                     },
                 }),
                 .pico2_arm = chip_rp2350_arm.derive(.{
diff --git a/port/raspberrypi/rp2xxx/src/boards/raspberry_pi_pico.zig b/port/raspberrypi/rp2xxx/src/boards/raspberry_pi_pico.zig
@@ -1,5 +1,7 @@
 pub const xosc_freq = 12_000_000;
 
+pub const bootrom = @import("shared/rp2040_bootrom.zig");
+
 comptime {
-    _ = @import("shared/bootrom.zig");
+    _ = bootrom;
 }
diff --git a/port/raspberrypi/rp2xxx/src/boards/shared/bootrom.zig b/port/raspberrypi/rp2xxx/src/boards/shared/bootrom.zig
diff --git a/port/raspberrypi/rp2xxx/src/boards/shared/rp2040_bootrom.zig b/port/raspberrypi/rp2xxx/src/boards/shared/rp2040_bootrom.zig
@@ -0,0 +1,43 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const chip = microzig.hal.compatibility.chip;
+
+comptime {
+    if (chip == .RP2040 and !microzig.config.ram_image) {
+        _ = bootloader_data;
+    }
+}
+
+/// Raw stage2 bootrom
+pub const stage2_rom: []const u8 = @embedFile("bootloader");
+
+pub export const bootloader_data: [256]u8 linksection(".boot2") = blk: {
+    @setEvalBranchQuota(10_000);
+
+    var bootrom: [256]u8 = @splat(0xFF);
+    @memcpy(bootrom[0..stage2_rom.len], stage2_rom);
+
+    // 2.8.1.3.1. Checksum
+    // The last four bytes of the image loaded from flash (which we hope is a valid flash second stage) are a CRC32 checksum
+    // of the first 252 bytes. The parameters of the checksum are:
+    // • Polynomial: 0x04c11db7
+    // • Input reflection: no
+    // • Output reflection: no
+    // • Initial value: 0xffffffff
+    // • Final XOR: 0x00000000
+    // • Checksum value appears as little-endian integer at end of image
+    // The Bootrom makes 128 attempts of approximately 4ms each for a total of approximately 0.5 seconds before giving up
+    // and dropping into USB code to load and checksum the second stage with varying SPI parameters. If it sees a checksum
+    // pass it will immediately jump into the 252-byte payload which contains the flash second stage.
+    const Hash = std.hash.crc.Crc(u32, .{
+        .polynomial = 0x04c11db7,
+        .initial = 0xffffffff,
+        .reflect_input = false,
+        .reflect_output = false,
+        .xor_output = 0x00000000,
+    });
+
+    std.mem.writeInt(u32, bootrom[252..256], Hash.hash(bootrom[0..252]), .little);
+
+    break :blk bootrom;
+};
diff --git a/port/raspberrypi/rp2xxx/src/boards/waveshare_rp2040_eth.zig b/port/raspberrypi/rp2xxx/src/boards/waveshare_rp2040_eth.zig
@@ -1,5 +1,7 @@
 pub const xosc_freq = 12_000_000;
 
+pub const bootrom = @import("shared/rp2040_bootrom.zig");
+
 comptime {
-    _ = @import("shared/bootrom.zig");
+    _ = bootrom;
 }
diff --git a/port/raspberrypi/rp2xxx/src/boards/waveshare_rp2040_matrix.zig b/port/raspberrypi/rp2xxx/src/boards/waveshare_rp2040_matrix.zig
@@ -1,5 +1,7 @@
 pub const xosc_freq = 12_000_000;
 
+pub const bootrom = @import("shared/rp2040_bootrom.zig");
+
 comptime {
-    _ = @import("shared/bootrom.zig");
+    _ = bootrom;
 }
diff --git a/port/raspberrypi/rp2xxx/src/boards/waveshare_rp2040_plus_16m.zig b/port/raspberrypi/rp2xxx/src/boards/waveshare_rp2040_plus_16m.zig
@@ -1,5 +1,7 @@
 pub const xosc_freq = 12_000_000;
 
+pub const bootrom = @import("shared/rp2040_bootrom.zig");
+
 comptime {
-    _ = @import("shared/bootrom.zig");
+    _ = bootrom;
 }
diff --git a/port/raspberrypi/rp2xxx/src/boards/waveshare_rp2040_plus_4m.zig b/port/raspberrypi/rp2xxx/src/boards/waveshare_rp2040_plus_4m.zig
@@ -1,5 +1,7 @@
 pub const xosc_freq = 12_000_000;
 
+pub const bootrom = @import("shared/rp2040_bootrom.zig");
+
 comptime {
-    _ = @import("shared/bootrom.zig");
+    _ = bootrom;
 }
diff --git a/port/raspberrypi/rp2xxx/src/hal.zig b/port/raspberrypi/rp2xxx/src/hal.zig
@@ -97,7 +97,7 @@ pub inline fn init() void {
 const is_fpu_used: bool = builtin.abi.float() == .hard;
 
 /// Allows user to easily swap in their own clock config while still
-/// using the reccomended initialization sequence
+/// using the recommended initialization sequence
 pub fn init_sequence(comptime clock_cfg: clocks.config.Global) void {
     if (compatibility.chip == .RP2350 and
         compatibility.arch == .arm)
diff --git a/port/raspberrypi/rp2xxx/src/hal/flash.zig b/port/raspberrypi/rp2xxx/src/hal/flash.zig
@@ -20,29 +20,30 @@ pub const BLOCK_SIZE = 65536;
 pub const XIP_BASE = 0x10000000;
 
 /// Flash code related to the second stage boot loader
-pub const boot2 = struct {
+pub const boot2 = if (!microzig.config.ram_image) struct {
     /// Size of the second stage bootloader in words
     const BOOT2_SIZE_WORDS = 64;
 
     /// Buffer for the second stage bootloader
     ///
     /// The only job of the second stage bootloader is to configure the SSI and
-    /// the external flash for the best possible execute-in-place (XIP) performance.
-    /// Until the SSI is correctly configured for the attached flash device, it's not
-    /// possible to access flash via the XIP address window, i.e., we have to copy
-    /// the bootloader into sram before calling `rom.flash_exit_xip`. This is required
-    /// if we want to erase and/or write to flash.
+    /// the external flash for the best possible execute-in-place (XIP)
+    /// performance. Until the SSI is correctly configured for the attached
+    /// flash device, it's not possible to access flash via the XIP address
+    /// window, i.e., we have to copy the bootloader into sram before calling
+    /// `rom.flash_exit_xip`. This is required if we want to erase and/or write
+    /// to flash.
     ///
-    /// At the end we can then just make a subroutine call to copyout, to configure
-    /// the SSI and flash. The second stage bootloader will return to the calling function
-    /// if a return address is provided in `lr`.
+    /// At the end we can then just make a subroutine call to copyout, to
+    /// configure the SSI and flash. The second stage bootloader will return to
+    /// the calling function if a return address is provided in `lr`.
     var copyout: [BOOT2_SIZE_WORDS]u32 = undefined;
     var copyout_valid: bool = false;
 
     /// Copy the 2nd stage bootloader into memory
     ///
-    /// This is required by `_range_erase` and `_range_program` so we can later setup
-    /// XIP via the second stage bootloader.
+    /// This is required by `_range_erase` and `_range_program` so we can later
+    /// setup XIP via the second stage bootloader.
     pub export fn flash_init() linksection(".ram_text") void {
         if (copyout_valid) return;
         const bootloader = @as([*]u32, @ptrFromInt(XIP_BASE));
@@ -53,8 +54,8 @@ pub const boot2 = struct {
         copyout_valid = true;
     }
 
-    /// Configure the SSI and the external flash for XIP by calling the second stage
-    /// bootloader that was copied out to `copyout`.
+    /// Configure the SSI and the external flash for XIP by calling the second
+    /// stage bootloader that was copied out to `copyout`.
     pub export fn flash_enable_xip() linksection(".ram_text") void {
         // The bootloader is in thumb mode
         asm volatile (
@@ -64,12 +65,27 @@ pub const boot2 = struct {
             : [copyout] "{r0}" (@intFromPtr(&copyout)),
             : .{ .r0 = true, .r14 = true });
     }
+} else struct {
+    // no op
+    pub inline fn flash_init() linksection(".ram_text") void {}
+
+    /// Configure the SSI and the external flash for XIP by calling the second
+    /// stage bootloader embedded into RAM.
+    pub inline fn flash_enable_xip() linksection(".ram_text") void {
+        // The bootloader is in thumb mode
+        asm volatile (
+            \\adds r0, #1
+            \\blx r0
+            :
+            : [copyout] "{r0}" (@intFromPtr(microzig.board.bootrom.stage2_rom.ptr)),
+            : .{ .r0 = true, .r14 = true });
+    }
 };
 
 /// Erase count bytes starting at offset (offset from start of flash)
 ///
-/// The offset must be aligned to a 4096-byte sector, and count must
-/// be a multiple of 4096 bytes!
+/// The offset must be aligned to a 4096-byte sector, and count must be a
+/// multiple of 4096 bytes!
 pub inline fn range_erase(offset: u32, count: u32) void {
     // Do not inline `_range_erase`!
     @call(.never_inline, _range_erase, .{ offset, count });
@@ -114,8 +130,8 @@ export fn _range_program(offset: u32, data: [*]const u8, len: usize) linksection
     boot2.flash_enable_xip();
 }
 
-/// Force the chip select using IO overrides, in case RAM-resident IRQs
-/// are still running, and the FIFO bottoms out
+/// Force the chip select using IO overrides, in case RAM-resident IRQs are
+/// still running, and the FIFO bottoms out
 pub inline fn force_cs(high: bool) void {
     @call(.never_inline, _force_cs, .{high});
 }
@@ -135,8 +151,8 @@ fn _force_cs(high: bool) linksection(".ram_text") void {
 
 /// Execute a command on the flash chip
 ///
-/// Configures flash for serial mode operation, sends a command, receives response
-/// and then configures flash back to XIP mode
+/// Configures flash for serial mode operation, sends a command, receives
+/// response and then configures flash back to XIP mode
 pub inline fn cmd(tx_buf: []const u8, rx_buf: []u8) void {
     @call(.never_inline, _cmd, .{ tx_buf, rx_buf });
 }

Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,7 @@`
`1`	`1`	`pub const xosc_freq = 12_000_000;`
`2`	`2`
	`3`	`+pub const bootrom = @import("shared/rp2040_bootrom.zig");`
	`4`	`+`
`3`	`5`	`comptime {`
`4`		`- _ = @import("shared/bootrom.zig");`
	`6`	`+ _ = bootrom;`
`5`	`7`	`}`