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RISC-V: Add "lp64e" ABI support
Since RV32E and RV64E are now ratified, this commit prepares the ABI support for LP64E (LP64 with reduced GPRs). gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Update the error message. (md_parse_option): Accept "lp64e". * doc/c-riscv.texi: Update the documentation to allow "lp64e". * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Change error message. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l: Likewise.
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lines changed

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gas/config/tc-riscv.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -386,7 +386,7 @@ riscv_set_abi_by_arch (void)
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as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
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if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi)
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as_bad ("only the ilp32e ABI is supported for e extension");
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as_bad ("only ilp32e/lp64e ABI are supported for e extension");
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if (float_abi == FLOAT_ABI_SINGLE
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&& !riscv_subset_supports (&riscv_rps_as, "f"))
@@ -3906,6 +3906,8 @@ md_parse_option (int c, const char *arg)
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riscv_set_abi (32, FLOAT_ABI_QUAD, false);
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else if (strcmp (arg, "lp64") == 0)
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riscv_set_abi (64, FLOAT_ABI_SOFT, false);
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else if (strcmp (arg, "lp64e") == 0)
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riscv_set_abi (64, FLOAT_ABI_SOFT, true);
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else if (strcmp (arg, "lp64f") == 0)
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riscv_set_abi (64, FLOAT_ABI_SINGLE, false);
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else if (strcmp (arg, "lp64d") == 0)

gas/doc/c-riscv.texi

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -65,9 +65,8 @@ aren't set, then assembler will check the default configure setting
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@item -mabi=ABI
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Selects the ABI, which is either "ilp32" or "lp64", optionally followed
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by "f", "d", or "q" to indicate single-precision, double-precision, or
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quad-precision floating-point calling convention, or none to indicate
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the soft-float calling convention. Also, "ilp32" can optionally be followed
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by "e" to indicate the RVE ABI, which is always soft-float.
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quad-precision floating-point calling convention, or none or "e" to indicate
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the soft-float calling convention ("e" indicates a soft-float RVE ABI).
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@cindex @samp{-mrelax} option, RISC-V
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@item -mrelax
Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
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.*Assembler messages:
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.*Error: can't have 64-bit ABI on 32-bit ISA
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.*Error: only the ilp32e ABI is supported for e extension
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.*Error: only ilp32e/lp64e ABI are supported for e extension
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.*Error: ilp32d/lp64d ABI can't be used when d extension isn't supported
Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
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.*Assembler messages:
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.*Error: can't have 64-bit ABI on 32-bit ISA
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.*Error: only the ilp32e ABI is supported for e extension
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.*Error: only ilp32e/lp64e ABI are supported for e extension
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.*Error: ilp32f/lp64f ABI can't be used when f extension isn't supported
Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
.*Assembler messages:
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.*Error: can't have 64-bit ABI on 32-bit ISA
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.*Error: only the ilp32e ABI is supported for e extension
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.*Error: only ilp32e/lp64e ABI are supported for e extension
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.*Error: ilp32q/lp64q ABI can't be used when q extension isn't supported

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