RISC-V: Add 'Zicntr' and 'Zihpm' support with compatibility measures

This commit adds support for 'Zicntr' and 'Zihpm' extensions (version 2.0).

However, because GNU Binutils handled those as a part of 'I' and there was
a time when a ratified specification did split counters from the 'I'
extension without separate extension names, we need to take care of
possible compatibility issues.

So, if 'Zicntr' pseudoinstructions are used without that extension,
it generates not an error but a warning.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implications related
	to counter extensions.
	(riscv_supported_std_z_ext): Add 'Zicntr' and 'Zihpm' extensions.
	(riscv_parse_add_subset): Add "zicntr" and "zihpm" to exceptions
	to recognize on older ISAs if there's no version number.
	(riscv_multi_subset_supports, riscv_multi_subset_supports_ext):
	Add support for the 'Zicntr' extension with compatibility measure.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add new CSR classes
	corresponding 'Zicntr' and 'Zihpm' extensions.
	(riscv_csr_address): Add handling for new CSR classes.
	(riscv_ip): Raise a warning if a 'Zicntr' pseudoinstruction is
	used without that extension.
	* testsuite/gas/riscv/csr-insns-pseudo.s: Rename section names
	to indicate that the extension 'Zicntr' is needed.
	* testsuite/gas/riscv/csr-insns-pseudo.d: Add "zicntr" to arch.
	* testsuite/gas/riscv/csr-insns-pseudo-noalias.d: Likewise.
	* testsuite/gas/riscv/csr-insns-pseudo-zfinx.d: Likewise.
	* testsuite/gas/riscv/csr-insns-read-only.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Add warnings regarding
	'Zicntr' and 'Zihpm' extension recategorization.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/csr-insns-pseudo-nozicntr.d: New test to
	see warnings are generated when the 'Zicntr' extension is not
	specified.
	* testsuite/gas/riscv/csr-insns-pseudo-nozicntr.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h: Recategorize user counter CSRs.
	* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZICNTR
	for 'Zicntr' pseudoinstructions.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Recategorize counter
	pseudoinstructions to the 'Zicntr' extension.

Author: a4lg

bfd/elfxx-riscv.c

@@ -1148,6 +1148,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zhinx", "zhinxmin",	check_implicit_always},
   {"zhinxmin", "zfinx",	check_implicit_always},
   {"zfinx", "zicsr",	check_implicit_always},
+  {"zicntr", "zicsr",	check_implicit_always},
+  {"zihpm", "zicsr",	check_implicit_always},
   {"zk", "zkn",		check_implicit_always},
   {"zk", "zkr",		check_implicit_always},
   {"zk", "zkt",		check_implicit_always},
@@ -1251,13 +1253,15 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicntr",		ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zicond",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zihintntl",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
+  {"zihpm",		ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfa",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },
@@ -1677,9 +1681,12 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
 	rps->error_handler
 	  (_("x ISA extension `%s' must be set with the versions"),
 	   subset);
-      /* Allow old ISA spec can recognize zicsr and zifencei.  */
+      /* Allow old ISA spec (version 2.2) can recognize extensions
+	 effectively split from the base 'I' extension version 2.0.  */
       else if (strcmp (subset, "zicsr") != 0
-	       && strcmp (subset, "zifencei") != 0)
+	       && strcmp (subset, "zifencei") != 0
+	       && strcmp (subset, "zicntr") != 0
+	       && strcmp (subset, "zihpm") != 0)
 	rps->error_handler
 	  (_("cannot find default versions of the ISA extension `%s'"),
 	   subset);
@@ -2389,6 +2396,9 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zicbop");
     case INSN_CLASS_ZICBOZ:
       return riscv_subset_supports (rps, "zicboz");
+    case INSN_CLASS_ZICNTR:
+      /* Instead of 'Zicntr', query for 'I' for compatibility.  */
+      return riscv_subset_supports (rps, "i");
     case INSN_CLASS_ZICOND:
       return riscv_subset_supports (rps, "zicond");
     case INSN_CLASS_ZICSR:
@@ -2592,6 +2602,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicbop";
     case INSN_CLASS_ZICBOZ:
       return "zicboz";
+    case INSN_CLASS_ZICNTR:
+      return "zicntr";
     case INSN_CLASS_ZICOND:
       return "zicond";
     case INSN_CLASS_ZICSR:

gas/config/tc-riscv.c

@@ -66,6 +66,10 @@ enum riscv_csr_class
 
   CSR_CLASS_I,
   CSR_CLASS_I_32,	/* rv32 only */
+  CSR_CLASS_ZICNTR,	/* basic hardware perf counter */
+  CSR_CLASS_ZICNTR_32,	/* basic hardware perf counter, rv32 only */
+  CSR_CLASS_ZIHPM,	/* additional hardware perf counter */
+  CSR_CLASS_ZIHPM_32,	/* additional hardware perf counter, rv32 only */
   CSR_CLASS_F,		/* f-ext only */
   CSR_CLASS_ZKR,	/* zkr only */
   CSR_CLASS_V,		/* rvv only */
@@ -1033,6 +1037,18 @@ riscv_csr_address (const char *csr_name,
       need_check_version = true;
       extension = "i";
       break;
+    case CSR_CLASS_ZICNTR_32:
+      is_rv32_only = true;
+      /* Fall through.  */
+    case CSR_CLASS_ZICNTR:
+      extension = "zicntr";
+      break;
+    case CSR_CLASS_ZIHPM_32:
+      is_rv32_only = true;
+      /* Fall through.  */
+    case CSR_CLASS_ZIHPM:
+      extension = "zihpm";
+      break;
     case CSR_CLASS_H_32:
       is_rv32_only = true;
       /* Fall through.  */
@@ -2611,6 +2627,15 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      insn_with_csr = false;
 		    }
 
+		  /* Check if we are using a 'Zicntr' pseudoinstruction
+		     without the 'Zicntr' extension.  */
+		  if (insn->insn_class == INSN_CLASS_ZICNTR
+		      && !riscv_subset_supports (&riscv_rps_as, "zicntr"))
+		    {
+		      as_warn (_("`%s' needs `zicntr' extension"),
+			       insn->name);
+		    }
+
 		  /* The (segmant) load and store with EEW 64 cannot be used
 		     when zve32x is enabled.  */
 		  if (ip->insn_mo->pinfo & INSN_V_EEW64

gas/testsuite/gas/riscv/csr-insns-pseudo-noalias.d

@@ -1,5 +1,5 @@
 #source: csr-insns-pseudo.s
-#as: -march=rv32if
+#as: -march=rv32if_zicntr
 #objdump: -dr -Mno-aliases
 
 .*:[ 	]+file format .*

gas/testsuite/gas/riscv/csr-insns-pseudo-nozicntr.d

@@ -0,0 +1,37 @@
+#source: csr-insns-pseudo.s
+#as: -march=rv32if
+#warning_output: csr-insns-pseudo-nozicntr.l
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <pseudo_csr_insn>:
+[ 	]+[0-9a-f]+:[ 	]+000022f3[ 	]+csrr[ 	]+t0,ustatus
+[ 	]+[0-9a-f]+:[ 	]+00029073[ 	]+csrw[ 	]+ustatus,t0
+[ 	]+[0-9a-f]+:[ 	]+0002a073[ 	]+csrs[ 	]+ustatus,t0
+[ 	]+[0-9a-f]+:[ 	]+0002b073[ 	]+csrc[ 	]+ustatus,t0
+[ 	]+[0-9a-f]+:[ 	]+000fd073[ 	]+csrwi[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000fe073[ 	]+csrsi[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000ff073[ 	]+csrci[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+c00022f3[ 	]+rdcycle[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c01022f3[ 	]+rdtime[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c02022f3[ 	]+rdinstret[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c80022f3[ 	]+rdcycleh[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c81022f3[ 	]+rdtimeh[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c82022f3[ 	]+rdinstreth[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+003022f3[ 	]+frcsr[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+003392f3[ 	]+fscsr[ 	]+t0,t2
+[ 	]+[0-9a-f]+:[ 	]+00339073[ 	]+fscsr[ 	]+t2
+[ 	]+[0-9a-f]+:[ 	]+002022f3[ 	]+frrm[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+002312f3[ 	]+fsrm[ 	]+t0,t1
+[ 	]+[0-9a-f]+:[ 	]+00231073[ 	]+fsrm[ 	]+t1
+[ 	]+[0-9a-f]+:[ 	]+002fd2f3[ 	]+fsrmi[ 	]+t0,31
+[ 	]+[0-9a-f]+:[ 	]+002fd073[ 	]+fsrmi[ 	]+zero,31
+[ 	]+[0-9a-f]+:[ 	]+001022f3[ 	]+frflags[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+001312f3[ 	]+fsflags[ 	]+t0,t1
+[ 	]+[0-9a-f]+:[ 	]+00131073[ 	]+fsflags[ 	]+t1
+[ 	]+[0-9a-f]+:[ 	]+001fd2f3[ 	]+fsflagsi[ 	]+t0,31
+[ 	]+[0-9a-f]+:[ 	]+001fd073[ 	]+fsflagsi[ 	]+zero,31

gas/testsuite/gas/riscv/csr-insns-pseudo-nozicntr.l

@@ -0,0 +1,7 @@
+.*Assembler messages:
+.*Warning: `rdcycle' needs `zicntr' extension
+.*Warning: `rdtime' needs `zicntr' extension
+.*Warning: `rdinstret' needs `zicntr' extension
+.*Warning: `rdcycleh' needs `zicntr' extension
+.*Warning: `rdtimeh' needs `zicntr' extension
+.*Warning: `rdinstreth' needs `zicntr' extension

gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d

@@ -1,5 +1,5 @@
 #source: csr-insns-pseudo.s
-#as: -march=rv32i_zfinx
+#as: -march=rv32i_zicntr_zfinx
 #objdump: -dr
 
 .*:[ 	]+file format .*

gas/testsuite/gas/riscv/csr-insns-pseudo.d

@@ -1,5 +1,5 @@
 #source: csr-insns-pseudo.s
-#as: -march=rv32if
+#as: -march=rv32if_zicntr
 #objdump: -dr
 
 .*:[ 	]+file format .*

gas/testsuite/gas/riscv/csr-insns-pseudo.s

@@ -8,11 +8,12 @@ pseudo_csr_insn:
 	csrsi 0x0, 31
 	csrci 0x0, 31
 
+	# Zicntr
 	rdcycle t0
 	rdtime t0
 	rdinstret t0
 
-	# rv32i-ext
+	# Zicntr (RV32)
 	rdcycleh t0
 	rdtimeh t0
 	rdinstreth t0

gas/testsuite/gas/riscv/csr-insns-read-only.d

@@ -1,3 +1,3 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
+#as: -march=rv32if_zicntr -mcsr-check -mpriv-spec=1.11
 #source: csr-insns-read-only.s
 #warning_output: csr-insns-read-only.l