Skip to content

Commit 292f9f8

Browse files
a4lga4lg
committed
RISC-V: Add INSN_DREF to memory read/write instructions
This commit adds INSN_DREF flag (and optional size-related flag) to the instructions that read/write the memory directly. It however excludes cache-related instructions that do synchronization of some sort but otherwise don't touch the contents of the memory. INSN_DREF and optional size flag are added to following instructions: - "cbo.zero" (from the 'Zicboz' extension) - All instructions from following custom extensions: - 'XTheadFMemIdx' - 'XTheadInt' - 'XTheadMemIdx' - 'XTheadMemPair' opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add INSN_DREF and optional size flag on the instructions directly read/write memory.
1 parent 6f85247 commit 292f9f8

File tree

1 file changed

+62
-62
lines changed

1 file changed

+62
-62
lines changed

‎opcodes/riscv-opc.c‎

Lines changed: 62 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -976,7 +976,7 @@ const struct riscv_opcode riscv_opcodes[] =
976976
{"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
977977
{"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
978978
{"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
979-
{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
979+
{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, INSN_DREF },
980980

981981
/* Zicond instructions. */
982982
{"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
@@ -2086,77 +2086,77 @@ const struct riscv_opcode riscv_opcodes[] =
20862086
{"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0},
20872087

20882088
/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */
2089-
{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0},
2090-
{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0},
2091-
{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0},
2092-
{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0},
2093-
{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0},
2094-
{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0},
2095-
{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0},
2096-
{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
2089+
{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, INSN_DREF|INSN_8_BYTE },
2090+
{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, INSN_DREF|INSN_4_BYTE },
2091+
{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, INSN_DREF|INSN_8_BYTE },
2092+
{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, INSN_DREF|INSN_4_BYTE },
2093+
{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, INSN_DREF|INSN_8_BYTE },
2094+
{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, INSN_DREF|INSN_4_BYTE },
2095+
{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, INSN_DREF|INSN_8_BYTE },
2096+
{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, INSN_DREF|INSN_4_BYTE },
20972097

20982098
/* Vendor-specific (T-Head) XTheadFmv instructions. */
20992099
{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
21002100
{"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0},
21012101

21022102
/* Vendor-specific (T-Head) XTheadInt instructions. */
2103-
{"th.ipop", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP, MASK_TH_IPOP, match_opcode, 0},
2104-
{"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, MASK_TH_IPUSH, match_opcode, 0},
2103+
{"th.ipop", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP, MASK_TH_IPOP, match_opcode, INSN_DREF },
2104+
{"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, MASK_TH_IPUSH, match_opcode, INSN_DREF },
21052105

21062106
/* Vendor-specific (T-Head) XTheadMemIdx instructions. */
2107-
{"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0},
2108-
{"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0},
2109-
{"th.lwia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIA, MASK_TH_LWIA, match_th_load_inc, 0},
2110-
{"th.lwib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIB, MASK_TH_LWIB, match_th_load_inc, 0},
2111-
{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, 0},
2112-
{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, 0},
2113-
{"th.lhia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIA, MASK_TH_LHIA, match_th_load_inc, 0},
2114-
{"th.lhib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIB, MASK_TH_LHIB, match_th_load_inc, 0},
2115-
{"th.lhuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, 0},
2116-
{"th.lhuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, 0},
2117-
{"th.lbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIA, MASK_TH_LBIA, match_th_load_inc, 0},
2118-
{"th.lbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIB, MASK_TH_LBIB, match_th_load_inc, 0},
2119-
{"th.lbuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, 0},
2120-
{"th.lbuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, 0},
2121-
{"th.sdia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, 0},
2122-
{"th.sdib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, 0},
2123-
{"th.swia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, 0},
2124-
{"th.swib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, 0},
2125-
{"th.shia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, 0},
2126-
{"th.shib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, 0},
2127-
{"th.sbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, 0},
2128-
{"th.sbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, 0},
2129-
2130-
{"th.lrd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRD, MASK_TH_LRD, match_opcode, 0},
2131-
{"th.lrw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRW, MASK_TH_LRW, match_opcode, 0},
2132-
{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, 0},
2133-
{"th.lrh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRH, MASK_TH_LRH, match_opcode, 0},
2134-
{"th.lrhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, 0},
2135-
{"th.lrb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRB, MASK_TH_LRB, match_opcode, 0},
2136-
{"th.lrbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, 0},
2137-
{"th.srd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRD, MASK_TH_SRD, match_opcode, 0},
2138-
{"th.srw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRW, MASK_TH_SRW, match_opcode, 0},
2139-
{"th.srh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRH, MASK_TH_SRH, match_opcode, 0},
2140-
{"th.srb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRB, MASK_TH_SRB, match_opcode, 0},
2141-
2142-
{"th.lurd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURD, MASK_TH_LURD, match_opcode, 0},
2143-
{"th.lurw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURW, MASK_TH_LURW, match_opcode, 0},
2144-
{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, 0},
2145-
{"th.lurh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURH, MASK_TH_LURH, match_opcode, 0},
2146-
{"th.lurhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, 0},
2147-
{"th.lurb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURB, MASK_TH_LURB, match_opcode, 0},
2148-
{"th.lurbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, 0},
2149-
{"th.surd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURD, MASK_TH_SURD, match_opcode, 0},
2150-
{"th.surw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURW, MASK_TH_SURW, match_opcode, 0},
2151-
{"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURH, MASK_TH_SURH, match_opcode, 0},
2152-
{"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURB, MASK_TH_SURB, match_opcode, 0},
2107+
{"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, INSN_DREF|INSN_8_BYTE },
2108+
{"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, INSN_DREF|INSN_8_BYTE },
2109+
{"th.lwia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIA, MASK_TH_LWIA, match_th_load_inc, INSN_DREF|INSN_4_BYTE },
2110+
{"th.lwib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIB, MASK_TH_LWIB, match_th_load_inc, INSN_DREF|INSN_4_BYTE },
2111+
{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, INSN_DREF|INSN_4_BYTE },
2112+
{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, INSN_DREF|INSN_4_BYTE },
2113+
{"th.lhia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIA, MASK_TH_LHIA, match_th_load_inc, INSN_DREF|INSN_2_BYTE },
2114+
{"th.lhib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIB, MASK_TH_LHIB, match_th_load_inc, INSN_DREF|INSN_2_BYTE },
2115+
{"th.lhuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, INSN_DREF|INSN_2_BYTE },
2116+
{"th.lhuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, INSN_DREF|INSN_2_BYTE },
2117+
{"th.lbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIA, MASK_TH_LBIA, match_th_load_inc, INSN_DREF|INSN_1_BYTE },
2118+
{"th.lbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIB, MASK_TH_LBIB, match_th_load_inc, INSN_DREF|INSN_1_BYTE },
2119+
{"th.lbuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, INSN_DREF|INSN_1_BYTE },
2120+
{"th.lbuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, INSN_DREF|INSN_1_BYTE },
2121+
{"th.sdia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, INSN_DREF|INSN_8_BYTE },
2122+
{"th.sdib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, INSN_DREF|INSN_8_BYTE },
2123+
{"th.swia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, INSN_DREF|INSN_4_BYTE },
2124+
{"th.swib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, INSN_DREF|INSN_4_BYTE },
2125+
{"th.shia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, INSN_DREF|INSN_2_BYTE },
2126+
{"th.shib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, INSN_DREF|INSN_2_BYTE },
2127+
{"th.sbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, INSN_DREF|INSN_1_BYTE },
2128+
{"th.sbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, INSN_DREF|INSN_1_BYTE },
2129+
2130+
{"th.lrd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRD, MASK_TH_LRD, match_opcode, INSN_DREF|INSN_8_BYTE },
2131+
{"th.lrw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRW, MASK_TH_LRW, match_opcode, INSN_DREF|INSN_4_BYTE },
2132+
{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, INSN_DREF|INSN_4_BYTE },
2133+
{"th.lrh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRH, MASK_TH_LRH, match_opcode, INSN_DREF|INSN_2_BYTE },
2134+
{"th.lrhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, INSN_DREF|INSN_2_BYTE },
2135+
{"th.lrb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRB, MASK_TH_LRB, match_opcode, INSN_DREF|INSN_1_BYTE },
2136+
{"th.lrbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, INSN_DREF|INSN_1_BYTE },
2137+
{"th.srd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRD, MASK_TH_SRD, match_opcode, INSN_DREF|INSN_8_BYTE },
2138+
{"th.srw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRW, MASK_TH_SRW, match_opcode, INSN_DREF|INSN_4_BYTE },
2139+
{"th.srh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRH, MASK_TH_SRH, match_opcode, INSN_DREF|INSN_2_BYTE },
2140+
{"th.srb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRB, MASK_TH_SRB, match_opcode, INSN_DREF|INSN_1_BYTE },
2141+
2142+
{"th.lurd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURD, MASK_TH_LURD, match_opcode, INSN_DREF|INSN_8_BYTE },
2143+
{"th.lurw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURW, MASK_TH_LURW, match_opcode, INSN_DREF|INSN_4_BYTE },
2144+
{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, INSN_DREF|INSN_4_BYTE },
2145+
{"th.lurh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURH, MASK_TH_LURH, match_opcode, INSN_DREF|INSN_2_BYTE },
2146+
{"th.lurhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, INSN_DREF|INSN_2_BYTE },
2147+
{"th.lurb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURB, MASK_TH_LURB, match_opcode, INSN_DREF|INSN_1_BYTE },
2148+
{"th.lurbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, INSN_DREF|INSN_1_BYTE },
2149+
{"th.surd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURD, MASK_TH_SURD, match_opcode, INSN_DREF|INSN_8_BYTE },
2150+
{"th.surw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURW, MASK_TH_SURW, match_opcode, INSN_DREF|INSN_4_BYTE },
2151+
{"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURH, MASK_TH_SURH, match_opcode, INSN_DREF|INSN_2_BYTE },
2152+
{"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURB, MASK_TH_SURB, match_opcode, INSN_DREF|INSN_1_BYTE },
21532153

21542154
/* Vendor-specific (T-Head) XTheadMemPair instructions. */
2155-
{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_LDD, MASK_TH_LDD, match_th_load_pair, 0},
2156-
{"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWD, MASK_TH_LWD, match_th_load_pair, 0},
2157-
{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, 0},
2158-
{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_SDD, MASK_TH_SDD, match_opcode, 0},
2159-
{"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_SWD, MASK_TH_SWD, match_opcode, 0},
2155+
{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_LDD, MASK_TH_LDD, match_th_load_pair, INSN_DREF|INSN_16_BYTE },
2156+
{"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWD, MASK_TH_LWD, match_th_load_pair, INSN_DREF|INSN_8_BYTE },
2157+
{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, INSN_DREF|INSN_8_BYTE },
2158+
{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_SDD, MASK_TH_SDD, match_opcode, INSN_DREF|INSN_16_BYTE },
2159+
{"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_SWD, MASK_TH_SWD, match_opcode, INSN_DREF|INSN_8_BYTE },
21602160

21612161
/* Vendor-specific (T-Head) XTheadMac instructions. */
21622162
{"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0},

0 commit comments

Comments
 (0)