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RISC-V: Add support for the 'Zihintntl' extension
This commit adds 'Zihintntl' extension and its hint instructions. This is based on: <riscv/riscv-isa-manual@0dc91f5>, the first ISA Manual noting that the 'Zihintntl' extension is ratified. Note that compressed 'Zihintntl' hints require either 'C' or 'Zca' extension. Co-authored-by: Nelson Chu <[email protected]> bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zihintntl' standard hint 'Z' extension. (riscv_multi_subset_supports): Support new instruction classes. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zihintntl.s: New test for 'Zihintntl' including auto-compression without C prefix and explicit C prefix. * testsuite/gas/riscv/zihintntl.d: Likewise. * testsuite/gas/riscv/zihintntl-na.d: Likewise. * testsuite/gas/riscv/zihintntl-base.s: New test for correspondence between 'Zihintntl' and base 'I' or 'C' instructions. * testsuite/gas/riscv/zihintntl-base.d: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes: INSN_CLASS_ZIHINTNTL and INSN_CLASS_ZIHINTNTL_AND_C. (MASK_NTL_P1, MATCH_NTL_P1, MASK_NTL_PALL, MATCH_NTL_PALL, MASK_NTL_S1, MATCH_NTL_S1, MASK_NTL_ALL, MATCH_NTL_ALL, MASK_C_NTL_P1, MATCH_C_NTL_P1, MASK_C_NTL_PALL, MATCH_C_NTL_PALL, MASK_C_NTL_S1, MATCH_C_NTL_S1, MASK_C_NTL_ALL, MATCH_C_NTL_ALL): New. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add instructions from the 'Zihintntl' extension.
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‎bfd/elfxx-riscv.c‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1254,6 +1254,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
12541254
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
12551255
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
12561256
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
1257+
{"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
12571258
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
12581259
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
12591260
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2391,6 +2392,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
23912392
return riscv_subset_supports (rps, "zicsr");
23922393
case INSN_CLASS_ZIFENCEI:
23932394
return riscv_subset_supports (rps, "zifencei");
2395+
case INSN_CLASS_ZIHINTNTL:
2396+
return riscv_subset_supports (rps, "zihintntl");
2397+
case INSN_CLASS_ZIHINTNTL_AND_C:
2398+
return (riscv_subset_supports (rps, "zihintntl")
2399+
&& (riscv_subset_supports (rps, "c")
2400+
|| riscv_subset_supports (rps, "zca")));
23942401
case INSN_CLASS_ZIHINTPAUSE:
23952402
return riscv_subset_supports (rps, "zihintpause");
23962403
case INSN_CLASS_M:
@@ -2584,6 +2591,19 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
25842591
return "zicsr";
25852592
case INSN_CLASS_ZIFENCEI:
25862593
return "zifencei";
2594+
case INSN_CLASS_ZIHINTNTL:
2595+
return "zihintntl";
2596+
case INSN_CLASS_ZIHINTNTL_AND_C:
2597+
if (!riscv_subset_supports (rps, "zihintntl"))
2598+
{
2599+
if (!riscv_subset_supports (rps, "c")
2600+
&& !riscv_subset_supports (rps, "zca"))
2601+
return _("zihintntl' and `c', or `zihintntl' and `zca");
2602+
else
2603+
return "zihintntl";
2604+
}
2605+
else
2606+
return _("c' or `zca");
25872607
case INSN_CLASS_ZIHINTPAUSE:
25882608
return "zihintpause";
25892609
case INSN_CLASS_M:

‎gas/testsuite/gas/riscv/zihintntl-base.d‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
#as: -march=rv32i_zihintntl
2+
#objdump: -d
3+
4+
.*:[ ]+file format .*
5+
6+
Disassembly of section .text:
7+
8+
0+000 <target>:
9+
[ ]+[0-9a-f]+:[ ]+00200033[ ]+ntl\.p1
10+
[ ]+[0-9a-f]+:[ ]+01b28023[ ]+sb[ ]+s11,0\(t0\)
11+
[ ]+[0-9a-f]+:[ ]+00300033[ ]+ntl\.pall
12+
[ ]+[0-9a-f]+:[ ]+01b28123[ ]+sb[ ]+s11,2\(t0\)
13+
[ ]+[0-9a-f]+:[ ]+00400033[ ]+ntl\.s1
14+
[ ]+[0-9a-f]+:[ ]+01b28223[ ]+sb[ ]+s11,4\(t0\)
15+
[ ]+[0-9a-f]+:[ ]+00500033[ ]+ntl\.all
16+
[ ]+[0-9a-f]+:[ ]+01b28323[ ]+sb[ ]+s11,6\(t0\)
17+
[ ]+[0-9a-f]+:[ ]+900a[ ]+ntl\.p1
18+
[ ]+[0-9a-f]+:[ ]+01b28423[ ]+sb[ ]+s11,8\(t0\)
19+
[ ]+[0-9a-f]+:[ ]+900e[ ]+ntl\.pall
20+
[ ]+[0-9a-f]+:[ ]+01b28523[ ]+sb[ ]+s11,10\(t0\)
21+
[ ]+[0-9a-f]+:[ ]+9012[ ]+ntl\.s1
22+
[ ]+[0-9a-f]+:[ ]+01b28623[ ]+sb[ ]+s11,12\(t0\)
23+
[ ]+[0-9a-f]+:[ ]+9016[ ]+ntl\.all
24+
[ ]+[0-9a-f]+:[ ]+01b28723[ ]+sb[ ]+s11,14\(t0\)

‎gas/testsuite/gas/riscv/zihintntl-base.s‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
target:
2+
# ntl.p1 == add x0, x0, x2
3+
# ntl.pall == add x0, x0, x3
4+
# ntl.s1 == add x0, x0, x4
5+
# ntl.all == add x0, x0, x5
6+
add x0, x0, x2
7+
sb s11, 0(t0)
8+
add x0, x0, x3
9+
sb s11, 2(t0)
10+
add x0, x0, x4
11+
sb s11, 4(t0)
12+
add x0, x0, x5
13+
sb s11, 6(t0)
14+
15+
# c.ntl.p1 == c.add x0, x2
16+
# c.ntl.pall == c.add x0, x3
17+
# c.ntl.s1 == c.add x0, x4
18+
# c.ntl.all == c.add x0, x5
19+
.option push
20+
.option arch, +zca
21+
c.add x0, x2
22+
sb s11, 8(t0)
23+
c.add x0, x3
24+
sb s11, 10(t0)
25+
c.add x0, x4
26+
sb s11, 12(t0)
27+
c.add x0, x5
28+
sb s11, 14(t0)
29+
.option pop

‎gas/testsuite/gas/riscv/zihintntl-na.d‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
#as: -march=rv32i_zihintntl
2+
#source: zihintntl.s
3+
#objdump: -d -M no-aliases
4+
5+
.*:[ ]+file format .*
6+
7+
Disassembly of section .text:
8+
9+
0+000 <target>:
10+
[ ]+[0-9a-f]+:[ ]+00200033[ ]+ntl\.p1
11+
[ ]+[0-9a-f]+:[ ]+01b28023[ ]+sb[ ]+s11,0\(t0\)
12+
[ ]+[0-9a-f]+:[ ]+00300033[ ]+ntl\.pall
13+
[ ]+[0-9a-f]+:[ ]+01b28123[ ]+sb[ ]+s11,2\(t0\)
14+
[ ]+[0-9a-f]+:[ ]+00400033[ ]+ntl\.s1
15+
[ ]+[0-9a-f]+:[ ]+01b28223[ ]+sb[ ]+s11,4\(t0\)
16+
[ ]+[0-9a-f]+:[ ]+00500033[ ]+ntl\.all
17+
[ ]+[0-9a-f]+:[ ]+01b28323[ ]+sb[ ]+s11,6\(t0\)
18+
[ ]+[0-9a-f]+:[ ]+900a[ ]+c\.ntl\.p1
19+
[ ]+[0-9a-f]+:[ ]+01b28023[ ]+sb[ ]+s11,0\(t0\)
20+
[ ]+[0-9a-f]+:[ ]+900e[ ]+c\.ntl\.pall
21+
[ ]+[0-9a-f]+:[ ]+01b28123[ ]+sb[ ]+s11,2\(t0\)
22+
[ ]+[0-9a-f]+:[ ]+9012[ ]+c\.ntl\.s1
23+
[ ]+[0-9a-f]+:[ ]+01b28223[ ]+sb[ ]+s11,4\(t0\)
24+
[ ]+[0-9a-f]+:[ ]+9016[ ]+c\.ntl\.all
25+
[ ]+[0-9a-f]+:[ ]+01b28323[ ]+sb[ ]+s11,6\(t0\)
26+
[ ]+[0-9a-f]+:[ ]+900a[ ]+c\.ntl\.p1
27+
[ ]+[0-9a-f]+:[ ]+01b28423[ ]+sb[ ]+s11,8\(t0\)
28+
[ ]+[0-9a-f]+:[ ]+900e[ ]+c\.ntl\.pall
29+
[ ]+[0-9a-f]+:[ ]+01b28523[ ]+sb[ ]+s11,10\(t0\)
30+
[ ]+[0-9a-f]+:[ ]+9012[ ]+c\.ntl\.s1
31+
[ ]+[0-9a-f]+:[ ]+01b28623[ ]+sb[ ]+s11,12\(t0\)
32+
[ ]+[0-9a-f]+:[ ]+9016[ ]+c\.ntl\.all
33+
[ ]+[0-9a-f]+:[ ]+01b28723[ ]+sb[ ]+s11,14\(t0\)

‎gas/testsuite/gas/riscv/zihintntl.d‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
#as: -march=rv32i_zihintntl
2+
#objdump: -d
3+
4+
.*:[ ]+file format .*
5+
6+
Disassembly of section .text:
7+
8+
0+000 <target>:
9+
[ ]+[0-9a-f]+:[ ]+00200033[ ]+ntl\.p1
10+
[ ]+[0-9a-f]+:[ ]+01b28023[ ]+sb[ ]+s11,0\(t0\)
11+
[ ]+[0-9a-f]+:[ ]+00300033[ ]+ntl\.pall
12+
[ ]+[0-9a-f]+:[ ]+01b28123[ ]+sb[ ]+s11,2\(t0\)
13+
[ ]+[0-9a-f]+:[ ]+00400033[ ]+ntl\.s1
14+
[ ]+[0-9a-f]+:[ ]+01b28223[ ]+sb[ ]+s11,4\(t0\)
15+
[ ]+[0-9a-f]+:[ ]+00500033[ ]+ntl\.all
16+
[ ]+[0-9a-f]+:[ ]+01b28323[ ]+sb[ ]+s11,6\(t0\)
17+
[ ]+[0-9a-f]+:[ ]+900a[ ]+ntl\.p1
18+
[ ]+[0-9a-f]+:[ ]+01b28023[ ]+sb[ ]+s11,0\(t0\)
19+
[ ]+[0-9a-f]+:[ ]+900e[ ]+ntl\.pall
20+
[ ]+[0-9a-f]+:[ ]+01b28123[ ]+sb[ ]+s11,2\(t0\)
21+
[ ]+[0-9a-f]+:[ ]+9012[ ]+ntl\.s1
22+
[ ]+[0-9a-f]+:[ ]+01b28223[ ]+sb[ ]+s11,4\(t0\)
23+
[ ]+[0-9a-f]+:[ ]+9016[ ]+ntl\.all
24+
[ ]+[0-9a-f]+:[ ]+01b28323[ ]+sb[ ]+s11,6\(t0\)
25+
[ ]+[0-9a-f]+:[ ]+900a[ ]+ntl\.p1
26+
[ ]+[0-9a-f]+:[ ]+01b28423[ ]+sb[ ]+s11,8\(t0\)
27+
[ ]+[0-9a-f]+:[ ]+900e[ ]+ntl\.pall
28+
[ ]+[0-9a-f]+:[ ]+01b28523[ ]+sb[ ]+s11,10\(t0\)
29+
[ ]+[0-9a-f]+:[ ]+9012[ ]+ntl\.s1
30+
[ ]+[0-9a-f]+:[ ]+01b28623[ ]+sb[ ]+s11,12\(t0\)
31+
[ ]+[0-9a-f]+:[ ]+9016[ ]+ntl\.all
32+
[ ]+[0-9a-f]+:[ ]+01b28723[ ]+sb[ ]+s11,14\(t0\)

‎gas/testsuite/gas/riscv/zihintntl.s‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
.macro INSN_SEQ
2+
ntl.p1
3+
sb s11, 0(t0)
4+
ntl.pall
5+
sb s11, 2(t0)
6+
ntl.s1
7+
sb s11, 4(t0)
8+
ntl.all
9+
sb s11, 6(t0)
10+
.endm
11+
12+
.macro INSN_SEQ_C
13+
c.ntl.p1
14+
sb s11, 8(t0)
15+
c.ntl.pall
16+
sb s11, 10(t0)
17+
c.ntl.s1
18+
sb s11, 12(t0)
19+
c.ntl.all
20+
sb s11, 14(t0)
21+
.endm
22+
23+
target:
24+
INSN_SEQ # RV32I_Zihintntl
25+
26+
# 'Zcb' is chosen to test complex cases to enable
27+
# compressed instructions.
28+
.option push
29+
.option arch, +zcb
30+
INSN_SEQ # RV32I_Zihintntl_Zca_Zcb (auto compression without prefix)
31+
INSN_SEQ_C # RV32I_Zihintntl_Zca_Zcb (with compressed prefix)
32+
.option pop

‎include/opcode/riscv-opc.h‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2298,6 +2298,23 @@
22982298
#define MASK_CZERO_EQZ 0xfe00707f
22992299
#define MATCH_CZERO_NEZ 0xe007033
23002300
#define MASK_CZERO_NEZ 0xfe00707f
2301+
/* Zihintntl hint instructions. */
2302+
#define MATCH_NTL_P1 0x200033
2303+
#define MASK_NTL_P1 0xffffffff
2304+
#define MATCH_NTL_PALL 0x300033
2305+
#define MASK_NTL_PALL 0xffffffff
2306+
#define MATCH_NTL_S1 0x400033
2307+
#define MASK_NTL_S1 0xffffffff
2308+
#define MATCH_NTL_ALL 0x500033
2309+
#define MASK_NTL_ALL 0xffffffff
2310+
#define MATCH_C_NTL_P1 0x900a
2311+
#define MASK_C_NTL_P1 0xffff
2312+
#define MATCH_C_NTL_PALL 0x900e
2313+
#define MASK_C_NTL_PALL 0xffff
2314+
#define MATCH_C_NTL_S1 0x9012
2315+
#define MASK_C_NTL_S1 0xffff
2316+
#define MATCH_C_NTL_ALL 0x9016
2317+
#define MASK_C_NTL_ALL 0xffff
23012318
/* Zawrs intructions. */
23022319
#define MATCH_WRS_NTO 0x00d00073
23032320
#define MASK_WRS_NTO 0xffffffff
@@ -3341,6 +3358,15 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
33413358
/* Zicond instructions. */
33423359
DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
33433360
DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
3361+
/* Zihintntl hint instructions. */
3362+
DECLARE_INSN(ntl_p1, MATCH_NTL_P1, MASK_NTL_P1);
3363+
DECLARE_INSN(ntl_pall, MATCH_NTL_PALL, MASK_NTL_PALL);
3364+
DECLARE_INSN(ntl_s1, MATCH_NTL_S1, MASK_NTL_S1);
3365+
DECLARE_INSN(ntl_all, MATCH_NTL_ALL, MASK_NTL_ALL);
3366+
DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1);
3367+
DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL);
3368+
DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1);
3369+
DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL);
33443370
/* Zawrs instructions. */
33453371
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
33463372
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)

‎include/opcode/riscv.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -392,6 +392,8 @@ enum riscv_insn_class
392392
INSN_CLASS_ZICOND,
393393
INSN_CLASS_ZICSR,
394394
INSN_CLASS_ZIFENCEI,
395+
INSN_CLASS_ZIHINTNTL,
396+
INSN_CLASS_ZIHINTNTL_AND_C,
395397
INSN_CLASS_ZIHINTPAUSE,
396398
INSN_CLASS_ZMMUL,
397399
INSN_CLASS_ZAWRS,

‎opcodes/riscv-opc.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -337,6 +337,18 @@ const struct riscv_opcode riscv_opcodes[] =
337337
{"prefetch.i", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
338338
{"prefetch.r", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
339339
{"prefetch.w", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
340+
{"ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, INSN_ALIAS },
341+
{"ntl.p1", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_P1, MASK_NTL_P1, match_opcode, 0 },
342+
{"ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, INSN_ALIAS },
343+
{"ntl.pall", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_PALL, MASK_NTL_PALL, match_opcode, 0 },
344+
{"ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, INSN_ALIAS },
345+
{"ntl.s1", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_S1, MASK_NTL_S1, match_opcode, 0 },
346+
{"ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, INSN_ALIAS },
347+
{"ntl.all", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_ALL, MASK_NTL_ALL, match_opcode, 0 },
348+
{"c.ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, 0 },
349+
{"c.ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, 0 },
350+
{"c.ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, 0 },
351+
{"c.ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, 0 },
340352
{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 },
341353

342354
/* Basic RVI instructions and aliases. */

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