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UNRATIFIED RISC-V: Add 'Zfbfmin' extension
[DO NOT MERGE] Until RISC-V BF16 extensions are frozen/ratified and the final version number is determined, this patch should not be merged upstream. This commit uses unratified version 0.8 as in the latest PDF documentation (instead of possible 1.0 after ratification). This commit adds support for the 'Zfbfmin' extension, the scalar BF16 conversion extension. It consists of two new instructions and four previously 'Zfhmin'-only instructions. This commit is based on the following specification: <riscv/riscv-bfloat16@5578e34> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets) Add 'Zfbfmin' -> 'F'. (riscv_supported_std_z_ext): Add 'Zfbfmin'. (riscv_multi_subset_supports): Recategory INSN_CLASS_ZFHMIN to mean 'Zfhmin' or 'Zfbfmin'. Add support to INSN_CLASS_ZFBFMIN. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zfbfmin.s: New test. * testsuite/gas/riscv/zfbfmin.d: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZFBFMIN. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add 'Zfbfmin'-only instructions.
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‎bfd/elfxx-riscv.c‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1140,6 +1140,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
11401140
{"zcf", "f", check_implicit_always},
11411141
{"zfa", "f", check_implicit_always},
11421142
{"d", "f", check_implicit_always},
1143+
{"zfbfmin", "f", check_implicit_always},
11431144
{"zfh", "zfhmin", check_implicit_always},
11441145
{"zfhmin", "f", check_implicit_always},
11451146
{"f", "zicsr", check_implicit_always},
@@ -1259,6 +1260,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
12591260
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
12601261
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
12611262
{"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 },
1263+
{"zfbfmin", ISA_SPEC_CLASS_DRAFT, 0, 8, 0 },
12621264
{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
12631265
{"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
12641266
{"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2434,11 +2436,14 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
24342436
case INSN_CLASS_Q_INX:
24352437
return (riscv_subset_supports (rps, "q")
24362438
|| riscv_subset_supports (rps, "zqinx"));
2439+
case INSN_CLASS_ZFBFMIN:
2440+
return riscv_subset_supports (rps, "zfbfmin");
24372441
case INSN_CLASS_ZFH_INX:
24382442
return (riscv_subset_supports (rps, "zfh")
24392443
|| riscv_subset_supports (rps, "zhinx"));
24402444
case INSN_CLASS_ZFHMIN:
2441-
return riscv_subset_supports (rps, "zfhmin");
2445+
return (riscv_subset_supports (rps, "zfhmin")
2446+
|| riscv_subset_supports (rps, "zfbfmin"));
24422447
case INSN_CLASS_ZFHMIN_INX:
24432448
return (riscv_subset_supports (rps, "zfhmin")
24442449
|| riscv_subset_supports (rps, "zhinxmin"));
@@ -2654,10 +2659,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
26542659
return _("d' or `zdinx");
26552660
case INSN_CLASS_Q_INX:
26562661
return _("q' or `zqinx");
2662+
case INSN_CLASS_ZFBFMIN:
2663+
return "zfbfmin";
26572664
case INSN_CLASS_ZFH_INX:
26582665
return _("zfh' or `zhinx");
26592666
case INSN_CLASS_ZFHMIN:
2660-
return "zfhmin";
2667+
return _("zfhmin' or `zfbfmin");
26612668
case INSN_CLASS_ZFHMIN_INX:
26622669
return _("zfhmin' or `zhinxmin");
26632670
case INSN_CLASS_ZFHMIN_AND_D_INX:

‎gas/testsuite/gas/riscv/zfbfmin.d‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
#as: -march=rv32i_zfbfmin
2+
#objdump: -d
3+
4+
.*:[ ]+file format .*
5+
6+
Disassembly of section .text:
7+
8+
0+000 <target>:
9+
[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt\.bf16\.s[ ]+fa0,fa1
10+
[ ]+[0-9a-f]+:[ ]+44859553[ ]+fcvt\.bf16\.s[ ]+fa0,fa1,rtz
11+
[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt\.s\.bf16[ ]+fa0,fa1
12+
[ ]+[0-9a-f]+:[ ]+00059507[ ]+flh[ ]+fa0,0\(a1\)
13+
[ ]+[0-9a-f]+:[ ]+00a59027[ ]+fsh[ ]+fa0,0\(a1\)
14+
[ ]+[0-9a-f]+:[ ]+e4058553[ ]+fmv\.x\.h[ ]+a0,fa1
15+
[ ]+[0-9a-f]+:[ ]+f4058553[ ]+fmv\.h\.x[ ]+fa0,a1

‎gas/testsuite/gas/riscv/zfbfmin.s‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
target:
2+
# Zfbfmin only instructions
3+
fcvt.bf16.s fa0, fa1
4+
fcvt.bf16.s fa0, fa1, rtz
5+
fcvt.s.bf16 fa0, fa1
6+
# Instructions shared with Zfhmin
7+
flh fa0, 0(a1)
8+
fsh fa0, 0(a1)
9+
fmv.x.h a0, fa1
10+
fmv.h.x fa0, a1

‎include/opcode/riscv-opc.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2121,6 +2121,11 @@
21212121
#define MASK_VDOTUVV 0xfc00707f
21222122
#define MATCH_VFDOTVV 0xe4001057
21232123
#define MASK_VFDOTVV 0xfc00707f
2124+
/* Zfbfmin instructions. */
2125+
#define MATCH_FCVT_BF16_S 0x44800053
2126+
#define MASK_FCVT_BF16_S 0xfff0007f
2127+
#define MATCH_FCVT_S_BF16 0x40600053
2128+
#define MASK_FCVT_S_BF16 0xfff0007f
21242129
/* Zvbb instructions. */
21252130
#define MATCH_VANDN_VV 0x4000057
21262131
#define MASK_VANDN_VV 0xfc00707f
@@ -3370,6 +3375,9 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL);
33703375
/* Zawrs instructions. */
33713376
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
33723377
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
3378+
/* Zfbfmin instructions. */
3379+
DECLARE_INSN(fcvt_bf16_s, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
3380+
DECLARE_INSN(fcvt_s_bf16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
33733381
/* Zvbb instructions. */
33743382
DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
33753383
DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)

‎include/opcode/riscv.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -400,6 +400,7 @@ enum riscv_insn_class
400400
INSN_CLASS_F_INX,
401401
INSN_CLASS_D_INX,
402402
INSN_CLASS_Q_INX,
403+
INSN_CLASS_ZFBFMIN,
403404
INSN_CLASS_ZFH_INX,
404405
INSN_CLASS_ZFHMIN,
405406
INSN_CLASS_ZFHMIN_INX,

‎opcodes/riscv-opc.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -986,6 +986,11 @@ const struct riscv_opcode riscv_opcodes[] =
986986
{"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
987987
{"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
988988

989+
/* Zfbfmin instructions. */
990+
{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
991+
{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 },
992+
{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
993+
989994
/* Zfa instructions. */
990995
{"fli.s", 0, INSN_CLASS_ZFA, "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 },
991996
{"fli.d", 0, INSN_CLASS_D_AND_ZFA, "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 },

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