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maciej-w-rozyckimaciej-w-rozycki
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PR 19977: MIPS: Add missing pairing for REL PCHI/PCLO relocations
Just as with all HI/LO 16-bit partial relocations the newly-introduced MIPSr6 PC-relative R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations require pairing for correct borrow propagation from the low part to the high part with REL targets, another case for PR 19977. Unlike with absolute relocation, there is a complication here in that both parts represent a calculation that is relative to the PC at the individual relocation's location rather than both referring to the location of the R_MIPS_PCHI16 relocation, normally applied to an AUIPC instruction, the location of which is used for the run-time calculation executed by hardware. To take this semantics into account, the addend of the R_MIPS_PCLO16 relocation matching a given R_MIPS_PCHI16 relocation is expected to be adjusted in the source assembly file for the distance between the two relocations in a single pair, so that once both relocations have been calculated by the linker, the expression calculated at run time is such as if the combined 32-bit immediate was added at the location of the AUIPC instruction. So for matching R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations into pairs GAS needs to check for the distance between the two relocations to be equal to the difference between the addends supplied, and then the linker has to subtract the low part of the distance between the two relocations from the low part in calculating the high part, so as to factor in any borrow. A further complication is that `_bfd_mips_elf_lo16_reloc' handler is supplied with the addend differently depending on whether it has been called by GAS via `bfd_install_relocation', or by the generic linker via `bfd_perform_relocation'. In the former case the addend is supplied with the relocation itself while in the latter one it comes from the field being relocated. We currently ignore the addend supplied with the relocation and it works for calculating absolute high-part relocations, because the same addend has been previously supplied with them when `_bfd_mips_elf_hi16_reloc' was called, however this approach does not work for the PC-relative case because as noted above the low-part addend is different and we need to consistently apply the distance adjustment both with GAS and LD. Since the supplied addend and one retrieved from field being relocated won't ever be both nonzero, just use the sum of the two values. The low-part addend in `mips_elf_add_lo16_rel_addend' always comes from the field being relocated, so there's no complication there, we just need to apply the same adjustment. New linker test cases verify that the same ultimate machine code is produced both for ELF and S-record output formats, ensuring that the both the MIPS/ELF linker and the generic linker behave in the correct way, consistent with each other.
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lines changed

‎bfd/elf32-mips.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -789,7 +789,7 @@ static reloc_howto_type elf_mips_howto_table_rel[] =
789789
true, /* pc_relative */
790790
0, /* bitpos */
791791
complain_overflow_signed, /* complain_on_overflow */
792-
_bfd_mips_elf_generic_reloc, /* special_function */
792+
_bfd_mips_elf_hi16_reloc, /* special_function */
793793
"R_MIPS_PCHI16", /* name */
794794
true, /* partial_inplace */
795795
0x0000ffff, /* src_mask */
@@ -803,7 +803,7 @@ static reloc_howto_type elf_mips_howto_table_rel[] =
803803
true, /* pc_relative */
804804
0, /* bitpos */
805805
complain_overflow_dont, /* complain_on_overflow */
806-
_bfd_mips_elf_generic_reloc, /* special_function */
806+
_bfd_mips_elf_lo16_reloc, /* special_function */
807807
"R_MIPS_PCLO16", /* name */
808808
true, /* partial_inplace */
809809
0x0000ffff, /* src_mask */

‎bfd/elf64-mips.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -868,7 +868,7 @@ static reloc_howto_type mips_elf64_howto_table_rel[] =
868868
true, /* pc_relative */
869869
0, /* bitpos */
870870
complain_overflow_signed, /* complain_on_overflow */
871-
_bfd_mips_elf_generic_reloc, /* special_function */
871+
_bfd_mips_elf_hi16_reloc, /* special_function */
872872
"R_MIPS_PCHI16", /* name */
873873
true, /* partial_inplace */
874874
0x0000ffff, /* src_mask */
@@ -882,7 +882,7 @@ static reloc_howto_type mips_elf64_howto_table_rel[] =
882882
true, /* pc_relative */
883883
0, /* bitpos */
884884
complain_overflow_dont, /* complain_on_overflow */
885-
_bfd_mips_elf_generic_reloc, /* special_function */
885+
_bfd_mips_elf_lo16_reloc, /* special_function */
886886
"R_MIPS_PCLO16", /* name */
887887
true, /* partial_inplace */
888888
0x0000ffff, /* src_mask */

‎bfd/elfn32-mips.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -847,7 +847,7 @@ static reloc_howto_type elf_mips_howto_table_rel[] =
847847
true, /* pc_relative */
848848
0, /* bitpos */
849849
complain_overflow_signed, /* complain_on_overflow */
850-
_bfd_mips_elf_generic_reloc, /* special_function */
850+
_bfd_mips_elf_hi16_reloc, /* special_function */
851851
"R_MIPS_PCHI16", /* name */
852852
true, /* partial_inplace */
853853
0x0000ffff, /* src_mask */
@@ -861,7 +861,7 @@ static reloc_howto_type elf_mips_howto_table_rel[] =
861861
true, /* pc_relative */
862862
0, /* bitpos */
863863
complain_overflow_dont, /* complain_on_overflow */
864-
_bfd_mips_elf_generic_reloc, /* special_function */
864+
_bfd_mips_elf_lo16_reloc, /* special_function */
865865
"R_MIPS_PCLO16", /* name */
866866
true, /* partial_inplace */
867867
0x0000ffff, /* src_mask */

‎bfd/elfxx-mips.c‎

Lines changed: 24 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2600,20 +2600,22 @@ _bfd_mips_elf_lo16_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol,
26002600
extended. For example, an addend of 0x38000 would have 0x0004 in
26012601
the high part and 0x8000 (=0xff..f8000) in the low part.
26022602
To extract the actual addend, calculate
2603-
((hi & 0xffff) << 16) + ((lo & 0xffff) ^ 0x8000) - 0x8000.
2604-
We will be applying (symbol + addend) & 0xffff to the low insn,
2605-
and we want to apply (symbol + addend + 0x8000) >> 16 to the
2606-
high insn (the +0x8000 adjusting for when the applied low part is
2607-
negative). */
2603+
((hi & 0xffff) << 16) + ((lo & 0xffff) ^ 0x8000) - 0x8000. */
26082604
vallo = _bfd_mips_elf_sign_extend (bfd_get_32 (abfd, location) & 0xffff, 16);
26092605
_bfd_mips_elf_reloc_shuffle (abfd, reloc_entry->howto->type, false,
26102606
location);
2607+
/* Add in the separate addend, if any. Since we are REL here this
2608+
will have been set and the in-place addend cleared if we have
2609+
been called from GAS via `bfd_install_relocation'. */
2610+
vallo += reloc_entry->addend;
26112611

26122612
tdata = mips_elf_tdata (abfd);
26132613
while (tdata->mips_hi16_list != NULL)
26142614
{
26152615
bfd_reloc_status_type ret;
26162616
struct mips_hi16 *hi;
2617+
bfd_vma addhi;
2618+
bfd_vma addlo;
26172619

26182620
hi = tdata->mips_hi16_list;
26192621

@@ -2629,7 +2631,19 @@ _bfd_mips_elf_lo16_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol,
26292631
else if (hi->rel.howto->type == R_MICROMIPS_GOT16)
26302632
hi->rel.howto = MIPS_ELF_RTYPE_TO_HOWTO (abfd, R_MICROMIPS_HI16, false);
26312633

2632-
hi->rel.addend += vallo;
2634+
/* We will be applying (symbol + addend) & 0xffff to the low insn,
2635+
and we want to apply (symbol + addend + 0x8000) >> 16 to the
2636+
high insn (the +0x8000 adjusting for when the applied low part is
2637+
negative). */
2638+
addhi = (hi->rel.addend + 0x8000) & ~(bfd_vma) 0xffff;
2639+
addlo = vallo;
2640+
2641+
/* For a PC-relative relocation the PCLO16 part of the addend
2642+
is relative to its PC and not ours, so we need to adjust it. */
2643+
if (hi->rel.howto->type == R_MIPS_PCHI16)
2644+
addlo -= reloc_entry->address - hi->rel.address;
2645+
2646+
hi->rel.addend = addhi + _bfd_mips_elf_sign_extend (addlo & 0xffff, 16);
26332647

26342648
ret = _bfd_mips_elf_generic_reloc (abfd, &hi->rel, symbol, hi->data,
26352649
hi->input_section, output_bfd,
@@ -8334,6 +8348,10 @@ mips_elf_add_lo16_rel_addend (bfd *abfd,
83348348
contents);
83358349

83368350
l <<= lo16_howto->rightshift;
8351+
/* For a PC-relative relocation the PCLO16 part of the addend
8352+
is relative to its PC and not ours, so we need to adjust it. */
8353+
if (r_type == R_MIPS_PCHI16)
8354+
l = (l - (lo16_relocation->r_offset - rel->r_offset)) & 0xffff;
83378355
l = _bfd_mips_elf_sign_extend (l, 16);
83388356

83398357
*addend <<= 16;

‎gas/config/tc-mips.c‎

Lines changed: 35 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4328,14 +4328,16 @@ got16_reloc_p (bfd_reloc_code_real_type reloc)
43284328
static inline bool
43294329
hi16_reloc_p (bfd_reloc_code_real_type reloc)
43304330
{
4331-
return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4331+
return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_HI16_S_PCREL
4332+
|| reloc == BFD_RELOC_MIPS16_HI16_S
43324333
|| reloc == BFD_RELOC_MICROMIPS_HI16_S);
43334334
}
43344335

43354336
static inline bool
43364337
lo16_reloc_p (bfd_reloc_code_real_type reloc)
43374338
{
4338-
return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4339+
return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_LO16_PCREL
4340+
|| reloc == BFD_RELOC_MIPS16_LO16
43394341
|| reloc == BFD_RELOC_MICROMIPS_LO16);
43404342
}
43414343

@@ -4402,8 +4404,9 @@ static inline bfd_reloc_code_real_type
44024404
matching_lo_reloc (bfd_reloc_code_real_type reloc)
44034405
{
44044406
return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4405-
: (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4406-
: BFD_RELOC_LO16));
4407+
: micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4408+
: reloc == BFD_RELOC_HI16_S_PCREL ? BFD_RELOC_LO16_PCREL
4409+
: BFD_RELOC_LO16);
44074410
}
44084411

44094412
/* Return true if the given fixup is followed by a matching R_MIPS_LO16
@@ -4415,7 +4418,12 @@ fixup_has_matching_lo_p (fixS *fixp)
44154418
return (fixp->fx_next != NULL
44164419
&& fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
44174420
&& fixp->fx_addsy == fixp->fx_next->fx_addsy
4418-
&& fixp->fx_offset == fixp->fx_next->fx_offset);
4421+
&& (fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
4422+
? (fixp->fx_next->fx_offset - fixp->fx_offset
4423+
== ((fixp->fx_next->fx_frag->fr_address
4424+
+ fixp->fx_next->fx_where)
4425+
- (fixp->fx_frag->fr_address + fixp->fx_where)))
4426+
: fixp->fx_offset == fixp->fx_next->fx_offset));
44194427
}
44204428

44214429
/* Move all labels in LABELS to the current insertion point. TEXT_P
@@ -15413,6 +15421,13 @@ mips_frob_file_before_adjust (void)
1541315421
if the user knows that adding 2 to "foo" will not induce a carry to
1541415422
the high 16 bits.
1541515423

15424+
A %pcrel_lo() expression matches a %pcrel_hi() expression if:
15425+
15426+
(a) it refers to the same symbol; and
15427+
(b) the offset applied in the %pcrel_lo() expression equals
15428+
the offset applied in the %pcrel_hi() expression plus the
15429+
distance from the location of %pcrel_hi() to %pcrel_lo().
15430+
1541615431
When several %lo()s match a particular %got() or %hi(), we use the
1541715432
following rules to distinguish them:
1541815433

@@ -15484,9 +15499,14 @@ mips_frob_file (void)
1548415499

1548515500
if ((*pos)->fx_r_type == looking_for_rtype
1548615501
&& symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15487-
&& (*pos)->fx_offset >= l->fixp->fx_offset
15502+
&& (l->fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
15503+
? ((*pos)->fx_offset - l->fixp->fx_offset
15504+
== (((*pos)->fx_frag->fr_address + (*pos)->fx_where)
15505+
- (l->fixp->fx_frag->fr_address + l->fixp->fx_where)))
15506+
: (*pos)->fx_offset >= l->fixp->fx_offset)
1548815507
&& (lo_pos == NULL
15489-
|| (*pos)->fx_offset < (*lo_pos)->fx_offset
15508+
|| (l->fixp->fx_r_type != BFD_RELOC_HI16_S_PCREL
15509+
&& (*pos)->fx_offset < (*lo_pos)->fx_offset)
1549015510
|| (!matched_lo_p
1549115511
&& (*pos)->fx_offset == (*lo_pos)->fx_offset)))
1549215512
lo_pos = pos;
@@ -15497,15 +15517,20 @@ mips_frob_file (void)
1549715517

1549815518
/* If we found a match, remove the high-part relocation from its
1549915519
current position and insert it before the low-part relocation.
15500-
Make the offsets match so that fixup_has_matching_lo_p()
15501-
will return true.
15520+
15521+
For absolute relocations make the offsets match so that
15522+
fixup_has_matching_lo_p() will return true. For PC-relative
15523+
relocations the distance between the offsets is retained
15524+
according to expectations in `fixup_has_matching_lo_p',
15525+
`_bfd_mips_elf_lo16_reloc' and `mips_elf_add_lo16_rel_addend'.
1550215526

1550315527
We don't warn about unmatched high-part relocations since some
1550415528
versions of gcc have been known to emit dead "lui ...%hi(...)"
1550515529
instructions. */
1550615530
if (lo_pos != NULL)
1550715531
{
15508-
l->fixp->fx_offset = (*lo_pos)->fx_offset;
15532+
if (l->fixp->fx_r_type != BFD_RELOC_HI16_S_PCREL)
15533+
l->fixp->fx_offset = (*lo_pos)->fx_offset;
1550915534
if (l->fixp->fx_next != *lo_pos)
1551015535
{
1551115536
*hi_pos = l->fixp->fx_next;

‎gas/testsuite/gas/mips/mips.exp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1724,6 +1724,13 @@ if { [istarget mips*-*-vxworks*] } {
17241724
run_dump_test "pcrel-4-n32"
17251725
run_dump_test "pcrel-4-64"
17261726
}
1727+
run_dump_test "pcrel-hilo-match"
1728+
run_dump_test "pcrel-hilo-addend"
1729+
run_dump_test "pcrel-hilo"
1730+
if $has_newabi {
1731+
run_dump_test "pcrel-hilo-n32"
1732+
run_dump_test "pcrel-hilo-64"
1733+
}
17271734

17281735
run_dump_test "pcrel-reloc-1"
17291736
run_dump_test "pcrel-reloc-1-r6"

‎gas/testsuite/gas/mips/pcrel-hilo-64.d‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
#readelf: -r
2+
#name: MIPSr6 PCHI16/PCLO16 relocations (n64)
3+
#as: -mabi=64 -march=mips64r6 -mno-pdr
4+
#source: pcrel-hilo.s
5+
6+
Relocation section '\.rela\.text' at offset .+ contains 24 entries:
7+
Offset Info Type Sym\. Value Sym\. Name \+ Addend
8+
000000000000 000800000040 R_MIPS_PCHI16 0000000000000000 bar \+ 7fec
9+
Type2: R_MIPS_NONE
10+
Type3: R_MIPS_NONE
11+
000000000004 000900000005 R_MIPS_HI16 0000000000000000 baz \+ 0
12+
Type2: R_MIPS_NONE
13+
Type3: R_MIPS_NONE
14+
000000000008 000800000040 R_MIPS_PCHI16 0000000000000000 bar \+ 7ff8
15+
Type2: R_MIPS_NONE
16+
Type3: R_MIPS_NONE
17+
00000000000c 000800000040 R_MIPS_PCHI16 0000000000000000 bar \+ fff0
18+
Type2: R_MIPS_NONE
19+
Type3: R_MIPS_NONE
20+
000000000010 000800000041 R_MIPS_PCLO16 0000000000000000 bar \+ 7ffc
21+
Type2: R_MIPS_NONE
22+
Type3: R_MIPS_NONE
23+
000000000014 000900000006 R_MIPS_LO16 0000000000000000 baz \+ 0
24+
Type2: R_MIPS_NONE
25+
Type3: R_MIPS_NONE
26+
000000000018 000800000041 R_MIPS_PCLO16 0000000000000000 bar \+ 8008
27+
Type2: R_MIPS_NONE
28+
Type3: R_MIPS_NONE
29+
00000000001c 000800000041 R_MIPS_PCLO16 0000000000000000 bar \+ 10000
30+
Type2: R_MIPS_NONE
31+
Type3: R_MIPS_NONE
32+
000000000020 000800000040 R_MIPS_PCHI16 0000000000000000 bar \+ 800c
33+
Type2: R_MIPS_NONE
34+
Type3: R_MIPS_NONE
35+
000000000024 000900000005 R_MIPS_HI16 0000000000000000 baz \+ 0
36+
Type2: R_MIPS_NONE
37+
Type3: R_MIPS_NONE
38+
000000000028 000800000040 R_MIPS_PCHI16 0000000000000000 bar \+ 8018
39+
Type2: R_MIPS_NONE
40+
Type3: R_MIPS_NONE
41+
00000000002c 000800000040 R_MIPS_PCHI16 0000000000000000 bar \+ 10010
42+
Type2: R_MIPS_NONE
43+
Type3: R_MIPS_NONE
44+
000000030030 000800000041 R_MIPS_PCLO16 0000000000000000 bar \+ 3801c
45+
Type2: R_MIPS_NONE
46+
Type3: R_MIPS_NONE
47+
000000030034 000900000006 R_MIPS_LO16 0000000000000000 baz \+ 0
48+
Type2: R_MIPS_NONE
49+
Type3: R_MIPS_NONE
50+
000000030038 000800000041 R_MIPS_PCLO16 0000000000000000 bar \+ 38028
51+
Type2: R_MIPS_NONE
52+
Type3: R_MIPS_NONE
53+
00000003003c 000800000041 R_MIPS_PCLO16 0000000000000000 bar \+ 40020
54+
Type2: R_MIPS_NONE
55+
Type3: R_MIPS_NONE
56+
000000030040 000800000041 R_MIPS_PCLO16 0000000000000000 bar \+ 3802c
57+
Type2: R_MIPS_NONE
58+
Type3: R_MIPS_NONE
59+
000000030044 000900000006 R_MIPS_LO16 0000000000000000 baz \+ 0
60+
Type2: R_MIPS_NONE
61+
Type3: R_MIPS_NONE
62+
000000030048 000800000041 R_MIPS_PCLO16 0000000000000000 bar \+ 38038
63+
Type2: R_MIPS_NONE
64+
Type3: R_MIPS_NONE
65+
00000003004c 000800000041 R_MIPS_PCLO16 0000000000000000 bar \+ 40030
66+
Type2: R_MIPS_NONE
67+
Type3: R_MIPS_NONE
68+
000000030050 000800000040 R_MIPS_PCHI16 0000000000000000 bar \+ 3803c
69+
Type2: R_MIPS_NONE
70+
Type3: R_MIPS_NONE
71+
000000030054 000900000005 R_MIPS_HI16 0000000000000000 baz \+ 0
72+
Type2: R_MIPS_NONE
73+
Type3: R_MIPS_NONE
74+
000000030058 000800000040 R_MIPS_PCHI16 0000000000000000 bar \+ 38048
75+
Type2: R_MIPS_NONE
76+
Type3: R_MIPS_NONE
77+
00000003005c 000800000040 R_MIPS_PCHI16 0000000000000000 bar \+ 40040
78+
Type2: R_MIPS_NONE
79+
Type3: R_MIPS_NONE

‎gas/testsuite/gas/mips/pcrel-hilo-addend.d‎

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
#objdump: -dr --prefix-addresses --show-raw-insn
2+
#name: MIPSr6 PCHI16/PCLO16 in-place addends (o32)
3+
#as: -mabi=32 -mno-pdr
4+
#source: pcrel-hilo.s
5+
6+
.*: +file format .*mips.*
7+
8+
Disassembly of section \.text:
9+
00000000 <[^>]*> ec9e0000 auipc a0,0x0
10+
0: R_MIPS_PCHI16 bar
11+
00000004 <[^>]*> 3c050000 lui a1,0x0
12+
4: R_MIPS_HI16 baz
13+
00000008 <[^>]*> ecde0000 auipc a2,0x0
14+
8: R_MIPS_PCHI16 bar
15+
0000000c <[^>]*> ecfe0001 auipc a3,0x1
16+
c: R_MIPS_PCHI16 bar
17+
00000010 <[^>]*> 24847ffc addiu a0,a0,32764
18+
10: R_MIPS_PCLO16 bar
19+
00000014 <[^>]*> 24a50000 addiu a1,a1,0
20+
14: R_MIPS_LO16 baz
21+
00000018 <[^>]*> 24c68008 addiu a2,a2,-32760
22+
18: R_MIPS_PCLO16 bar
23+
0000001c <[^>]*> 24e70000 addiu a3,a3,0
24+
1c: R_MIPS_PCLO16 bar
25+
00000020 <[^>]*> ec9e0001 auipc a0,0x1
26+
20: R_MIPS_PCHI16 bar
27+
00000024 <[^>]*> 3c050000 lui a1,0x0
28+
24: R_MIPS_HI16 baz
29+
00000028 <[^>]*> ecde0001 auipc a2,0x1
30+
28: R_MIPS_PCHI16 bar
31+
0000002c <[^>]*> ecfe0001 auipc a3,0x1
32+
2c: R_MIPS_PCHI16 bar
33+
\.\.\.
34+
00030030 <[^>]*> 2484801c addiu a0,a0,-32740
35+
30030: R_MIPS_PCLO16 bar
36+
00030034 <[^>]*> 24a50000 addiu a1,a1,0
37+
30034: R_MIPS_LO16 baz
38+
00030038 <[^>]*> 24c68028 addiu a2,a2,-32728
39+
30038: R_MIPS_PCLO16 bar
40+
0003003c <[^>]*> 24e70020 addiu a3,a3,32
41+
3003c: R_MIPS_PCLO16 bar
42+
00030040 <[^>]*> 2410802c li s0,-32724
43+
30040: R_MIPS_PCLO16 bar
44+
00030044 <[^>]*> 24110000 li s1,0
45+
30044: R_MIPS_LO16 baz
46+
00030048 <[^>]*> 24128038 li s2,-32712
47+
30048: R_MIPS_PCLO16 bar
48+
0003004c <[^>]*> 24130030 li s3,48
49+
3004c: R_MIPS_PCLO16 bar
50+
00030050 <[^>]*> ec9e0004 auipc a0,0x4
51+
30050: R_MIPS_PCHI16 bar
52+
00030054 <[^>]*> 3c050000 lui a1,0x0
53+
30054: R_MIPS_HI16 baz
54+
00030058 <[^>]*> ecde0004 auipc a2,0x4
55+
30058: R_MIPS_PCHI16 bar
56+
0003005c <[^>]*> ecfe0004 auipc a3,0x4
57+
3005c: R_MIPS_PCHI16 bar
58+
00030060 <[^>]*> 00902021 addu a0,a0,s0
59+
00030064 <[^>]*> 00b12821 addu a1,a1,s1
60+
00030068 <[^>]*> 00d23021 addu a2,a2,s2
61+
0003006c <[^>]*> 00f33821 addu a3,a3,s3
62+
00030070 <[^>]*> d81f0000 jrc ra
63+
\.\.\.

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