RISC-V: Prohibit combination of 'E' and 'H'

According to the ratified privileged specification (version 20211203),
it says:

> The hypervisor extension depends on an "I" base integer ISA with 32 x
> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.

Also in the latest draft, it also prohibits RV64E with the 'H' extension.
This commit prohibits the combination of 'E' and 'H' extensions.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_parse_check_conflicts): Prohibit 'E' and
	'H' combinations.

gas/ChangeLog:

	* testsuite/gas/riscv/march-fail-rv32eh.d: New failure test to
	make sure that RV32E + 'H' is prohibited.
	* testsuite/gas/riscv/march-fail-rv32eh.l: Likewise.

Author: a4lg

bfd/elfxx-riscv.c

@@ -1949,6 +1949,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
 	(_("rv%d does not support the `e' extension"), xlen);
       no_conflict = false;
     }
+  if (riscv_subset_supports (rps, "e")
+      && riscv_subset_supports (rps, "h"))
+    {
+      rps->error_handler
+	(_("rv%de does not support the `h' extension"), xlen);
+      no_conflict = false;
+    }
   if (riscv_lookup_subset (rps->subset_list, "q", &subset)
       && (subset->major_version < 2 || (subset->major_version == 2
 					&& subset->minor_version < 2))

gas/testsuite/gas/riscv/march-fail-rv32eh.d

@@ -0,0 +1,3 @@
+#as: -march=rv32eh
+#source: empty.s
+#error_output: march-fail-rv32eh.l

gas/testsuite/gas/riscv/march-fail-rv32eh.l

@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*Error: .*rv32e does not support the `h' extension