UNRATIFIED RISC-V: Add 'Zicfilp' extension

[DO NOT MERGE]
Until the 'Zicfilp' extension is frozen/ratified and final version number
is determined, this patch should not be merged upstream. This commit uses
unratified version 0.1 as in the documentation (instead of possible 1.0
after ratification).

This commit adds RISC-V Landing Pads extension (Zicfilp) based on
the document version 0.1 (latest git revision):
<riscv/riscv-cfi@c6a8311>

**Important Note**

The "lpad" instruction requires 4-byte alignment to complete without
exceptions but this is not currently enforced by the assembler.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zicfilp' extension
	to valid 'Z' extension list.
	(riscv_multi_subset_supports): Support new instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zicfilp.s: New test.
	* testsuite/gas/riscv/zicfilp.d: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_LPAD, MASK_LPAD): New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class INSN_CLASS_ZICFILP.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Although not strictly a hint, add
	"lpad" to the list of standard hints because of its encoding.

Author: a4lg

bfd/elfxx-riscv.c

@@ -1256,6 +1256,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicfilp",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },
   {"zicfiss",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },
   {"zicond",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
@@ -2395,6 +2396,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zicbop");
     case INSN_CLASS_ZICBOZ:
       return riscv_subset_supports (rps, "zicboz");
+    case INSN_CLASS_ZICFILP:
+      return riscv_subset_supports (rps, "zicfilp");
     case INSN_CLASS_ZICFISS:
       return riscv_subset_supports (rps, "zicfiss");
     case INSN_CLASS_ZICOND:
@@ -2594,6 +2597,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicbop";
     case INSN_CLASS_ZICBOZ:
       return "zicboz";
+    case INSN_CLASS_ZICFILP:
+      return "zicfilp";
     case INSN_CLASS_ZICFISS:
       return "zicfiss";
     case INSN_CLASS_ZICOND:

gas/testsuite/gas/riscv/zicfilp.d

@@ -0,0 +1,13 @@
+#as: -march=rv32ic_zicfilp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+12345017[ 	]+lpad[ 	]+0x12345
+[ 	]+[0-9a-f]+:[ 	]+12345017[ 	]+lpad[ 	]+0x12345
+[ 	]+[0-9a-f]+:[ 	]+0001[ 	]+nop
+[ 	]+[0-9a-f]+:[ 	]+f0123017[ 	]+lpad[ 	]+0xf0123
+[ 	]+[0-9a-f]+:[ 	]+f0123017[ 	]+lpad[ 	]+0xf0123

gas/testsuite/gas/riscv/zicfilp.s

@@ -0,0 +1,14 @@
+target:
+	# lpad LPL == auipc x0, LPL
+	lpad	0x12345
+	auipc	zero, 0x12345
+
+	# Break alignment:
+	#
+	# Unaligned lpad causes illegal-instruction exception
+	# but must be disassembled (since alignment checking is a part of
+	# the lpad instruction operations).
+	c.nop
+
+	lpad	0xf0123
+	auipc	zero, 0xf0123

include/opcode/riscv-opc.h

@@ -2379,6 +2379,9 @@
 #define MASK_MOP_RR_6 0xfe00707f
 #define MATCH_MOP_RR_7 0xce004073
 #define MASK_MOP_RR_7 0xfe00707f
+/* Zicfilp instructions.  */
+#define MATCH_LPAD 0x00000017
+#define MASK_LPAD 0x00000fff
 /* Zicfiss instructions.  */
 #define MATCH_SSLOAD 0x81c04073
 #define MASK_SSLOAD 0xfffff07f

include/opcode/riscv.h

@@ -441,6 +441,7 @@ enum riscv_insn_class
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
   INSN_CLASS_ZICBOZ,
+  INSN_CLASS_ZICFILP,
   INSN_CLASS_ZICFISS,
   INSN_CLASS_H,
   INSN_CLASS_XTHEADBA,

opcodes/riscv-opc.c

@@ -368,6 +368,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"prefetch.r",  0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
 {"prefetch.w",  0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
 {"pause",       0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 },
+{"lpad",        0, INSN_CLASS_ZICFILP, "u", MATCH_LPAD, MASK_LPAD, match_opcode, 0 },
 
 /* Standard "May Be Ops" (and compressed aliases).  */
 {"ssload",     0, INSN_CLASS_ZICFISS, "d",        MATCH_SSLOAD, MASK_SSLOAD, match_rd_eq_1_or_5, INSN_DREF },