RISC-V: Support ".option [no]exact" assembler directives

This commit adds two assembler directives: ".option exact" and
".option noexact" (enable/disable the exact mode) as discussed in
<riscv-non-isa/riscv-asm-manual#122>.

When the exact mode is enabled,

1.  Linker relaxations are turned off,
2.  Instruction aliases that will change the encoding from the
    (likely non-alias) instruction with the same name are disabled
    (e.g. "addi" will never turn into "c.addi" even if optimizable) and
3.  Assembler relaxation of branch instructions are disabled
    (e.g. "blt" with a long offset will not turn into "bge + j").

The main purpose of this mode is to emit desired machine code as the
user writes, assuming the user knows constraints of their code.  So,
macros like "li" (known to be expanded into possibly complex sequences)
without single instruction encoding are not fully aware of this mode.

Currently, interactions between ".option relax/norelax" and
".option exact/noexact" are designed to be LLVM-compatible (i.e.
".option exact/noexact" imply ".option norelax/relax", respectively).

cf. <llvm/llvm-project#122483>

gas/ChangeLog:

	* config/tc-riscv.c (struct riscv_set_options): Add exact option.
	(RELAX_BRANCH_ENCODE): Encode exact option.
	(RELAX_BRANCH_EXACT): New predicate macro.
	(relaxed_branch_length): Handle exact mode cases.
	(append_insn): Pass exact option to RELAX_BRANCH_ENCODE.
	(riscv_ip): Skip instructions that would change the encoding
	when the exact mode is enabled.
	(s_riscv_option): Parse ".option exact" and ".option noexact"
	assembler directives.
	* doc/c-riscv.texi: Document new assembler directives.
	* testsuite/gas/riscv/exact.s: Test exact mode basics.
	* testsuite/gas/riscv/exact.d: Ditto.
	* testsuite/gas/riscv/exact-branch-local.s: Test conditional
	branches and unconditional jumps relative to a local symbol.
	* testsuite/gas/riscv/exact-branch-local-noexact.d: Ditto.
	* testsuite/gas/riscv/exact-branch-local-exact-ok.d: Ditto.
	* testsuite/gas/riscv/exact-branch-local-exact-fail.d: Ditto.
	* testsuite/gas/riscv/exact-branch-local-exact-fail.l: Ditto.
	* testsuite/gas/riscv/exact-branch-extern.s: Test conditional
	branches and unconditional jumps relative to an external symbol.
	* testsuite/gas/riscv/exact-branch-extern-noexact.d: Ditto.
	* testsuite/gas/riscv/exact-branch-extern-exact.d: Ditto.
	* testsuite/gas/riscv/no-relax-branch-offset-fail.s: Use exact
	mode to test various configurations and instructions.
	* testsuite/gas/riscv/no-relax-branch-offset-fail.d: Ditto.
	* testsuite/gas/riscv/no-relax-branch-offset-fail.l: Ditto.

include/ChangeLog:

	* opcode/riscv.h (INSN_NON_EXACT): New flag to represent aliases
	to reject on the exact mode.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add INSN_NON_EXACT flag to all
	instructions that should be rejected on the exact mode.

Author: a4lg

gas/config/tc-riscv.c

@@ -268,6 +268,7 @@ struct riscv_set_options
   int pic; /* Generate position-independent code.  */
   int rvc; /* Generate RVC code.  */
   int relax; /* Emit relocs the linker is allowed to relax.  */
+  int exact; /* Emit instructions without compression or relaxation.  */
   int arch_attr; /* Emit architecture and privileged elf attributes.  */
   int csr_check; /* Enable the CSR checking.  */
 };
@@ -277,6 +278,7 @@ static struct riscv_set_options riscv_opts =
   0, /* pic */
   0, /* rvc */
   1, /* relax */
+  0, /* exact */
   DEFAULT_RISCV_ATTR, /* arch_attr */
   0, /* csr_check */
 };
@@ -469,16 +471,18 @@ static bool explicit_priv_attr = false;
 static char *expr_parse_end;
 
 /* Macros for encoding relaxation state for RVC branches and far jumps.  */
-#define RELAX_BRANCH_ENCODE(uncond, rvc, length)	\
+#define RELAX_BRANCH_ENCODE(uncond, rvc, length, exact)	\
   ((relax_substateT) 					\
    (0xc0000000						\
     | ((uncond) ? 1 : 0)				\
     | ((rvc) ? 2 : 0)					\
-    | ((length) << 2)))
+    | ((length) << 2)					\
+    | ((exact) << 6)))
 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
+#define RELAX_BRANCH_EXACT(i) (((i) & 0x40) != 0)
 
 /* Is the given value a sign-extended 32-bit value?  */
 #define IS_SEXT_32BIT_NUM(x)						\
@@ -808,22 +812,25 @@ add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
 static unsigned
 relaxed_branch_length (fragS *fragp, asection *sec, int update)
 {
-  int jump, rvc, length = 8;
+  int jump, rvc, exact, length = 8;
 
   if (!fragp)
     return length;
 
   jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
   rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
+  exact = RELAX_BRANCH_EXACT (fragp->fr_subtype);
   length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
 
   /* Assume jumps are in range; the linker will catch any that aren't.  */
   length = jump ? 4 : 8;
 
-  if (fragp->fr_symbol != NULL
-      && S_IS_DEFINED (fragp->fr_symbol)
-      && !S_IS_WEAK (fragp->fr_symbol)
-      && sec == S_GET_SEGMENT (fragp->fr_symbol))
+  if (exact)
+    length = rvc ? 2 : 4;
+  else if (fragp->fr_symbol != NULL
+	   && S_IS_DEFINED (fragp->fr_symbol)
+	   && !S_IS_WEAK (fragp->fr_symbol)
+	   && sec == S_GET_SEGMENT (fragp->fr_symbol))
     {
       offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
       bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
@@ -838,7 +845,7 @@ relaxed_branch_length (fragS *fragp, asection *sec, int update)
     }
 
   if (update)
-    fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
+    fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length, exact);
 
   return length;
 }
@@ -1990,7 +1997,8 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
 	    }
 
 	  add_relaxed_insn (ip, worst_case, best_case,
-			    RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
+			    RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case,
+						 riscv_opts.exact),
 			    address_expr->X_add_symbol,
 			    address_expr->X_add_number);
 	  return;
@@ -2870,6 +2878,9 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
       if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
 	continue;
 
+      if (riscv_opts.exact && (insn->pinfo & INSN_NON_EXACT))
+	continue;
+
       if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class))
 	{
 	  error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as,
@@ -5089,6 +5100,16 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
     riscv_opts.relax = true;
   else if (strcmp (name, "norelax") == 0)
     riscv_opts.relax = false;
+  else if (strcmp (name, "exact") == 0)
+    {
+      riscv_opts.exact = true;
+      riscv_opts.relax = false;
+    }
+  else if (strcmp (name, "noexact") == 0)
+    {
+      riscv_opts.exact = false;
+      riscv_opts.relax = true;
+    }
   else if (strcmp (name, "csr-check") == 0)
     riscv_opts.csr_check = true;
   else if (strcmp (name, "no-csr-check") == 0)

gas/doc/c-riscv.texi

@@ -210,6 +210,17 @@ Enables or disables relaxation.  The RISC-V assembler and linker
 opportunistically relax some code sequences, but sometimes this behavior is not
 desirable.
 
+@item exact
+@itemx noexact
+Enables or disables exact mode.  Not only the exact mode disables linker
+relaxations, it also disables automatic instruction compression and the branch
+relaxation (both optionally change instruction encodings and/or instruction
+count).  This mode is useful in some cases where the instruction sequences, as
+exactly written, are expected to be emitted.
+
+Note that, @samp{.option exact} implies @samp{.option norelax} and
+@samp{.option noexact} implies @samp{.option relax}.
+
 @item csr-check
 @itemx no-csr-check
 Enables or disables the CSR checking.

gas/testsuite/gas/riscv/exact-branch-extern-exact.d

@@ -0,0 +1,32 @@
+#as: -march=rv32ic --defsym exact_mode=1
+#source: exact-branch-extern.s
+#objdump: -drw -Mno-aliases
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[ 	]+[0-9a-f]+:[ 	]+00b50063[ 	]+beq[ 	]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+feb51ee3[ 	]+bne[ 	]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+feb54ce3[ 	]+blt[ 	]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+feb55ae3[ 	]+bge[ 	]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+feb568e3[ 	]+bltu[ 	]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+feb576e3[ 	]+bgeu[ 	]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+d565[ 	]+c\.beqz[ 	]+a0,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_RVC_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+f17d[ 	]+c\.bnez[ 	]+a0,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_RVC_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+fea5c2e3[ 	]+blt[ 	]+a1,a0,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_BRANCH[ 	]+ext
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+[ 	]+[0-9a-f]+:[ 	]+fca052e3[ 	]+bge[ 	]+zero,a0,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+fc0550e3[ 	]+bge[ 	]+a0,zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_BRANCH[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+0001[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+fbbff56f[ 	]+jal[ 	]+a0,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+bf5d[ 	]+c\.j[ 	]+[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_RVC_JUMP[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+3f55[ 	]+c\.jal[ 	]+[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_RVC_JUMP[ 	]+ext

gas/testsuite/gas/riscv/exact-branch-extern-noexact.d

@@ -0,0 +1,50 @@
+#as: -march=rv32ic
+#source: exact-branch-extern.s
+#objdump: -drw -Mno-aliases
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[ 	]+[0-9a-f]+:[ 	]+00b51463[ 	]+bne[ 	]+a0,a1,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+ffdff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00b50463[ 	]+beq[ 	]+a0,a1,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+ff5ff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00b55463[ 	]+bge[ 	]+a0,a1,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+fedff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00b54463[ 	]+blt[ 	]+a0,a1,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+fe5ff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00b57463[ 	]+bgeu[ 	]+a0,a1,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+fddff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00b56463[ 	]+bltu[ 	]+a0,a1,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+fd5ff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00051463[ 	]+bne[ 	]+a0,zero,[0-9a-f]+.*
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+[ 	]+[0-9a-f]+:[ 	]+fbdff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00a5c463[ 	]+blt[ 	]+a1,a0,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+fb5ff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00a5f463[ 	]+bgeu[ 	]+a1,a0,[0-9a-f]+.*
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+[ 	]+[0-9a-f]+:[ 	]+00a5e463[ 	]+bltu[ 	]+a1,a0,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+fa5ff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00051463[ 	]+bne[ 	]+a0,zero,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+f9dff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00050463[ 	]+beq[ 	]+a0,zero,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+f95ff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00055463[ 	]+bge[ 	]+a0,zero,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+f8dff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+00a05463[ 	]+bge[ 	]+zero,a0,[0-9a-f]+.*
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+[ 	]+[0-9a-f]+:[ 	]+00a04463[ 	]+blt[ 	]+zero,a0,[0-9a-f]+.*
+[ 	]+[0-9a-f]+:[ 	]+f7dff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
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+[ 	]+[0-9a-f]+:[ 	]+f6bff06f[ 	]+jal[ 	]+zero,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext
+[ 	]+[0-9a-f]+:[ 	]+f67ff0ef[ 	]+jal[ 	]+ra,[0-9a-f]+.*[0-9a-f]+:[ 	]+R_RISCV_JAL[ 	]+ext

gas/testsuite/gas/riscv/exact-branch-extern.s

@@ -0,0 +1,40 @@
+.ifdef exact_mode
+	.option	exact
+.else
+	.option	noexact
+.endif
+	.extern	ext
+
+	## Conditional Branches
+
+	# Basic instructions
+	beq	a0, a1, ext
+	bne	a0, a1, ext
+	blt	a0, a1, ext
+	bge	a0, a1, ext
+	bltu	a0, a1, ext
+	bgeu	a0, a1, ext
+
+	# Compressed instructions
+	c.beqz	a0, ext
+	c.bnez	a0, ext
+
+	# Aliases
+	bgt	a0, a1, ext
+	ble	a0, a1, ext
+	bgtu	a0, a1, ext
+	bleu	a0, a1, ext
+	beqz	a0, ext
+	bnez	a0, ext
+	bltz	a0, ext
+	bgtz	a0, ext
+	blez	a0, ext
+	bgez	a0, ext
+
+	c.nop
+
+	## Unconditional Jumps (normal and compressed)
+
+	jal	a0, ext
+	c.j	ext
+	c.jal	ext	# RV32C only

gas/testsuite/gas/riscv/exact-branch-local-exact-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv32ic --defsym exact_mode=1 --defsym long_branch=1
+#source: exact-branch-local.s
+#error_output: exact-branch-local-exact-fail.l

gas/testsuite/gas/riscv/exact-branch-local-exact-fail.l

@@ -0,0 +1,43 @@
+.*Assembler messages:
+.*:93: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:94: Error: offset \(-4098\) is invalid for B-type immediate
+.*:95: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:96: Error: offset \(-4098\) is invalid for B-type immediate
+.*:97: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:98: Error: offset \(-4098\) is invalid for B-type immediate
+.*:99: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:100: Error: offset \(-4098\) is invalid for B-type immediate
+.*:101: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:102: Error: offset \(-4098\) is invalid for B-type immediate
+.*:103: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:104: Error: offset \(-4098\) is invalid for B-type immediate
+.*:105: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:106: Error: offset \(-4098\) is invalid for B-type immediate
+.*:107: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:108: Error: offset \(-4098\) is invalid for B-type immediate
+.*:109: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:110: Error: offset \(-4098\) is invalid for B-type immediate
+.*:111: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:112: Error: offset \(-4098\) is invalid for B-type immediate
+.*:113: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:114: Error: offset \(-4098\) is invalid for B-type immediate
+.*:115: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:116: Error: offset \(-4098\) is invalid for B-type immediate
+.*:117: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:118: Error: offset \(-4098\) is invalid for B-type immediate
+.*:119: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:120: Error: offset \(-4098\) is invalid for B-type immediate
+.*:121: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:122: Error: offset \(-4098\) is invalid for B-type immediate
+.*:123: Error: offset \(\+4096\) is invalid for B-type immediate
+.*:124: Error: offset \(-4098\) is invalid for B-type immediate
+.*:128: Error: offset \(\+256\) is invalid for CB-type immediate
+.*:129: Error: offset \(-258\) is invalid for CB-type immediate
+.*:130: Error: offset \(\+256\) is invalid for CB-type immediate
+.*:131: Error: offset \(-258\) is invalid for CB-type immediate
+.*:132: Error: offset \(\+1048576\) is invalid for J-type immediate
+.*:133: Error: offset \(-1048578\) is invalid for J-type immediate
+.*:134: Error: offset \(\+2048\) is invalid for CJ-type immediate
+.*:135: Error: offset \(-2050\) is invalid for CJ-type immediate
+.*:136: Error: offset \(\+2048\) is invalid for CJ-type immediate
+.*:137: Error: offset \(-2050\) is invalid for CJ-type immediate

gas/testsuite/gas/riscv/exact-branch-local-exact-ok.d

@@ -0,0 +1,75 @@
+#as: -march=rv32ic --defsym exact_mode=1
+#source: exact-branch-local.s
+#objdump: -d -Mno-aliases
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
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