RISC-V: Add complex implications from 'C'+'[DF]'

The 'C' extension and its subsets have complex relations, depending on
the implemented floating point extensions.

They are the expansions related in this context:

'C'             == 'Zca'
'C' + 'F'       == 'Zca' + 'Zcf'         + 'F' (RV32)
'C' + 'F'       == 'Zca'                 + 'F' (RV64)
'C' + 'F' + 'D' == 'Zca' + 'Zcf' + 'Zcd' + 'F' + 'D' (RV32)
'C' + 'F' + 'D' == 'Zca'         + 'Zcd' + 'F' + 'D' (RV64)
[they exclude dependencies from 'F' and 'D']

This commit implements those implications.

Note that some test cases are modified to reflect new compressed
instruction extensions:

1.  Test cases that use ".option arch, -c" to turn off RVC
    (at least the 'Zca' extension must be also turned off).
2.  Test cases that test RISC-V attributes and/or mapping symbols
    when the 'C' extension is enabled.

bfd/ChangeLog:

	* elfxx-riscv.c (check_implicit_for_d_c): New.
	(check_implicit_for_f_c): New.
	(riscv_implicit_subsets): Add unconditional implication,
	'C' -> 'Zca'.  Add conditional implications, 'D' -> 'Zcd'
	and 'F' -> 'Zcf'.

gas/ChangeLog:

	* testsuite/gas/riscv/march-imply-c.d: Test implied
	extensions from 'C' alone.
	* testsuite/gas/riscv/march-imply-c-d-32.d: New to test implied
	extensions from 'C' and 'D' on RV32.
	* testsuite/gas/riscv/march-imply-c-d-64.d: New to test implied
	extensions from 'C' and 'D' on RV64.
	* testsuite/gas/riscv/attribute-10.d: Reflect reorganization of
	compressed instruction extensions.
	* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
	* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
	* testsuite/gas/riscv/dis-addr-overflow.s: Likewise.
	* testsuite/gas/riscv/mapping-symbols.d: Likewise.
	* testsuite/gas/riscv/mapping.s: Likewise.
	* testsuite/gas/riscv/march-ok-reorder.d: Likewise.
	* testsuite/gas/riscv/option-arch-01.s: Likewise.
	* testsuite/gas/riscv/option-arch-01b.d: Likewise.
	* testsuite/gas/riscv/option-arch-02.d: Likewise.
	* testsuite/gas/riscv/option-arch-02.s: Likewise.
	* testsuite/gas/riscv/option-arch-03.d: Likewise.
	* testsuite/gas/riscv/option-arch-03.s: Likewise.

Author: a4lg

bfd/elfxx-riscv.c

@@ -1099,6 +1099,29 @@ check_implicit_for_i (riscv_parse_subset_t *rps ATTRIBUTE_UNUSED,
 	      && subset->minor_version < 1));
 }
 
+/* Add the IMPLICIT only when the 'C' extension is also available.  */
+
+static bool
+check_implicit_for_d_c (riscv_parse_subset_t *rps,
+			const riscv_implicit_subset_t *implicit
+			    ATTRIBUTE_UNUSED,
+			const riscv_subset_t *subset ATTRIBUTE_UNUSED)
+{
+  return riscv_subset_supports (rps, "c");
+}
+
+/* Add the IMPLICIT only when the 'C' extension is also available
+   and XLEN is 32.  */
+
+static bool
+check_implicit_for_f_c (riscv_parse_subset_t *rps,
+			const riscv_implicit_subset_t *implicit
+			    ATTRIBUTE_UNUSED,
+			const riscv_subset_t *subset ATTRIBUTE_UNUSED)
+{
+  return *rps->xlen == 32 && check_implicit_for_d_c (rps, implicit, subset);
+}
+
 /* All extension implications.  */
 
 static riscv_implicit_subset_t riscv_implicit_subsets[] =
@@ -1188,6 +1211,7 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] =
   {"zvksg", "zvkg",	check_implicit_always},
   {"zvksc", "zvks",	check_implicit_always},
   {"zvksc", "zvbc",	check_implicit_always},
+  {"c", "zca",		check_implicit_always},
   {"zcf", "zca",	check_implicit_always},
   {"zcd", "zca",	check_implicit_always},
   {"zcb", "zca",	check_implicit_always},
@@ -1200,6 +1224,10 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] =
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
   {"svadu", "zicsr",		check_implicit_always},
+  /* Complex implications (that should be checked after others).  */
+  {"d", "zcd",		check_implicit_for_d_c},
+  {"f", "zcf",		check_implicit_for_f_c},
+  /* Tail of the list.  */
   {NULL, NULL, NULL}
 };
 

gas/testsuite/gas/riscv/attribute-10.d

@@ -3,4 +3,4 @@
 #source: empty.s
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zca1p0_zcd1p0_zcf1p0"

gas/testsuite/gas/riscv/dis-addr-overflow-32.d

@@ -1,4 +1,4 @@
-#as: -march=rv32ic
+#as: -march=rv32i_zca
 #source: dis-addr-overflow.s
 #objdump: -d
 

gas/testsuite/gas/riscv/dis-addr-overflow-64.d

@@ -1,4 +1,4 @@
-#as: -march=rv64ic -defsym rv64=1
+#as: -march=rv64i_zca -defsym rv64=1
 #source: dis-addr-overflow.s
 #objdump: -d
 

gas/testsuite/gas/riscv/dis-addr-overflow.s

@@ -24,7 +24,7 @@ topbase = 0
 
 target:
 	.option	push
-	.option	arch, -c
+	.option	arch, -zca
 	## Use hi_addr
 	# Load
 	lui	t0, 0xfffff
@@ -50,7 +50,7 @@ target:
 	c.addi	t6, -20
 .ifdef rv64
 	.option	push
-	.option	arch, -c
+	.option	arch, -zca
 	# ADDIW (not compressed)
 	lui	s6, 0xffff8
 	addiw	s7, s6, -24

gas/testsuite/gas/riscv/mapping-symbols.d

@@ -9,44 +9,44 @@ SYMBOL TABLE:
 0+00 l    d  .data	0+00 .data
 0+00 l    d  .bss	0+00 .bss
 0+00 l    d  .text.cross.section.A	0+00 .text.cross.section.A
-0+00 l       .text.cross.section.A	0+00 \$xrv32i2p1_c2p0
+0+00 l       .text.cross.section.A	0+00 \$xrv32i2p1_zca1p0
 0+00 l    d  .text.corss.section.B	0+00 .text.corss.section.B
-0+00 l       .text.corss.section.B	0+00 \$xrv32i2p1_c2p0
+0+00 l       .text.corss.section.B	0+00 \$xrv32i2p1_zca1p0
 0+02 l       .text.corss.section.B	0+00 \$xrv32i2p1
 0+00 l    d  .text.data	0+00 .text.data
 0+00 l       .text.data	0+00 \$d
-0+08 l       .text.data	0+00 \$xrv32i2p1_c2p0
+0+08 l       .text.data	0+00 \$xrv32i2p1_zca1p0
 0+0c l       .text.data	0+00 \$d
 0+00 l    d  .text.odd.align.start.insn	0+00 .text.odd.align.start.insn
-0+00 l       .text.odd.align.start.insn	0+00 \$xrv32i2p1_c2p0
+0+00 l       .text.odd.align.start.insn	0+00 \$xrv32i2p1_zca1p0
 0+02 l       .text.odd.align.start.insn	0+00 \$d
 0+08 l       .text.odd.align.start.insn	0+00 \$xrv32i2p1
 0+00 l    d  .text.odd.align.start.data	0+00 .text.odd.align.start.data
 0+00 l       .text.odd.align.start.data	0+00 \$d
 0+00 l    d  .text.zero.fill.first	0+00 .text.zero.fill.first
-0+00 l       .text.zero.fill.first	0+00 \$xrv32i2p1_c2p0
+0+00 l       .text.zero.fill.first	0+00 \$xrv32i2p1_zca1p0
 0+00 l    d  .text.zero.fill.last	0+00 .text.zero.fill.last
-0+00 l       .text.zero.fill.last	0+00 \$xrv32i2p1_c2p0
+0+00 l       .text.zero.fill.last	0+00 \$xrv32i2p1_zca1p0
 0+02 l       .text.zero.fill.last	0+00 \$x
 0+00 l    d  .text.zero.fill.align.A	0+00 .text.zero.fill.align.A
-0+00 l       .text.zero.fill.align.A	0+00 \$xrv32i2p1_c2p0
+0+00 l       .text.zero.fill.align.A	0+00 \$xrv32i2p1_zca1p0
 0+00 l    d  .text.zero.fill.align.B	0+00 .text.zero.fill.align.B
 0+00 l       .text.zero.fill.align.B	0+00 \$xrv32i2p1
 0+00 l    d  .text.last.section	0+00 .text.last.section
 0+00 l       .text.last.section	0+00 \$xrv32i2p1
 0+04 l       .text.last.section	0+00 \$d
 0+00 l    d  .text.section.padding	0+00 .text.section.padding
-0+00 l       .text.section.padding	0+00 \$xrv32i2p1_c2p0
-0+04 l       .text.section.padding	0+00 \$xrv32i2p1_a2p1_c2p0
+0+00 l       .text.section.padding	0+00 \$xrv32i2p1_zca1p0
+0+04 l       .text.section.padding	0+00 \$xrv32i2p1_a2p1_zca1p0
 0+06 l       .text.section.padding	0+00 \$d
 0+00 l    d  .text.relax.align	0+00 .text.relax.align
-0+00 l       .text.relax.align	0+00 \$xrv32i2p1_c2p0
+0+00 l       .text.relax.align	0+00 \$xrv32i2p1_zca1p0
 0+08 l       .text.relax.align	0+00 \$xrv32i2p1
 0+0a l       .text.section.padding	0+00 \$x
 0+03 l       .text.odd.align.start.insn	0+00 \$d
 0+04 l       .text.odd.align.start.insn	0+00 \$x
 0+01 l       .text.odd.align.start.data	0+00 \$d
-0+02 l       .text.odd.align.start.data	0+00 \$xrv32i2p1_c2p0
+0+02 l       .text.odd.align.start.data	0+00 \$xrv32i2p1_zca1p0
 0+00 l    d  .riscv.attributes	0+00 .riscv.attributes
 0+00 g       .text.cross.section.A	0+00 funcA
 0+00 g       .text.corss.section.B	0+00 funcB

gas/testsuite/gas/riscv/mapping.s

@@ -1,4 +1,4 @@
-.attribute arch, "rv32ic"
+.attribute arch, "rv32i_zca"
 .option norelax			# FIXME: assembler fill the paddings after parsing everything,
 				# so we probably won't fill anything for the norelax region when
 				# the riscv_opts.relax is enabled at somewhere.
@@ -8,21 +8,21 @@
 .global funcA
 funcA:
 addi	a0, zero, 1		# rv32i
-.option arch, +c
-j	funcA			# rv32ic
+.option arch, +zca
+j	funcA			# rv32i_zca
 .section .text.corss.section.B, "ax"
 .globl funcB
 funcB:
-addi	a0, zero, 2		# rv32ic, need to be added since start of section
-.option arch, -c
+addi	a0, zero, 2		# rv32i_zca, need to be added since start of section
+.option arch, -zca
 j	funcB			# rv32i
 .option pop
 
 .section .text.data, "ax"
 .option push
 .word	0			# $d
 .long	1
-addi	a0, zero, 1		# rv32ic
+addi	a0, zero, 1		# rv32i_zca
 .data
 .word	2			# don't add mapping symbols for non-text section
 .section .text.data
@@ -35,34 +35,34 @@ addi	a0, zero, 2		# $x, but same as previous addi, so removed
 .section .text.odd.align.start.insn, "ax"
 .option push
 .option norelax
-.option arch, +c
-addi	a0, zero, 1		# $xrv32ic
+.option arch, +zca
+addi	a0, zero, 1		# $xrv32i_zca
 .byte	1			# $d
-.option arch, -c
+.option arch, -zca
 .align	3			# odd alignment, $x replaced by $d + $x
 addi	a0, zero, 2		# $xrv32i
 .option pop
 
 .section .text.odd.align.start.data, "ax"
 .option push
 .option norelax
-.option arch, +c
+.option arch, +zca
 .byte	1			# $d
-.align	2			# odd alignment, $xrv32ic replaced by $d + $xrv32ic
+.align	2			# odd alignment, $xrv32i_zca replaced by $d + $xrv32i_zca
 addi	a0, zero, 1
 .option pop
 
 .section .text.zero.fill.first, "ax"
 .option push
 .option norelax
 .fill	1, 0, 0			# $d with zero size, removed in make_mapping_symbol
-addi	a0, zero, 1		# $xrv32ic
+addi	a0, zero, 1		# $xrv32i_zca
 .option pop
 
 .section .text.zero.fill.last, "ax"
 .option push
 .option norelax
-addi	a0, zero, 1		# $xrv32ic
+addi	a0, zero, 1		# $xrv32i_zca
 .fill	1, 0, 0			# $d with zero size, removed in make_mapping_symbol
 addi	a0, zero, 2		# $x, FIXME: need find a way to remove?
 .option pop
@@ -71,8 +71,8 @@ addi	a0, zero, 2		# $x, FIXME: need find a way to remove?
 .section .text.zero.fill.align.A, "ax"
 .option push
 .option norelax
-.align	2			# $xrv32ic, .align and .fill are in the different frag, so neither be removed
-.fill	1, 0, 0			# $d with zero size, removed in make_mapping_symbol when adding $xrv32ic
+.align	2			# $xrv32i_zca, .align and .fill are in the different frag, so neither be removed
+.fill	1, 0, 0			# $d with zero size, removed in make_mapping_symbol when adding $xrv32i_zca
 addi	a0, zero, 1		# $x, should be removed in riscv_check_mapping_symbols
 addi	a0, zero, 2
 .option pop
@@ -81,18 +81,18 @@ addi	a0, zero, 2
 .section .text.zero.fill.align.B, "ax"
 .option push
 .option norelax
-.align	2			# $xrv32ic, .align and .fill are in the different frag, so neither be removed,
+.align	2			# $xrv32i_zca, .align and .fill are in the different frag, so neither be removed,
 				# but will be removed in riscv_check_mapping_symbols
-.fill	1, 0, 0			# $d with zero size, removed in make_mapping_symbol when adding $xrv32ic
-.option arch, -c
+.fill	1, 0, 0			# $d with zero size, removed in make_mapping_symbol when adding $xrv32i_zca
+.option arch, -zca
 addi	a0, zero, 1		# $xrv32i
 addi	a0, zero, 2
 .option pop
 
 .section .text.last.section, "ax"
 .option push
 .option norelax
-.option arch, -c
+.option arch, -zca
 addi	a0, zero, 1		# $xrv32i
 .word	1			# $d
 .align	2			# zero section padding, $x at the end of section, removed in riscv_check_mapping_symbols
@@ -102,20 +102,20 @@ addi	a0, zero, 1		# $xrv32i
 .option push
 .option norelax
 .align	2
-addi	a0, zero, 1		# $rv32ic
+addi	a0, zero, 1		# $rv32i_zca
 .option arch, +a
 .align	2			# 2-byte padding, $x, removed
-addi	a0, zero, 2		# $xrv32iac
+addi	a0, zero, 2		# $xrv32ia_zca
 .word	1			# $d
 .option pop			# 2-byte padding, $x
 
 .section .text.relax.align, "ax"
 .option push
 .option relax
-.option arch, rv32ic
-.balign	4			# $xrv32ic, add at the start of section
+.option arch, rv32i_zca
+.balign	4			# $xrv32i_zca, add at the start of section
 addi	a0, zero, 1		# $x, won't added
-.option arch, -c
+.option arch, -zca
 .align	3			# $x, won't added
 addi	a0, zero, 2		# $xrv32i
 .option pop

gas/testsuite/gas/riscv/march-imply-c-d-32.d

@@ -0,0 +1,6 @@
+#as: -march=rv32idc -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0"

gas/testsuite/gas/riscv/march-imply-c-d-64.d

@@ -0,0 +1,6 @@
+#as: -march=rv64idc -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0"

gas/testsuite/gas/riscv/march-imply-c.d

@@ -0,0 +1,6 @@
+#as: -march=rv32ic -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_c2p0_zca1p0"