UNRATIFIED RISC-V: Add 'Zvfbfmin' extension

[DO NOT MERGE]
Until RISC-V BF16 extensions are frozen/ratified and the final version
number is determined, this patch should not be merged upstream. This
commit uses unratified version 0.8 as in the latest PDF documentation
(instead of possible 1.0 after ratification).

This commit adds support for the 'Zvfbfmin' extension, the vector BF16
conversion only extension, consisting of two narrowing / widening conversion
instructions between BF16 and FP32.

This commit is based on the following specification:
<riscv/riscv-bfloat16@5578e34>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets) Add implications 'Zvfbfmin'
	-> 'Zfbfmin' and 'Zve32f'.
	(riscv_supported_std_z_ext): Add 'Zvfbfmin'.
	(riscv_multi_subset_supports): Add support to INSN_CLASS_ZVFBFMIN.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvfbfmin.s: New test.
	* testsuite/gas/riscv/zvfbfmin.d: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W,
	MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction class
	INSN_CLASS_ZVFBFMIN.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add 'Zvfbfmin' instructions.

Author: a4lg

bfd/elfxx-riscv.c

@@ -1110,6 +1110,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"v", "d",		check_implicit_always},
   {"v", "zve64d",	check_implicit_always},
   {"v", "zvl128b",	check_implicit_always},
+  {"zvfbfmin", "zfbfmin",	check_implicit_always},
+  {"zvfbfmin", "zve32f",	check_implicit_always},
   {"zvfh", "zvfhmin",	check_implicit_always},
   {"zvfh", "zfhmin",	check_implicit_always},
   {"zvfhmin", "zve32f",	check_implicit_always},
@@ -1292,6 +1294,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvfbfmin",		ISA_SPEC_CLASS_DRAFT,		0, 8,  0 },
   {"zvfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2508,6 +2511,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_ZVBC:
       return riscv_subset_supports (rps, "zvbc");
+    case INSN_CLASS_ZVFBFMIN:
+      return riscv_subset_supports (rps, "zvfbfmin");
     case INSN_CLASS_ZVKG:
       return riscv_subset_supports (rps, "zvkg");
     case INSN_CLASS_ZVKNED:
@@ -2728,6 +2733,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64d' or `zve64f' or `zve32f");
     case INSN_CLASS_ZVBB:
       return _("zvbb");
+    case INSN_CLASS_ZVFBFMIN:
+      return "zvfbfmin";
     case INSN_CLASS_ZVBC:
       return _("zvbc");
     case INSN_CLASS_ZVKG:

gas/testsuite/gas/riscv/zvfbfmin.d

@@ -0,0 +1,12 @@
+#as: -march=rv32i_zvfbfmin
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+4a8e9257[ 	]+vfncvtbf16\.f\.f\.w[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+488e9257[ 	]+vfncvtbf16\.f\.f\.w[ 	]+v4,v8,v0\.t
+[ 	]+[0-9a-f]+:[ 	]+4a869257[ 	]+vfwcvtbf16\.f\.f\.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48869257[ 	]+vfwcvtbf16\.f\.f\.v[ 	]+v4,v8,v0\.t

gas/testsuite/gas/riscv/zvfbfmin.s

@@ -0,0 +1,5 @@
+target:
+	vfncvtbf16.f.f.w v4, v8
+	vfncvtbf16.f.f.w v4, v8, v0.t
+	vfwcvtbf16.f.f.v v4, v8
+	vfwcvtbf16.f.f.v v4, v8, v0.t

include/opcode/riscv-opc.h

@@ -2168,6 +2168,11 @@
 #define MASK_VCLMULH_VV 0xfc00707f
 #define MATCH_VCLMULH_VX 0x34006057
 #define MASK_VCLMULH_VX 0xfc00707f
+/* Zvfbfmin instructions.  */
+#define MATCH_VFNCVTBF16_F_F_W 0x480e9057
+#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
+#define MATCH_VFWCVTBF16_F_F_V 0x48069057
+#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
 /* Zvkg instructions.  */
 #define MATCH_VGHSH_VV 0xb2002077
 #define MASK_VGHSH_VV 0xfe00707f
@@ -3374,6 +3379,9 @@ DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
 DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
 DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
 DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
+/* Zvfbfmin instructions.  */
+DECLARE_INSN(vfncvtbf16_f_f_w, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
+DECLARE_INSN(vfwcvtbf16_f_f_v, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
 /* Zvkg instructions.  */
 DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
 DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)

include/opcode/riscv.h

@@ -427,6 +427,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
+  INSN_CLASS_ZVFBFMIN,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,

opcodes/riscv-opc.c

@@ -1926,6 +1926,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
 {"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
 
+/* Zvfbfmin instructions.  */
+{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
+{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
+
 /* Zvkg instructions.  */
 {"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
 {"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},