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RISC-V: Allocate "various" operand type
This commit intends to move operands that require very special handling or operand types that are so minor (e.g. only useful on a few instructions) under "W". I also intend this "W" to be "temporary" operand storage until we can find good two character (or less) operand type. In this commit, prefetch offset operand "f" for 'Zicbop' extension is moved to "Wif" because of its special handling (and allocating single character "f" for this operand type seemed too much). Current expected allocation guideline is as follows: 1. 'W' 2. The most closely related single-letter extension in lowercase (strongly recommended but not mandatory) 3. Identify operand type The author currently plans to allocate following three-character operand types (for operands including instructions from unratified extensions). 1. "Wif" ('Zicbop': fetch offset) 2. "Wfv" (unratified 'Zfa': value operand from FLI.[HSDQ] instructions) 3. "Wfm" / "WfM" 'Zfh', 'F', 'D', 'Q': rounding modes "m" with special handling solely for widening conversion instructions. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn, riscv_ip): Move from "f" to "Wif". opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Move from "f" to "Wif". * riscv-opc.c (riscv_opcodes): Reflect new operand type.
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3 files changed

+71
-25
lines changed

3 files changed

+71
-25
lines changed

‎gas/config/tc-riscv.c‎

Lines changed: 47 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1362,7 +1362,6 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
13621362
case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
13631363
case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
13641364
case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
1365-
case 'f': /* Fall through. */
13661365
case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
13671366
case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
13681367
case 'z': break; /* Zero immediate. */
@@ -1389,6 +1388,21 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
13891388
goto unknown_validate_operand;
13901389
}
13911390
break;
1391+
case 'W': /* Various operands. */
1392+
switch (*++oparg)
1393+
{
1394+
case 'i':
1395+
switch (*++oparg)
1396+
{
1397+
case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
1398+
default:
1399+
goto unknown_validate_operand;
1400+
}
1401+
break;
1402+
default:
1403+
goto unknown_validate_operand;
1404+
}
1405+
break;
13921406
case 'X': /* Integer immediate. */
13931407
{
13941408
size_t n;
@@ -3420,22 +3434,37 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
34203434
imm_expr->X_op = O_absent;
34213435
continue;
34223436

3423-
case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
3424-
if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
3425-
continue;
3426-
my_getExpression (imm_expr, asarg);
3427-
check_absolute_expr (ip, imm_expr, false);
3428-
if (((unsigned) (imm_expr->X_add_number) & 0x1fU)
3429-
|| imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2
3430-
|| imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2)
3431-
as_bad (_("improper prefetch offset (%ld)"),
3432-
(long) imm_expr->X_add_number);
3433-
ip->insn_opcode |=
3434-
ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) &
3435-
~ 0x1fU);
3436-
imm_expr->X_op = O_absent;
3437-
asarg = expr_parse_end;
3438-
continue;
3437+
case 'W': /* Various operands. */
3438+
switch (*++oparg)
3439+
{
3440+
case 'i':
3441+
switch (*++oparg)
3442+
{
3443+
case 'f':
3444+
/* Prefetch offset for 'Zicbop' extension.
3445+
pseudo S-type but lower 5-bits zero. */
3446+
if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
3447+
continue;
3448+
my_getExpression (imm_expr, asarg);
3449+
check_absolute_expr (ip, imm_expr, false);
3450+
if (((unsigned) (imm_expr->X_add_number) & 0x1fU)
3451+
|| imm_expr->X_add_number >= RISCV_IMM_REACH / 2
3452+
|| imm_expr->X_add_number < -RISCV_IMM_REACH / 2)
3453+
as_bad (_ ("improper prefetch offset (%ld)"),
3454+
(long) imm_expr->X_add_number);
3455+
ip->insn_opcode |= ENCODE_STYPE_IMM (
3456+
(unsigned) (imm_expr->X_add_number) & ~0x1fU);
3457+
imm_expr->X_op = O_absent;
3458+
asarg = expr_parse_end;
3459+
continue;
3460+
default:
3461+
goto unknown_riscv_ip_operand;
3462+
}
3463+
break;
3464+
default:
3465+
goto unknown_riscv_ip_operand;
3466+
}
3467+
break;
34393468

34403469
case 'X': /* Integer immediate. */
34413470
{
@@ -3488,6 +3517,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
34883517
}
34893518
}
34903519
break;
3520+
34913521
default:
34923522
unknown_riscv_ip_operand:
34933523
as_fatal (_("internal: unknown argument type `%s'"),

‎opcodes/riscv-dis.c‎

Lines changed: 21 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -473,11 +473,6 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
473473
(int)EXTRACT_STYPE_IMM (l));
474474
break;
475475

476-
case 'f':
477-
print (info->stream, dis_style_address_offset, "%d",
478-
(int)EXTRACT_STYPE_IMM (l));
479-
break;
480-
481476
case 'a':
482477
info->target = EXTRACT_JTYPE_IMM (l) + pc;
483478
(*info->print_address_func) (info->target, info);
@@ -582,6 +577,27 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
582577
print (info->stream, dis_style_immediate, "%d", rs1);
583578
break;
584579

580+
case 'W': /* Various operands. */
581+
{
582+
switch (*++oparg)
583+
{
584+
case 'i':
585+
switch (*++oparg)
586+
{
587+
case 'f':
588+
print (info->stream, dis_style_address_offset, "%d",
589+
(int) EXTRACT_STYPE_IMM (l));
590+
break;
591+
default:
592+
goto undefined_modifier;
593+
}
594+
break;
595+
default:
596+
goto undefined_modifier;
597+
}
598+
}
599+
break;
600+
585601
case 'X': /* Integer immediate. */
586602
{
587603
size_t n;

‎opcodes/riscv-opc.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -313,9 +313,9 @@ const struct riscv_opcode riscv_opcodes[] =
313313
/* name, xlen, isa, operands, match, mask, match_func, pinfo. */
314314

315315
/* Standard hints. */
316-
{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
317-
{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
318-
{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
316+
{"prefetch.i", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
317+
{"prefetch.r", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
318+
{"prefetch.w", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
319319
{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 },
320320

321321
/* Basic RVI instructions and aliases. */

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