diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index c070394a366..fe451ff7ef6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1182,6 +1182,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, + {"zcmop", "zca", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smcntrpmf", "zicsr", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, @@ -1258,6 +1259,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zimop", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, @@ -1324,6 +1326,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmop", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2403,6 +2406,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zca"))); case INSN_CLASS_ZIHINTPAUSE: return riscv_subset_supports (rps, "zihintpause"); + case INSN_CLASS_ZIMOP: + return riscv_subset_supports (rps, "zimop"); case INSN_CLASS_M: return riscv_subset_supports (rps, "m"); case INSN_CLASS_ZMMUL: @@ -2538,6 +2543,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_ZCB_AND_ZMMUL: return (riscv_subset_supports (rps, "zcb") && riscv_subset_supports (rps, "zmmul")); + case INSN_CLASS_ZCMOP: + return riscv_subset_supports (rps, "zcmop"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2613,6 +2620,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("c' or `zca"); case INSN_CLASS_ZIHINTPAUSE: return "zihintpause"; + case INSN_CLASS_ZIMOP: + return "zimop"; case INSN_CLASS_M: return "m"; case INSN_CLASS_ZMMUL: @@ -2778,6 +2787,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zcb' and `zbb"); case INSN_CLASS_ZCB_AND_ZMMUL: return _("zcb' and `zmmul', or `zcb' and `m"); + case INSN_CLASS_ZCMOP: + return "zcmop"; case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zcmop.d b/gas/testsuite/gas/riscv/zcmop.d new file mode 100644 index 00000000000..0aa090c8e42 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmop.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_zcmop +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+6081[ ]+c\.mop\.0 +[ ]+[0-9a-f]+:[ ]+6181[ ]+c\.mop\.1 +[ ]+[0-9a-f]+:[ ]+6281[ ]+c\.mop\.2 +[ ]+[0-9a-f]+:[ ]+6381[ ]+c\.mop\.3 +[ ]+[0-9a-f]+:[ ]+6481[ ]+c\.mop\.4 +[ ]+[0-9a-f]+:[ ]+6581[ ]+c\.mop\.5 +[ ]+[0-9a-f]+:[ ]+6681[ ]+c\.mop\.6 +[ ]+[0-9a-f]+:[ ]+6781[ ]+c\.mop\.7 diff --git a/gas/testsuite/gas/riscv/zcmop.s b/gas/testsuite/gas/riscv/zcmop.s new file mode 100644 index 00000000000..8edf2e358c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmop.s @@ -0,0 +1,9 @@ +target: + c.mop.0 + c.mop.1 + c.mop.2 + c.mop.3 + c.mop.4 + c.mop.5 + c.mop.6 + c.mop.7 diff --git a/gas/testsuite/gas/riscv/zimop.d b/gas/testsuite/gas/riscv/zimop.d new file mode 100644 index 00000000000..abade445098 --- /dev/null +++ b/gas/testsuite/gas/riscv/zimop.d @@ -0,0 +1,48 @@ +#as: -march=rv32i_zimop +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+81c140f3[ ]+mop\.r\.0[ ]+ra,sp +[ ]+[0-9a-f]+:[ ]+81d3c273[ ]+mop\.r\.1[ ]+tp,t2 +[ ]+[0-9a-f]+:[ ]+81e643f3[ ]+mop\.r\.2[ ]+t2,a2 +[ ]+[0-9a-f]+:[ ]+81f8c573[ ]+mop\.r\.3[ ]+a0,a7 +[ ]+[0-9a-f]+:[ ]+85cb46f3[ ]+mop\.r\.4[ ]+a3,s6 +[ ]+[0-9a-f]+:[ ]+85ddc873[ ]+mop\.r\.5[ ]+a6,s11 +[ ]+[0-9a-f]+:[ ]+85e049f3[ ]+mop\.r\.6[ ]+s3,zero +[ ]+[0-9a-f]+:[ ]+85f2cb73[ ]+mop\.r\.7[ ]+s6,t0 +[ ]+[0-9a-f]+:[ ]+89c54cf3[ ]+mop\.r\.8[ ]+s9,a0 +[ ]+[0-9a-f]+:[ ]+89d7ce73[ ]+mop\.r\.9[ ]+t3,a5 +[ ]+[0-9a-f]+:[ ]+89ea4ff3[ ]+mop\.r\.10[ ]+t6,s4 +[ ]+[0-9a-f]+:[ ]+89fcc173[ ]+mop\.r\.11[ ]+sp,s9 +[ ]+[0-9a-f]+:[ ]+8dcf42f3[ ]+mop\.r\.12[ ]+t0,t5 +[ ]+[0-9a-f]+:[ ]+8dd1c473[ ]+mop\.r\.13[ ]+s0,gp +[ ]+[0-9a-f]+:[ ]+8de445f3[ ]+mop\.r\.14[ ]+a1,s0 +[ ]+[0-9a-f]+:[ ]+8df6c773[ ]+mop\.r\.15[ ]+a4,a3 +[ ]+[0-9a-f]+:[ ]+c1c948f3[ ]+mop\.r\.16[ ]+a7,s2 +[ ]+[0-9a-f]+:[ ]+c1dbca73[ ]+mop\.r\.17[ ]+s4,s7 +[ ]+[0-9a-f]+:[ ]+c1ee4bf3[ ]+mop\.r\.18[ ]+s7,t3 +[ ]+[0-9a-f]+:[ ]+c1f0cd73[ ]+mop\.r\.19[ ]+s10,ra +[ ]+[0-9a-f]+:[ ]+c5c34ef3[ ]+mop\.r\.20[ ]+t4,t1 +[ ]+[0-9a-f]+:[ ]+c5d5c073[ ]+mop\.r\.21[ ]+zero,a1 +[ ]+[0-9a-f]+:[ ]+c5e841f3[ ]+mop\.r\.22[ ]+gp,a6 +[ ]+[0-9a-f]+:[ ]+c5fac373[ ]+mop\.r\.23[ ]+t1,s5 +[ ]+[0-9a-f]+:[ ]+c9cd44f3[ ]+mop\.r\.24[ ]+s1,s10 +[ ]+[0-9a-f]+:[ ]+c9dfc673[ ]+mop\.r\.25[ ]+a2,t6 +[ ]+[0-9a-f]+:[ ]+c9e247f3[ ]+mop\.r\.26[ ]+a5,tp +[ ]+[0-9a-f]+:[ ]+c9f4c973[ ]+mop\.r\.27[ ]+s2,s1 +[ ]+[0-9a-f]+:[ ]+cdc74af3[ ]+mop\.r\.28[ ]+s5,a4 +[ ]+[0-9a-f]+:[ ]+cdd9cc73[ ]+mop\.r\.29[ ]+s8,s3 +[ ]+[0-9a-f]+:[ ]+cdec4df3[ ]+mop\.r\.30[ ]+s11,s8 +[ ]+[0-9a-f]+:[ ]+cdfecf73[ ]+mop\.r\.31[ ]+t5,t4 +[ ]+[0-9a-f]+:[ ]+8324c473[ ]+mop\.rr\.0[ ]+s0,s1,s2 +[ ]+[0-9a-f]+:[ ]+873944f3[ ]+mop\.rr\.1[ ]+s1,s2,s3 +[ ]+[0-9a-f]+:[ ]+8b49c973[ ]+mop\.rr\.2[ ]+s2,s3,s4 +[ ]+[0-9a-f]+:[ ]+8f5a49f3[ ]+mop\.rr\.3[ ]+s3,s4,s5 +[ ]+[0-9a-f]+:[ ]+c36aca73[ ]+mop\.rr\.4[ ]+s4,s5,s6 +[ ]+[0-9a-f]+:[ ]+c77b4af3[ ]+mop\.rr\.5[ ]+s5,s6,s7 +[ ]+[0-9a-f]+:[ ]+cb8bcb73[ ]+mop\.rr\.6[ ]+s6,s7,s8 +[ ]+[0-9a-f]+:[ ]+cf9c4bf3[ ]+mop\.rr\.7[ ]+s7,s8,s9 diff --git a/gas/testsuite/gas/riscv/zimop.s b/gas/testsuite/gas/riscv/zimop.s new file mode 100644 index 00000000000..d4fdf217c7f --- /dev/null +++ b/gas/testsuite/gas/riscv/zimop.s @@ -0,0 +1,41 @@ +target: + mop.r.0 x1, x2 + mop.r.1 x4, x7 + mop.r.2 x7, x12 + mop.r.3 x10, x17 + mop.r.4 x13, x22 + mop.r.5 x16, x27 + mop.r.6 x19, x0 + mop.r.7 x22, x5 + mop.r.8 x25, x10 + mop.r.9 x28, x15 + mop.r.10 x31, x20 + mop.r.11 x2, x25 + mop.r.12 x5, x30 + mop.r.13 x8, x3 + mop.r.14 x11, x8 + mop.r.15 x14, x13 + mop.r.16 x17, x18 + mop.r.17 x20, x23 + mop.r.18 x23, x28 + mop.r.19 x26, x1 + mop.r.20 x29, x6 + mop.r.21 x0, x11 + mop.r.22 x3, x16 + mop.r.23 x6, x21 + mop.r.24 x9, x26 + mop.r.25 x12, x31 + mop.r.26 x15, x4 + mop.r.27 x18, x9 + mop.r.28 x21, x14 + mop.r.29 x24, x19 + mop.r.30 x27, x24 + mop.r.31 x30, x29 + mop.rr.0 s0, s1, s2 + mop.rr.1 s1, s2, s3 + mop.rr.2 s2, s3, s4 + mop.rr.3 s3, s4, s5 + mop.rr.4 s4, s5, s6 + mop.rr.5 s5, s6, s7 + mop.rr.6 s6, s7, s8 + mop.rr.7 s7, s8, s9 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 375483500e2..db516f06aee 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2315,11 +2315,109 @@ #define MASK_C_NTL_S1 0xffff #define MATCH_C_NTL_ALL 0x9016 #define MASK_C_NTL_ALL 0xffff +/* Zimop "may be" operations. */ +#define MATCH_MOP_R_0 0x81c04073 +#define MASK_MOP_R_0 0xfff0707f +#define MATCH_MOP_R_1 0x81d04073 +#define MASK_MOP_R_1 0xfff0707f +#define MATCH_MOP_R_2 0x81e04073 +#define MASK_MOP_R_2 0xfff0707f +#define MATCH_MOP_R_3 0x81f04073 +#define MASK_MOP_R_3 0xfff0707f +#define MATCH_MOP_R_4 0x85c04073 +#define MASK_MOP_R_4 0xfff0707f +#define MATCH_MOP_R_5 0x85d04073 +#define MASK_MOP_R_5 0xfff0707f +#define MATCH_MOP_R_6 0x85e04073 +#define MASK_MOP_R_6 0xfff0707f +#define MATCH_MOP_R_7 0x85f04073 +#define MASK_MOP_R_7 0xfff0707f +#define MATCH_MOP_R_8 0x89c04073 +#define MASK_MOP_R_8 0xfff0707f +#define MATCH_MOP_R_9 0x89d04073 +#define MASK_MOP_R_9 0xfff0707f +#define MATCH_MOP_R_10 0x89e04073 +#define MASK_MOP_R_10 0xfff0707f +#define MATCH_MOP_R_11 0x89f04073 +#define MASK_MOP_R_11 0xfff0707f +#define MATCH_MOP_R_12 0x8dc04073 +#define MASK_MOP_R_12 0xfff0707f +#define MATCH_MOP_R_13 0x8dd04073 +#define MASK_MOP_R_13 0xfff0707f +#define MATCH_MOP_R_14 0x8de04073 +#define MASK_MOP_R_14 0xfff0707f +#define MATCH_MOP_R_15 0x8df04073 +#define MASK_MOP_R_15 0xfff0707f +#define MATCH_MOP_R_16 0xc1c04073 +#define MASK_MOP_R_16 0xfff0707f +#define MATCH_MOP_R_17 0xc1d04073 +#define MASK_MOP_R_17 0xfff0707f +#define MATCH_MOP_R_18 0xc1e04073 +#define MASK_MOP_R_18 0xfff0707f +#define MATCH_MOP_R_19 0xc1f04073 +#define MASK_MOP_R_19 0xfff0707f +#define MATCH_MOP_R_20 0xc5c04073 +#define MASK_MOP_R_20 0xfff0707f +#define MATCH_MOP_R_21 0xc5d04073 +#define MASK_MOP_R_21 0xfff0707f +#define MATCH_MOP_R_22 0xc5e04073 +#define MASK_MOP_R_22 0xfff0707f +#define MATCH_MOP_R_23 0xc5f04073 +#define MASK_MOP_R_23 0xfff0707f +#define MATCH_MOP_R_24 0xc9c04073 +#define MASK_MOP_R_24 0xfff0707f +#define MATCH_MOP_R_25 0xc9d04073 +#define MASK_MOP_R_25 0xfff0707f +#define MATCH_MOP_R_26 0xc9e04073 +#define MASK_MOP_R_26 0xfff0707f +#define MATCH_MOP_R_27 0xc9f04073 +#define MASK_MOP_R_27 0xfff0707f +#define MATCH_MOP_R_28 0xcdc04073 +#define MASK_MOP_R_28 0xfff0707f +#define MATCH_MOP_R_29 0xcdd04073 +#define MASK_MOP_R_29 0xfff0707f +#define MATCH_MOP_R_30 0xcde04073 +#define MASK_MOP_R_30 0xfff0707f +#define MATCH_MOP_R_31 0xcdf04073 +#define MASK_MOP_R_31 0xfff0707f +#define MATCH_MOP_RR_0 0x82004073 +#define MASK_MOP_RR_0 0xfe00707f +#define MATCH_MOP_RR_1 0x86004073 +#define MASK_MOP_RR_1 0xfe00707f +#define MATCH_MOP_RR_2 0x8a004073 +#define MASK_MOP_RR_2 0xfe00707f +#define MATCH_MOP_RR_3 0x8e004073 +#define MASK_MOP_RR_3 0xfe00707f +#define MATCH_MOP_RR_4 0xc2004073 +#define MASK_MOP_RR_4 0xfe00707f +#define MATCH_MOP_RR_5 0xc6004073 +#define MASK_MOP_RR_5 0xfe00707f +#define MATCH_MOP_RR_6 0xca004073 +#define MASK_MOP_RR_6 0xfe00707f +#define MATCH_MOP_RR_7 0xce004073 +#define MASK_MOP_RR_7 0xfe00707f /* Zawrs instructions. */ #define MATCH_WRS_NTO 0x00d00073 #define MASK_WRS_NTO 0xffffffff #define MATCH_WRS_STO 0x01d00073 #define MASK_WRS_STO 0xffffffff +/* Zcmop "may be" operations. */ +#define MATCH_C_MOP_0 0x6081 +#define MASK_C_MOP_0 0xffff +#define MATCH_C_MOP_1 0x6181 +#define MASK_C_MOP_1 0xffff +#define MATCH_C_MOP_2 0x6281 +#define MASK_C_MOP_2 0xffff +#define MATCH_C_MOP_3 0x6381 +#define MASK_C_MOP_3 0xffff +#define MATCH_C_MOP_4 0x6481 +#define MASK_C_MOP_4 0xffff +#define MATCH_C_MOP_5 0x6581 +#define MASK_C_MOP_5 0xffff +#define MATCH_C_MOP_6 0x6681 +#define MASK_C_MOP_6 0xffff +#define MATCH_C_MOP_7 0x6781 +#define MASK_C_MOP_7 0xffff /* Vendor-specific (T-Head) XTheadBa instructions. */ #define MATCH_TH_ADDSL 0x0000100b #define MASK_TH_ADDSL 0xf800707f @@ -3370,6 +3468,47 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) +/* Zimop "may be" operations. */ +DECLARE_INSN(mop_r_0, MATCH_MOP_R_0, MASK_MOP_R_0) +DECLARE_INSN(mop_r_1, MATCH_MOP_R_1, MASK_MOP_R_1) +DECLARE_INSN(mop_r_2, MATCH_MOP_R_2, MASK_MOP_R_2) +DECLARE_INSN(mop_r_3, MATCH_MOP_R_3, MASK_MOP_R_3) +DECLARE_INSN(mop_r_4, MATCH_MOP_R_4, MASK_MOP_R_4) +DECLARE_INSN(mop_r_5, MATCH_MOP_R_5, MASK_MOP_R_5) +DECLARE_INSN(mop_r_6, MATCH_MOP_R_6, MASK_MOP_R_6) +DECLARE_INSN(mop_r_7, MATCH_MOP_R_7, MASK_MOP_R_7) +DECLARE_INSN(mop_r_8, MATCH_MOP_R_8, MASK_MOP_R_8) +DECLARE_INSN(mop_r_9, MATCH_MOP_R_9, MASK_MOP_R_9) +DECLARE_INSN(mop_r_10, MATCH_MOP_R_10, MASK_MOP_R_10) +DECLARE_INSN(mop_r_11, MATCH_MOP_R_11, MASK_MOP_R_11) +DECLARE_INSN(mop_r_12, MATCH_MOP_R_12, MASK_MOP_R_12) +DECLARE_INSN(mop_r_13, MATCH_MOP_R_13, MASK_MOP_R_13) +DECLARE_INSN(mop_r_14, MATCH_MOP_R_14, MASK_MOP_R_14) +DECLARE_INSN(mop_r_15, MATCH_MOP_R_15, MASK_MOP_R_15) +DECLARE_INSN(mop_r_16, MATCH_MOP_R_16, MASK_MOP_R_16) +DECLARE_INSN(mop_r_17, MATCH_MOP_R_17, MASK_MOP_R_17) +DECLARE_INSN(mop_r_18, MATCH_MOP_R_18, MASK_MOP_R_18) +DECLARE_INSN(mop_r_19, MATCH_MOP_R_19, MASK_MOP_R_19) +DECLARE_INSN(mop_r_20, MATCH_MOP_R_20, MASK_MOP_R_20) +DECLARE_INSN(mop_r_21, MATCH_MOP_R_21, MASK_MOP_R_21) +DECLARE_INSN(mop_r_22, MATCH_MOP_R_22, MASK_MOP_R_22) +DECLARE_INSN(mop_r_23, MATCH_MOP_R_23, MASK_MOP_R_23) +DECLARE_INSN(mop_r_24, MATCH_MOP_R_24, MASK_MOP_R_24) +DECLARE_INSN(mop_r_25, MATCH_MOP_R_25, MASK_MOP_R_25) +DECLARE_INSN(mop_r_26, MATCH_MOP_R_26, MASK_MOP_R_26) +DECLARE_INSN(mop_r_27, MATCH_MOP_R_27, MASK_MOP_R_27) +DECLARE_INSN(mop_r_28, MATCH_MOP_R_28, MASK_MOP_R_28) +DECLARE_INSN(mop_r_29, MATCH_MOP_R_29, MASK_MOP_R_29) +DECLARE_INSN(mop_r_30, MATCH_MOP_R_30, MASK_MOP_R_30) +DECLARE_INSN(mop_r_31, MATCH_MOP_R_31, MASK_MOP_R_31) +DECLARE_INSN(mop_rr_0, MATCH_MOP_RR_0, MASK_MOP_RR_0) +DECLARE_INSN(mop_rr_1, MATCH_MOP_RR_1, MASK_MOP_RR_1) +DECLARE_INSN(mop_rr_2, MATCH_MOP_RR_2, MASK_MOP_RR_2) +DECLARE_INSN(mop_rr_3, MATCH_MOP_RR_3, MASK_MOP_RR_3) +DECLARE_INSN(mop_rr_4, MATCH_MOP_RR_4, MASK_MOP_RR_4) +DECLARE_INSN(mop_rr_5, MATCH_MOP_RR_5, MASK_MOP_RR_5) +DECLARE_INSN(mop_rr_6, MATCH_MOP_RR_6, MASK_MOP_RR_6) +DECLARE_INSN(mop_rr_7, MATCH_MOP_RR_7, MASK_MOP_RR_7) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) @@ -3434,6 +3573,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) +/* Zcmop "may be" operations. */ +DECLARE_INSN(c_mop_0, MATCH_C_MOP_0, MASK_C_MOP_0) +DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1) +DECLARE_INSN(c_mop_2, MATCH_C_MOP_2, MASK_C_MOP_2) +DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3) +DECLARE_INSN(c_mop_4, MATCH_C_MOP_4, MASK_C_MOP_4) +DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5) +DECLARE_INSN(c_mop_6, MATCH_C_MOP_6, MASK_C_MOP_6) +DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 93dd5169ebc..dbe1fe16674 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -395,6 +395,7 @@ enum riscv_insn_class INSN_CLASS_ZIHINTNTL, INSN_CLASS_ZIHINTNTL_AND_C, INSN_CLASS_ZIHINTPAUSE, + INSN_CLASS_ZIMOP, INSN_CLASS_ZMMUL, INSN_CLASS_ZAWRS, INSN_CLASS_F_INX, @@ -438,6 +439,7 @@ enum riscv_insn_class INSN_CLASS_ZCB_AND_ZBA, INSN_CLASS_ZCB_AND_ZBB, INSN_CLASS_ZCB_AND_ZMMUL, + INSN_CLASS_ZCMOP, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 8e0ae85eb06..c2017e9dbe3 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1979,6 +1979,58 @@ const struct riscv_opcode riscv_opcodes[] = {"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 }, {"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +/* Zimop "may be" operations. */ +{"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 }, +{"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 }, +{"mop.r.2", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_2, MASK_MOP_R_2, match_opcode, 0 }, +{"mop.r.3", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_3, MASK_MOP_R_3, match_opcode, 0 }, +{"mop.r.4", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_4, MASK_MOP_R_4, match_opcode, 0 }, +{"mop.r.5", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_5, MASK_MOP_R_5, match_opcode, 0 }, +{"mop.r.6", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_6, MASK_MOP_R_6, match_opcode, 0 }, +{"mop.r.7", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_7, MASK_MOP_R_7, match_opcode, 0 }, +{"mop.r.8", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_8, MASK_MOP_R_8, match_opcode, 0 }, +{"mop.r.9", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_9, MASK_MOP_R_9, match_opcode, 0 }, +{"mop.r.10", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_10, MASK_MOP_R_10, match_opcode, 0 }, +{"mop.r.11", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_11, MASK_MOP_R_11, match_opcode, 0 }, +{"mop.r.12", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_12, MASK_MOP_R_12, match_opcode, 0 }, +{"mop.r.13", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_13, MASK_MOP_R_13, match_opcode, 0 }, +{"mop.r.14", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_14, MASK_MOP_R_14, match_opcode, 0 }, +{"mop.r.15", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_15, MASK_MOP_R_15, match_opcode, 0 }, +{"mop.r.16", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_16, MASK_MOP_R_16, match_opcode, 0 }, +{"mop.r.17", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_17, MASK_MOP_R_17, match_opcode, 0 }, +{"mop.r.18", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_18, MASK_MOP_R_18, match_opcode, 0 }, +{"mop.r.19", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_19, MASK_MOP_R_19, match_opcode, 0 }, +{"mop.r.20", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_20, MASK_MOP_R_20, match_opcode, 0 }, +{"mop.r.21", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_21, MASK_MOP_R_21, match_opcode, 0 }, +{"mop.r.22", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_22, MASK_MOP_R_22, match_opcode, 0 }, +{"mop.r.23", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_23, MASK_MOP_R_23, match_opcode, 0 }, +{"mop.r.24", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_24, MASK_MOP_R_24, match_opcode, 0 }, +{"mop.r.25", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_25, MASK_MOP_R_25, match_opcode, 0 }, +{"mop.r.26", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_26, MASK_MOP_R_26, match_opcode, 0 }, +{"mop.r.27", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_27, MASK_MOP_R_27, match_opcode, 0 }, +{"mop.r.28", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_28, MASK_MOP_R_28, match_opcode, 0 }, +{"mop.r.29", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_29, MASK_MOP_R_29, match_opcode, 0 }, +{"mop.r.30", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_30, MASK_MOP_R_30, match_opcode, 0 }, +{"mop.r.31", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_31, MASK_MOP_R_31, match_opcode, 0 }, +{"mop.rr.0", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_0, MASK_MOP_RR_0, match_opcode, 0 }, +{"mop.rr.1", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_1, MASK_MOP_RR_1, match_opcode, 0 }, +{"mop.rr.2", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_2, MASK_MOP_RR_2, match_opcode, 0 }, +{"mop.rr.3", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_3, MASK_MOP_RR_3, match_opcode, 0 }, +{"mop.rr.4", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_4, MASK_MOP_RR_4, match_opcode, 0 }, +{"mop.rr.5", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_5, MASK_MOP_RR_5, match_opcode, 0 }, +{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 }, +{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 }, + +/* Zcmop "may be" operations. */ +{"c.mop.0", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_0, MASK_C_MOP_0, match_opcode, 0 }, +{"c.mop.1", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_1, MASK_C_MOP_1, match_opcode, 0 }, +{"c.mop.2", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_2, MASK_C_MOP_2, match_opcode, 0 }, +{"c.mop.3", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_3, MASK_C_MOP_3, match_opcode, 0 }, +{"c.mop.4", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_4, MASK_C_MOP_4, match_opcode, 0 }, +{"c.mop.5", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_5, MASK_C_MOP_5, match_opcode, 0 }, +{"c.mop.6", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_6, MASK_C_MOP_6, match_opcode, 0 }, +{"c.mop.7", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_7, MASK_C_MOP_7, match_opcode, 0 }, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },