diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index fe451ff7ef6..8da68f4844d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1148,6 +1148,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zhinx", "zhinxmin",	check_implicit_always},
   {"zhinxmin", "zfinx",	check_implicit_always},
   {"zfinx", "zicsr",	check_implicit_always},
+  {"zicfiss", "zicsr",	check_implicit_always},
+  {"zicfiss", "zimop",	check_implicit_always},
+  {"zicfiss", "zcmop",	check_implicit_always},
   {"zk", "zkn",		check_implicit_always},
   {"zk", "zkr",		check_implicit_always},
   {"zk", "zkt",		check_implicit_always},
@@ -1192,6 +1195,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
   {"svadu", "zicsr",		check_implicit_always},
+  /* Complex implications (that should be checked after others).  */
+  /* Tail of the list.  */
   {NULL, NULL, NULL}
 };
 
@@ -1252,6 +1257,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicfilp",		ISA_SPEC_CLASS_DRAFT,		0, 3,  0 },
+  {"zicfiss",		ISA_SPEC_CLASS_DRAFT,		0, 3,  0 },
   {"zicond",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
@@ -2392,6 +2399,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zicbop");
     case INSN_CLASS_ZICBOZ:
       return riscv_subset_supports (rps, "zicboz");
+    case INSN_CLASS_ZICFILP:
+      return riscv_subset_supports (rps, "zicfilp");
+    case INSN_CLASS_ZICFISS:
+      return riscv_subset_supports (rps, "zicfiss");
     case INSN_CLASS_ZICOND:
       return riscv_subset_supports (rps, "zicond");
     case INSN_CLASS_ZICSR:
@@ -2599,6 +2610,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicbop";
     case INSN_CLASS_ZICBOZ:
       return "zicboz";
+    case INSN_CLASS_ZICFILP:
+      return "zicfilp";
+    case INSN_CLASS_ZICFISS:
+      return "zicfiss";
     case INSN_CLASS_ZICOND:
       return "zicond";
     case INSN_CLASS_ZICSR:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5759d3a5fc4..12cd239e747 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -67,6 +67,7 @@ enum riscv_csr_class
   CSR_CLASS_I,
   CSR_CLASS_I_32,	/* rv32 only */
   CSR_CLASS_F,		/* f-ext only */
+  CSR_CLASS_ZICFISS,	/* Zicfiss only */
   CSR_CLASS_ZKR,	/* zkr only */
   CSR_CLASS_V,		/* rvv only */
   CSR_CLASS_DEBUG,	/* debug CSR */
@@ -1042,6 +1043,9 @@ riscv_csr_address (const char *csr_name,
     case CSR_CLASS_F:
       extension = "f";
       break;
+    case CSR_CLASS_ZICFISS:
+      extension = "zicfiss";
+      break;
     case CSR_CLASS_ZKR:
       extension = "zkr";
       break;
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index cabb7c71918..b3c66e4a4cc 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -403,6 +403,7 @@ Contents of the .* section:
   DW_CFA_offset_extended_sf: r4445 \(stimecmph\) at cfa\+1396
   DW_CFA_offset_extended_sf: r4685 \(vstimecmp\) at cfa\+2356
   DW_CFA_offset_extended_sf: r4701 \(vstimecmph\) at cfa\+2420
+  DW_CFA_offset_extended_sf: r4113 \(ssp\) at cfa\+68
   DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
   DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
   DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index 428d0770779..e1a2ac10dc3 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -405,6 +405,8 @@ _start:
 	.cfi_offset stimecmph, 1396
 	.cfi_offset vstimecmp, 2356
 	.cfi_offset vstimecmph, 2420
+	# Zicfiss extension
+	.cfi_offset ssp, 68
 	# dropped
 	.cfi_offset ubadaddr, 268	# aliases
 	.cfi_offset sbadaddr, 1292	# aliases
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index dbdc077adac..03623f251f1 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -895,3 +895,5 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+c2159073[ 	]+csrw[ 	]+vtype,a1
 [ 	]+[0-9a-f]+:[ 	]+c2202573[ 	]+csrr[ 	]+a0,vlenb
 [ 	]+[0-9a-f]+:[ 	]+c2259073[ 	]+csrw[ 	]+vlenb,a1
+[ 	]+[0-9a-f]+:[ 	]+01102573[ 	]+csrr[ 	]+a0,ssp
+[ 	]+[0-9a-f]+:[ 	]+01159073[ 	]+csrw[ 	]+ssp,a1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 054179a416d..9e029e83ec4 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -1613,3 +1613,7 @@
 .*Info: macro .*
 .*Warning: read-only CSR is written `csrw vlenb,a1'
 .*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index 7ba88b6d1d5..34b4e7b3e06 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -895,3 +895,5 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+c2159073[ 	]+csrw[ 	]+vtype,a1
 [ 	]+[0-9a-f]+:[ 	]+c2202573[ 	]+csrr[ 	]+a0,vlenb
 [ 	]+[0-9a-f]+:[ 	]+c2259073[ 	]+csrw[ 	]+vlenb,a1
+[ 	]+[0-9a-f]+:[ 	]+01102573[ 	]+csrr[ 	]+a0,ssp
+[ 	]+[0-9a-f]+:[ 	]+01159073[ 	]+csrw[ 	]+ssp,a1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index cc365f1df41..6d485ec0e62 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -1609,3 +1609,7 @@
 .*Info: macro .*
 .*Warning: read-only CSR is written `csrw vlenb,a1'
 .*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index 677820b9526..5ba74da5bee 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -895,3 +895,5 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+c2159073[ 	]+csrw[ 	]+vtype,a1
 [ 	]+[0-9a-f]+:[ 	]+c2202573[ 	]+csrr[ 	]+a0,vlenb
 [ 	]+[0-9a-f]+:[ 	]+c2259073[ 	]+csrw[ 	]+vlenb,a1
+[ 	]+[0-9a-f]+:[ 	]+01102573[ 	]+csrr[ 	]+a0,ssp
+[ 	]+[0-9a-f]+:[ 	]+01159073[ 	]+csrw[ 	]+ssp,a1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 7a7f5f717c5..4672ae0e29e 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -1373,3 +1373,7 @@
 .*Info: macro .*
 .*Warning: read-only CSR is written `csrw vlenb,a1'
 .*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index f4d2b04ca6a..53250a0a756 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -895,3 +895,5 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+c2159073[ 	]+csrw[ 	]+vtype,a1
 [ 	]+[0-9a-f]+:[ 	]+c2202573[ 	]+csrr[ 	]+a0,vlenb
 [ 	]+[0-9a-f]+:[ 	]+c2259073[ 	]+csrw[ 	]+vlenb,a1
+[ 	]+[0-9a-f]+:[ 	]+01102573[ 	]+csrr[ 	]+a0,ssp
+[ 	]+[0-9a-f]+:[ 	]+01159073[ 	]+csrw[ 	]+ssp,a1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
index 7fcd73ab7dd..476f14281fe 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
@@ -1681,3 +1681,7 @@
 .*Info: macro .*
 .*Warning: read-only CSR is written `csrw vlenb,a1'
 .*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index 3d8da5488a0..ee02ccc08f6 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -510,3 +510,6 @@
 	csr vl
 	csr vtype
 	csr vlenb
+
+	# Control flow integrity (the Zicfiss extension)
+	csr ssp
diff --git a/gas/testsuite/gas/riscv/zicfilp.d b/gas/testsuite/gas/riscv/zicfilp.d
new file mode 100644
index 00000000000..572f1545b7d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfilp.d
@@ -0,0 +1,13 @@
+#as: -march=rv32ic_zicfilp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+12345017[ 	]+lpad[ 	]+0x12345
+[ 	]+[0-9a-f]+:[ 	]+12345017[ 	]+lpad[ 	]+0x12345
+[ 	]+[0-9a-f]+:[ 	]+0001[ 	]+nop
+[ 	]+[0-9a-f]+:[ 	]+f0123017[ 	]+lpad[ 	]+0xf0123
+[ 	]+[0-9a-f]+:[ 	]+f0123017[ 	]+lpad[ 	]+0xf0123
diff --git a/gas/testsuite/gas/riscv/zicfilp.s b/gas/testsuite/gas/riscv/zicfilp.s
new file mode 100644
index 00000000000..aac9b2b6656
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfilp.s
@@ -0,0 +1,14 @@
+target:
+	# lpad LPL == auipc x0, LPL
+	lpad	0x12345
+	auipc	zero, 0x12345
+
+	# Break alignment:
+	#
+	# Unaligned lpad causes illegal-instruction exception
+	# but must be disassembled (since alignment checking is a part of
+	# the lpad instruction operations).
+	c.nop
+
+	lpad	0xf0123
+	auipc	zero, 0xf0123
diff --git a/gas/testsuite/gas/riscv/zicfiss-32.d b/gas/testsuite/gas/riscv/zicfiss-32.d
new file mode 100644
index 00000000000..faa58189ee1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-32.d
@@ -0,0 +1,10 @@
+#as: -march=rv32ic_zicfiss
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+81c040f3[ 	]+sslw[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+81c042f3[ 	]+sslw[ 	]+t0
diff --git a/gas/testsuite/gas/riscv/zicfiss-32.s b/gas/testsuite/gas/riscv/zicfiss-32.s
new file mode 100644
index 00000000000..43546a1bf27
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-32.s
@@ -0,0 +1,3 @@
+target:
+	sslw	ra
+	sslw	t0
diff --git a/gas/testsuite/gas/riscv/zicfiss-64.d b/gas/testsuite/gas/riscv/zicfiss-64.d
new file mode 100644
index 00000000000..9bf58bc5726
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-64.d
@@ -0,0 +1,10 @@
+#as: -march=rv64ic_zicfiss
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+81c040f3[ 	]+ssld[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+81c042f3[ 	]+ssld[ 	]+t0
diff --git a/gas/testsuite/gas/riscv/zicfiss-64.s b/gas/testsuite/gas/riscv/zicfiss-64.s
new file mode 100644
index 00000000000..cb7c58026db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-64.s
@@ -0,0 +1,3 @@
+target:
+	ssld	ra
+	ssld	t0
diff --git a/gas/testsuite/gas/riscv/zicfiss-fail-64.d b/gas/testsuite/gas/riscv/zicfiss-fail-64.d
new file mode 100644
index 00000000000..7be1fd1a449
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-fail-64.d
@@ -0,0 +1,2 @@
+#as: -march=rv64i_zicfiss
+#error_output: zicfiss-fail-64.l
diff --git a/gas/testsuite/gas/riscv/zicfiss-fail-64.l b/gas/testsuite/gas/riscv/zicfiss-fail-64.l
new file mode 100644
index 00000000000..fb1a927fe9d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-fail-64.l
@@ -0,0 +1,6 @@
+.*: Assembler messages:
+.*: Error: illegal operands `ssld x0'
+.*: Error: illegal operands `ssld x2'
+.*: Error: illegal operands `ssld x31'
+.*: Error: unrecognized opcode `sslw x1'
+.*: Error: unrecognized opcode `sslw x5'
diff --git a/gas/testsuite/gas/riscv/zicfiss-fail-64.s b/gas/testsuite/gas/riscv/zicfiss-fail-64.s
new file mode 100644
index 00000000000..1fd19ae3754
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-fail-64.s
@@ -0,0 +1,9 @@
+target:
+	# ssld: only x1 or x5 are allowed.
+	ssld	x0
+	ssld	x2
+	ssld	x31
+
+	# sslw: only available on RV32.
+	sslw	x1
+	sslw	x5
diff --git a/gas/testsuite/gas/riscv/zicfiss-fail.d b/gas/testsuite/gas/riscv/zicfiss-fail.d
new file mode 100644
index 00000000000..0b4f09c9bab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_zicfiss
+#error_output: zicfiss-fail.l
diff --git a/gas/testsuite/gas/riscv/zicfiss-fail.l b/gas/testsuite/gas/riscv/zicfiss-fail.l
new file mode 100644
index 00000000000..ce9b5a31bba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-fail.l
@@ -0,0 +1,21 @@
+.*: Assembler messages:
+.*: Error: illegal operands `sspush x0'
+.*: Error: illegal operands `sspush x2'
+.*: Error: illegal operands `sspush x31'
+.*: Error: illegal operands `sspopchk x0'
+.*: Error: illegal operands `sspopchk x2'
+.*: Error: illegal operands `sspopchk x31'
+.*: Error: illegal operands `sslw x0'
+.*: Error: illegal operands `sslw x2'
+.*: Error: illegal operands `sslw x31'
+.*: Error: unrecognized opcode `ssld x1'
+.*: Error: unrecognized opcode `ssld x5'
+.*: Error: illegal operands `c\.sspush x5'
+.*: Error: illegal operands `c\.sspopchk x1'
+.*: Error: illegal operands `c\.sspush x0'
+.*: Error: illegal operands `c\.sspush x2'
+.*: Error: illegal operands `c\.sspush x31'
+.*: Error: illegal operands `c\.sspopchk x0'
+.*: Error: illegal operands `c\.sspopchk x2'
+.*: Error: illegal operands `c\.sspopchk x31'
+.*: Error: illegal operands `ssrdp x0'
diff --git a/gas/testsuite/gas/riscv/zicfiss-fail.s b/gas/testsuite/gas/riscv/zicfiss-fail.s
new file mode 100644
index 00000000000..35bd4f979dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-fail.s
@@ -0,0 +1,29 @@
+# Tested with RV32
+target:
+	# sspush / sspopchk / sslw: only x1 or x5 are allowed.
+	sspush		x0
+	sspush		x2
+	sspush		x31
+	sspopchk	x0
+	sspopchk	x2
+	sspopchk	x31
+	sslw		x0
+	sslw		x2
+	sslw		x31
+
+	# ssld: only available on RV64.
+	ssld		x1
+	ssld		x5
+
+	# c.sspush x1 / c.sspopchk x5: all other GPRs are not allowed.
+	c.sspush	x5
+	c.sspopchk	x1
+	c.sspush	x0
+	c.sspush	x2
+	c.sspush	x31
+	c.sspopchk	x0
+	c.sspopchk	x2
+	c.sspopchk	x31
+
+	# ssrdp: rd must not be x0.
+	ssrdp		x0
diff --git a/gas/testsuite/gas/riscv/zicfiss-mop-32.d b/gas/testsuite/gas/riscv/zicfiss-mop-32.d
new file mode 100644
index 00000000000..fdd39ce8c64
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-mop-32.d
@@ -0,0 +1,19 @@
+#as: -march=rv32ic_zicfiss
+#source: zicfiss-mop.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+81c040f3[ 	]+sslw[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+81c042f3[ 	]+sslw[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+81c0c073[ 	]+sspopchk[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+81c2c073[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+81d04ff3[ 	]+ssrdp[ 	]+t6
+[ 	]+[0-9a-f]+:[ 	]+82104073[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+82504073[ 	]+sspush[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6181[ 	]+ssincp
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+sspopchk[ 	]+t0
diff --git a/gas/testsuite/gas/riscv/zicfiss-mop-64.d b/gas/testsuite/gas/riscv/zicfiss-mop-64.d
new file mode 100644
index 00000000000..797c0f1fb9b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-mop-64.d
@@ -0,0 +1,19 @@
+#as: -march=rv64ic_zicfiss
+#source: zicfiss-mop.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+81c040f3[ 	]+ssld[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+81c042f3[ 	]+ssld[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+81c0c073[ 	]+sspopchk[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+81c2c073[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+81d04ff3[ 	]+ssrdp[ 	]+t6
+[ 	]+[0-9a-f]+:[ 	]+82104073[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+82504073[ 	]+sspush[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6181[ 	]+ssincp
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+sspopchk[ 	]+t0
diff --git a/gas/testsuite/gas/riscv/zicfiss-mop.s b/gas/testsuite/gas/riscv/zicfiss-mop.s
new file mode 100644
index 00000000000..71589844a6e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-mop.s
@@ -0,0 +1,24 @@
+target:
+	# ssl[wd]  x1 == mop.r.0 x1, x0
+	# ssl[wd]  x5 == mop.r.0 x5, x0
+	# sspopchk x1 == mop.r.0 x0, x1
+	# sspopchk x5 == mop.r.0 x0, x5
+	mop.r.0		ra, zero
+	mop.r.0		t0, zero
+	mop.r.0		zero, ra
+	mop.r.0		zero, t0
+
+	# ssrdp    rd == mop.r.1 rd, x0 (rd != 0)
+	mop.r.1		x31, zero
+
+	# sspush   x1 == mop.rr.0 x0, x0, x1
+	# sspush   x5 == mop.rr.0 x0, x0, x5
+	mop.rr.0	zero, zero, ra
+	mop.rr.0	zero, zero, t0
+
+	# c.sspush   x1 == c.mop.0
+	# c.ssincp      == c.mop.1
+	# c.sspopchk x5 == c.mop.2
+	c.mop.0
+	c.mop.1
+	c.mop.2
diff --git a/gas/testsuite/gas/riscv/zicfiss-na.d b/gas/testsuite/gas/riscv/zicfiss-na.d
new file mode 100644
index 00000000000..258e995098e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss-na.d
@@ -0,0 +1,20 @@
+#as: -march=rv32i_zicfiss
+#source: zicfiss.s
+#objdump: -d -M no-aliases
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+c\.sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+c\.sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+c\.sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+c\.sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+c\.sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+82504073[ 	]+sspush[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+81c0c073[ 	]+sspopchk[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+c\.sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6181[ 	]+c\.ssincp
+[ 	]+[0-9a-f]+:[ 	]+81d042f3[ 	]+ssrdp[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+81d04573[ 	]+ssrdp[ 	]+a0
diff --git a/gas/testsuite/gas/riscv/zicfiss.d b/gas/testsuite/gas/riscv/zicfiss.d
new file mode 100644
index 00000000000..2f9d7ff915c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_zicfiss
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+82504073[ 	]+sspush[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+81c0c073[ 	]+sspopchk[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6181[ 	]+ssincp
+[ 	]+[0-9a-f]+:[ 	]+81d042f3[ 	]+ssrdp[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+81d04573[ 	]+ssrdp[ 	]+a0
diff --git a/gas/testsuite/gas/riscv/zicfiss.s b/gas/testsuite/gas/riscv/zicfiss.s
new file mode 100644
index 00000000000..75fe56d171a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfiss.s
@@ -0,0 +1,15 @@
+target:
+	# Auto-compressed variants
+	sspush		ra
+	c.sspush	ra
+	sspopchk	t0
+	c.sspopchk	t0
+
+	# All uncompressed forms (except XLEN-specific sslw/ssld)
+	sspush		ra
+	sspush		t0
+	sspopchk	ra
+	sspopchk	t0
+	ssincp
+	ssrdp		t0
+	ssrdp		a0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index db516f06aee..00fc75e0f64 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2396,6 +2396,28 @@
 #define MASK_MOP_RR_6 0xfe00707f
 #define MATCH_MOP_RR_7 0xce004073
 #define MASK_MOP_RR_7 0xfe00707f
+/* Zicfilp instructions.  */
+#define MATCH_LPAD 0x00000017
+#define MASK_LPAD 0x00000fff
+/* Zicfiss instructions.  */
+#define MATCH_SSPUSH 0x82004073
+#define MASK_SSPUSH 0xfe0fffff
+#define MATCH_SSPOPCHK 0x81c04073
+#define MASK_SSPOPCHK 0xfff07fff
+#define MATCH_SSLW 0x81c04073
+#define MASK_SSLW 0xfffff07f
+#define MATCH_SSLD 0x81c04073
+#define MASK_SSLD 0xfffff07f
+#define MATCH_SSINCP 0x81c04073
+#define MASK_SSINCP 0xffffffff
+#define MATCH_SSRDP 0x81d04073
+#define MASK_SSRDP 0xfffff07f
+#define MATCH_C_SSPUSH 0x6081
+#define MASK_C_SSPUSH 0xffff
+#define MATCH_C_SSPOPCHK 0x6281
+#define MASK_C_SSPOPCHK 0xffff
+#define MATCH_C_SSINCP 0x6181
+#define MASK_C_SSINCP 0xffff
 /* Zawrs instructions.  */
 #define MATCH_WRS_NTO 0x00d00073
 #define MASK_WRS_NTO 0xffffffff
@@ -3089,6 +3111,8 @@
 #define CSR_VL 0xc20
 #define CSR_VTYPE 0xc21
 #define CSR_VLENB 0xc22
+/* Zicfiss extension CSR addresses.  */
+#define CSR_SSP 0x11
 #endif /* RISCV_ENCODING_H */
 #ifdef DECLARE_INSN
 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
@@ -4118,6 +4142,8 @@ DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS
 DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12)
 DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12)
 DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12)
+/* Zicfiss extension CSRs.  */
+DECLARE_CSR(ssp, CSR_SSP, CSR_CLASS_ZICFISS, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Unprivileged Floating-Point CSRs.  */
 DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index dbe1fe16674..99975c212e4 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -444,6 +444,8 @@ enum riscv_insn_class
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
   INSN_CLASS_ZICBOZ,
+  INSN_CLASS_ZICFILP,
+  INSN_CLASS_ZICFISS,
   INSN_CLASS_H,
   INSN_CLASS_XTHEADBA,
   INSN_CLASS_XTHEADBB,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c2017e9dbe3..2e888b91f65 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -319,6 +319,30 @@ match_th_load_pair(const struct riscv_opcode *op,
   return rd1 != rd2 && rd1 != rs && rd2 != rs && match_opcode (op, insn);
 }
 
+static int
+match_rd_eq_1_or_5(const struct riscv_opcode *op,
+		insn_t insn)
+{
+  int rd = (insn & MASK_RD) >> OP_SH_RD;
+  return match_opcode (op, insn) && (rd == 1 || rd == 5);
+}
+
+static int
+match_rs1_eq_1_or_5(const struct riscv_opcode *op,
+		insn_t insn)
+{
+  int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
+  return match_opcode (op, insn) && (rs1 == 1 || rs1 == 5);
+}
+
+static int
+match_rs2_eq_1_or_5(const struct riscv_opcode *op,
+		insn_t insn)
+{
+  int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
+  return match_opcode (op, insn) && (rs2 == 1 || rs2 == 5);
+}
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -350,6 +374,23 @@ const struct riscv_opcode riscv_opcodes[] =
 {"c.ntl.s1",    0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, 0 },
 {"c.ntl.all",   0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, 0 },
 {"pause",       0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 },
+{"lpad",        0, INSN_CLASS_ZICFILP, "u", MATCH_LPAD, MASK_LPAD, match_opcode, 0 },
+
+/* Standard "May Be Ops" (and compressed aliases).  */
+{"sspush",     0, INSN_CLASS_ZICFISS, "d",  MATCH_C_SSPUSH, MASK_C_SSPUSH, match_opcode, INSN_ALIAS|INSN_DREF },
+{"sspush",     0, INSN_CLASS_ZICFISS, "t",  MATCH_SSPUSH, MASK_SSPUSH, match_rs2_eq_1_or_5, INSN_DREF },
+{"sspopchk",   0, INSN_CLASS_ZICFISS, "d",  MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_opcode, INSN_ALIAS|INSN_DREF },
+{"sspopchk",   0, INSN_CLASS_ZICFISS, "s",  MATCH_SSPOPCHK, MASK_SSPOPCHK, match_rs1_eq_1_or_5, INSN_DREF },
+{"sslw",      32, INSN_CLASS_ZICFISS, "d",  MATCH_SSLW, MASK_SSLW, match_rd_eq_1_or_5, INSN_DREF },
+{"ssld",      64, INSN_CLASS_ZICFISS, "d",  MATCH_SSLD, MASK_SSLD, match_rd_eq_1_or_5, INSN_DREF },
+{"ssincp",     0, INSN_CLASS_ZICFISS, "",   MATCH_C_SSINCP, MASK_C_SSINCP, match_opcode, INSN_ALIAS|INSN_DREF },
+{"ssincp",     0, INSN_CLASS_ZICFISS, "",   MATCH_SSINCP, MASK_SSINCP, match_opcode, 0 },
+{"ssrdp",      0, INSN_CLASS_ZICFISS, "d",  MATCH_SSRDP, MASK_SSRDP, match_rd_nonzero, 0 },
+
+/* Standard compressed "May Be Ops".  */
+{"c.sspush",   0, INSN_CLASS_ZICFISS, "d",  MATCH_C_SSPUSH, MASK_C_SSPUSH, match_opcode, INSN_DREF },
+{"c.sspopchk", 0, INSN_CLASS_ZICFISS, "d",  MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_opcode, INSN_DREF },
+{"c.ssincp",   0, INSN_CLASS_ZICFISS, "",   MATCH_C_SSINCP, MASK_C_SSINCP, match_opcode, INSN_DREF },
 
 /* Basic RVI instructions and aliases.  */
 {"unimp",       0, INSN_CLASS_C, "",          0, 0xffffU, match_opcode, INSN_ALIAS },