From e4d4e27cab9c06aeb9c519b51a1058dee023cb4e Mon Sep 17 00:00:00 2001
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Wed, 26 Jul 2023 00:29:47 +0000
Subject: [PATCH 1/5] RISC-V: Base for complex extension implications

Thanks to the commit 48558a5e5471 ("RISC-V: Allow nested implications for
extensions"), we can write complex extension implications in theory.
However, to actually do that, we need to pass more information to
check_func.

For example, we want to imply 'Zcf' from 'F' if and only if the 'Zce'
extension is also enabled and XLEN is 32.  Passing rps is a way to
enable this.

This commit prepares for such complex extension implications.

bfd/ChangeLog:

	* elfxx-riscv.c (struct riscv_implicit_subset): Move around and
	change check_func function prototype.
	(check_implicit_always): New arguments.
	(check_implicit_for_i): Likewise.
	(riscv_implicit_subsets): Add comment for this variable.
	(riscv_parse_add_implicit_subsets): Call check_func with
	new arguments.
---
 bfd/elfxx-riscv.c | 39 ++++++++++++++++++++++++---------------
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c070394a366..95836b3296f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1064,11 +1064,25 @@ riscv_elf_ignore_reloc (bfd *abfd ATTRIBUTE_UNUSED,
   return bfd_reloc_ok;
 }
 
+/* Record all implicit information for the subsets.  */
+
+typedef struct riscv_implicit_subset
+{
+  const char *subset_name;
+  const char *implicit_name;
+  /* A function to determine if we need to add the implicit subset.  */
+  bool (*check_func) (riscv_parse_subset_t *,
+		      const struct riscv_implicit_subset *,
+		      const riscv_subset_t *);
+} riscv_implicit_subset_t;
+
 /* Always add the IMPLICIT for the SUBSET.  */
 
 static bool
-check_implicit_always (const char *implicit ATTRIBUTE_UNUSED,
-		       riscv_subset_t *subset ATTRIBUTE_UNUSED)
+check_implicit_always (riscv_parse_subset_t *rps ATTRIBUTE_UNUSED,
+		       const riscv_implicit_subset_t *implicit
+			   ATTRIBUTE_UNUSED,
+		       const riscv_subset_t *subset ATTRIBUTE_UNUSED)
 {
   return true;
 }
@@ -1076,23 +1090,18 @@ check_implicit_always (const char *implicit ATTRIBUTE_UNUSED,
 /* Add the IMPLICIT only when the version of SUBSET less than 2.1.  */
 
 static bool
-check_implicit_for_i (const char *implicit ATTRIBUTE_UNUSED,
-		      riscv_subset_t *subset)
+check_implicit_for_i (riscv_parse_subset_t *rps ATTRIBUTE_UNUSED,
+		      const riscv_implicit_subset_t *implicit ATTRIBUTE_UNUSED,
+		      const riscv_subset_t *subset)
 {
   return (subset->major_version < 2
 	  || (subset->major_version == 2
 	      && subset->minor_version < 1));
 }
 
-/* Record all implicit information for the subsets.  */
-struct riscv_implicit_subset
-{
-  const char *subset_name;
-  const char *implicit_name;
-  /* A function to determine if we need to add the implicit subset.  */
-  bool (*check_func) (const char *, riscv_subset_t *);
-};
-static struct riscv_implicit_subset riscv_implicit_subsets[] =
+/* All extension implications.  */
+
+static riscv_implicit_subset_t riscv_implicit_subsets[] =
 {
   {"e", "i",		check_implicit_always},
   {"i", "zicsr",	check_implicit_for_i},
@@ -1909,7 +1918,7 @@ riscv_parse_extensions (riscv_parse_subset_t *rps,
 static void
 riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
 {
-  struct riscv_implicit_subset *t = riscv_implicit_subsets;
+  riscv_implicit_subset_t *t = riscv_implicit_subsets;
   bool finished = false;
   while (!finished)
     {
@@ -1921,7 +1930,7 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
 	  if (riscv_lookup_subset (rps->subset_list, t->subset_name, &subset)
 	      && !riscv_lookup_subset (rps->subset_list, t->implicit_name,
 				       &implicit_subset)
-	      && t->check_func (t->implicit_name, subset))
+	      && t->check_func (rps, t, subset))
 	    {
 	      riscv_parse_add_subset (rps, t->implicit_name,
 				      RISCV_UNKNOWN_VERSION,

From f3c2a5c54f8ac6a26a752bc4346de1c4d9d45ed4 Mon Sep 17 00:00:00 2001
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Mon, 30 Jan 2023 09:36:52 +0000
Subject: [PATCH 2/5] RISC-V: Add 'Zicntr' and 'Zihpm' support with
 compatibility measures

This commit adds support for 'Zicntr' and 'Zihpm' extensions (version 2.0).

However, because GNU Binutils handled those as a part of 'I' and there was
a time when a ratified specification did split counters from the 'I'
extension without separate extension names.

To preserve maximum compatibility, this commit implements as follows:

*   For RISC-V ISA version 20191213 or less (all current non-draft ones),
    imply counter extensions from 'I' and DO NOT imply the 'Zicsr' extension
    from counter extensions.  We also suppress outputting the existence of
    counter extensions unless the version number is explicitly specified.
*   For future ratified ISAs, leave two options (each require minor edits):
    *   Continue previous behaviors or
    *   DO NOT imply counter extensions from 'I'.  DO imply the 'Zicsr'
        extension from counter extensions.  DO NOT suppress outputting the
        existence of such counter extensions by having a known
        version number (version 2.0 or [though unlikely] later).
        Make small changes to the disassembler to keep compatibility when
        disassembling old files.

bfd/ChangeLog:

	* elfxx-riscv.c (check_implicit_compat_counter_from_i): New function
	for counter compatibility from 'I' to counter extensions.
	(check_implicit_compat_counter_to_zicsr): New function for counter
	compatibility from counter extensions to the 'Zicsr' extension.
	(riscv_implicit_subsets): Add implications related to counter
	extensions with compatibility measures.
	(riscv_supported_std_z_ext): Add 'Zicntr' and 'Zihpm' extensions.
	But make version "unknown" to suppress outputting implicit
	dependencies on older ISAs.
	(riscv_parse_add_subset): Add "zicntr" and "zihpm" to exceptions
	to recognize on older ISAs if there's no version number.
	(riscv_multi_subset_supports): Add support for 'Zicntr'.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for
	'Zicntr' and 'Zihpm' extensions.
	(riscv_csr_address): Add handling for new CSR classes.
	* testsuite/gas/riscv/march-imply-i.s: Add 'Zicntr' instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Change CSR classes for counter CSRs.
	* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZICNTR
	for 'Zicntr' pseudoinstructions.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Recategorize counter
	pseudoinstructions to the 'Zicntr' extension.
---
 bfd/elfxx-riscv.c                       |  49 +++-
 gas/config/tc-riscv.c                   |  16 ++
 gas/testsuite/gas/riscv/march-imply-i.s |   8 +
 include/opcode/riscv-opc.h              | 310 ++++++++++++------------
 include/opcode/riscv.h                  |   1 +
 opcodes/riscv-opc.c                     |  12 +-
 6 files changed, 233 insertions(+), 163 deletions(-)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 95836b3296f..019d0cd1d06 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1099,6 +1099,32 @@ check_implicit_for_i (riscv_parse_subset_t *rps ATTRIBUTE_UNUSED,
 	      && subset->minor_version < 1));
 }
 
+/* Compatibility measure for counters (Zicntr and Zihpm):
+   Do or do not add the IMPLICIT only when the ISA version is
+   less than the border.  */
+
+static bool
+check_implicit_compat_counter_from_i (riscv_parse_subset_t *rps,
+				      const riscv_implicit_subset_t *implicit
+					  ATTRIBUTE_UNUSED,
+				      const riscv_subset_t *subset
+					  ATTRIBUTE_UNUSED)
+{
+  /* When rps->isa_spec is NULL, we don't need to care about implicit
+     extensions because the caller is the linker.  */
+  return rps->isa_spec && *rps->isa_spec <= ISA_SPEC_CLASS_20191213;
+}
+
+static bool
+check_implicit_compat_counter_to_zicsr (riscv_parse_subset_t *rps,
+					const riscv_implicit_subset_t
+					    *implicit,
+					const riscv_subset_t *subset)
+{
+  return (rps->isa_spec
+	  && !check_implicit_compat_counter_from_i (rps, implicit, subset));
+}
+
 /* All extension implications.  */
 
 static riscv_implicit_subset_t riscv_implicit_subsets[] =
@@ -1106,6 +1132,8 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] =
   {"e", "i",		check_implicit_always},
   {"i", "zicsr",	check_implicit_for_i},
   {"i", "zifencei",	check_implicit_for_i},
+  {"i", "zicntr",	check_implicit_compat_counter_from_i},
+  {"i", "zihpm",	check_implicit_compat_counter_from_i},
   {"g", "i",		check_implicit_always},
   {"g", "m",		check_implicit_always},
   {"g", "a",		check_implicit_always},
@@ -1191,6 +1219,8 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] =
   {"zcf", "zca",	check_implicit_always},
   {"zcd", "zca",	check_implicit_always},
   {"zcb", "zca",	check_implicit_always},
+  {"zicntr", "zicsr",	check_implicit_compat_counter_to_zicsr},
+  {"zihpm", "zicsr",	check_implicit_compat_counter_to_zicsr},
   {"smaia", "ssaia",		check_implicit_always},
   {"smcntrpmf", "zicsr",	check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
@@ -1260,6 +1290,10 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicntr",		ISA_SPEC_CLASS_2P2,		RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION,  0 }, /* Compat.  */
+  {"zicntr",		ISA_SPEC_CLASS_20190608,	RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION,  0 }, /* Compat.  */
+  {"zicntr",		ISA_SPEC_CLASS_20191213,	RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION,  0 }, /* Compat.  */
+  {"zicntr",		ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zicond",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
@@ -1267,6 +1301,10 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zifencei",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zihintntl",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
+  {"zihpm",		ISA_SPEC_CLASS_2P2,		RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION,  0 }, /* Compat.  */
+  {"zihpm",		ISA_SPEC_CLASS_20190608,	RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION,  0 }, /* Compat.  */
+  {"zihpm",		ISA_SPEC_CLASS_20191213,	RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION,  0 }, /* Compat.  */
+  {"zihpm",		ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfa",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },
@@ -1686,9 +1724,12 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
 	rps->error_handler
 	  (_("x ISA extension `%s' must be set with the versions"),
 	   subset);
-      /* Allow old ISA spec can recognize zicsr and zifencei.  */
+      /* Allow old ISA spec (version 2.2) can recognize extensions
+	 effectively split from the base 'I' extension version 2.0.  */
       else if (strcmp (subset, "zicsr") != 0
-	       && strcmp (subset, "zifencei") != 0)
+	       && strcmp (subset, "zifencei") != 0
+	       && strcmp (subset, "zicntr") != 0
+	       && strcmp (subset, "zihpm") != 0)
 	rps->error_handler
 	  (_("cannot find default versions of the ISA extension `%s'"),
 	   subset);
@@ -2398,6 +2439,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zicbop");
     case INSN_CLASS_ZICBOZ:
       return riscv_subset_supports (rps, "zicboz");
+    case INSN_CLASS_ZICNTR:
+      return riscv_subset_supports (rps, "zicntr");
     case INSN_CLASS_ZICOND:
       return riscv_subset_supports (rps, "zicond");
     case INSN_CLASS_ZICSR:
@@ -2601,6 +2644,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicbop";
     case INSN_CLASS_ZICBOZ:
       return "zicboz";
+    case INSN_CLASS_ZICNTR:
+      return "zicntr";
     case INSN_CLASS_ZICOND:
       return "zicond";
     case INSN_CLASS_ZICSR:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5759d3a5fc4..60d0faf8f88 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -66,6 +66,10 @@ enum riscv_csr_class
 
   CSR_CLASS_I,
   CSR_CLASS_I_32,	/* rv32 only */
+  CSR_CLASS_ZICNTR,	/* basic hardware perf counter */
+  CSR_CLASS_ZICNTR_32,	/* basic hardware perf counter, rv32 only */
+  CSR_CLASS_ZIHPM,	/* additional hardware perf counter */
+  CSR_CLASS_ZIHPM_32,	/* additional hardware perf counter, rv32 only */
   CSR_CLASS_F,		/* f-ext only */
   CSR_CLASS_ZKR,	/* zkr only */
   CSR_CLASS_V,		/* rvv only */
@@ -1033,6 +1037,18 @@ riscv_csr_address (const char *csr_name,
       need_check_version = true;
       extension = "i";
       break;
+    case CSR_CLASS_ZICNTR_32:
+      is_rv32_only = true;
+      /* Fall through.  */
+    case CSR_CLASS_ZICNTR:
+      extension = "zicntr";
+      break;
+    case CSR_CLASS_ZIHPM_32:
+      is_rv32_only = true;
+      /* Fall through.  */
+    case CSR_CLASS_ZIHPM:
+      extension = "zihpm";
+      break;
     case CSR_CLASS_H_32:
       is_rv32_only = true;
       /* Fall through.  */
diff --git a/gas/testsuite/gas/riscv/march-imply-i.s b/gas/testsuite/gas/riscv/march-imply-i.s
index b65c3c32aa6..a225aaf72ae 100644
--- a/gas/testsuite/gas/riscv/march-imply-i.s
+++ b/gas/testsuite/gas/riscv/march-imply-i.s
@@ -22,3 +22,11 @@ target:
 
 	# zifencei
 	fence.i
+
+	# zicntr
+	rdcycle		t0
+	rdtime		t0
+	rdinstret	t0
+	rdcycleh	t0
+	rdtimeh		t0
+	rdinstreth	t0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 375483500e2..b50a30587b5 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -3558,70 +3558,70 @@ DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN)
 #endif /* DECLARE_INSN */
 #ifdef DECLARE_CSR
 /* Unprivileged Counter/Timers CSRs.  */
-DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(time, CSR_TIME, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Privileged Supervisor CSRs.  */
 DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
@@ -3739,98 +3739,98 @@ DECLARE_CSR(pmpaddr60, CSR_PMPADDR60, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SP
 DECLARE_CSR(pmpaddr61, CSR_PMPADDR61, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(pmpaddr62, CSR_PMPADDR62, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(pmpaddr63, CSR_PMPADDR63, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Privileged Hypervisor CSRs.  */
 DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 93dd5169ebc..847a5a04f5a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -389,6 +389,7 @@ enum riscv_insn_class
   INSN_CLASS_Q,
   INSN_CLASS_F_AND_C,
   INSN_CLASS_D_AND_C,
+  INSN_CLASS_ZICNTR,
   INSN_CLASS_ZICOND,
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 8e0ae85eb06..5da55ab9e32 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -510,12 +510,12 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fence",       0, INSN_CLASS_I, "P,Q",       MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
 {"fence.i",     0, INSN_CLASS_ZIFENCEI, "",   MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
 {"fence.tso",   0, INSN_CLASS_I, "",          MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 },
-{"rdcycle",     0, INSN_CLASS_I, "d",         MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
-{"rdinstret",   0, INSN_CLASS_I, "d",         MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
-{"rdtime",      0, INSN_CLASS_I, "d",         MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
-{"rdcycleh",   32, INSN_CLASS_I, "d",         MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS },
-{"rdinstreth", 32, INSN_CLASS_I, "d",         MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS },
-{"rdtimeh",    32, INSN_CLASS_I, "d",         MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS },
+{"rdcycle",     0, INSN_CLASS_ZICNTR, "d",    MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
+{"rdinstret",   0, INSN_CLASS_ZICNTR, "d",    MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
+{"rdtime",      0, INSN_CLASS_ZICNTR, "d",    MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
+{"rdcycleh",   32, INSN_CLASS_ZICNTR, "d",    MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS },
+{"rdinstreth", 32, INSN_CLASS_ZICNTR, "d",    MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS },
+{"rdtimeh",    32, INSN_CLASS_ZICNTR, "d",    MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS },
 {"ecall",       0, INSN_CLASS_I, "",          MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
 {"scall",       0, INSN_CLASS_I, "",          MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
 {"xori",        0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, 0 },

From 62bf546f124bcccac0fa7b43e93608b68287a8a3 Mon Sep 17 00:00:00 2001
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Mon, 6 Feb 2023 06:39:10 +0000
Subject: [PATCH 3/5] RISC-V: Add complex CSR error handling

This commit adds template for complex CSR error handling (such like
multiple extensions involved).

gas/ChangeLog:

	* config/tc-riscv.c (riscv_csr_address): Add complex CSR error
	handling.
---
 gas/config/tc-riscv.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 60d0faf8f88..724d58ddd6e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1026,6 +1026,8 @@ riscv_csr_address (const char *csr_name,
   bool need_check_version = false;
   bool is_rv32_only = false;
   bool is_h_required = false;
+  bool is_csr_req_complex = false;
+  bool csr_ok = false;
   const char* extension = NULL;
 
   switch (csr_class)
@@ -1131,8 +1133,10 @@ riscv_csr_address (const char *csr_name,
       if (is_h_required && !riscv_subset_supports (&riscv_rps_as, "h"))
 	as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name);
 
-      if (extension != NULL
-	  && !riscv_subset_supports (&riscv_rps_as, extension))
+      if (is_csr_req_complex
+	      ? !csr_ok
+	      : (extension != NULL
+		 && !riscv_subset_supports (&riscv_rps_as, extension)))
 	as_warn (_("invalid CSR `%s', needs `%s' extension"),
 		 csr_name, extension);
     }

From f91776e1aa3bbe82d072b684367db76a865960ed Mon Sep 17 00:00:00 2001
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Sun, 5 Feb 2023 12:14:50 +0000
Subject: [PATCH 4/5] UNRATIFIED RISC-V: Add indirect CSR Access Extensions and
 its CSRs

[DO NOT MERGE]
Until the Indirect CSR Access Architecture Extension is frozen/ratified and
final version number is determined, this patch should not be merged
upstream.  This commit uses placeholder version 0.1 because there's no
version number in the current documentation.

This commit adds indirect CSR access extensions (Smcsrind / Sscsrind) and
their CSRs based on the latest documentation (as of 2023-08-07):
<https://docs.google.com/document/d/1ZxTSUWX_9_VafWeA0l1ci9RFjmivLuZn-US9IbFOEWY>

Because six CSRs are duplicates of 'Smaia' / 'Ssaia' extensions, it adds
complex CSR handling for those.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implications
	'Smcsrind' / 'Sscsrind' -> 'Zicsr'.
	(riscv_supported_std_s_ext): Add 'Smcsrind' and 'Sscsrind'
	extensions to the valid 'S' extension list.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for
	the 'S[ms]csrind' extensions. (riscv_csr_address): Add handling for
	new CSR classes.
	* testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr.s: Add new CSRs.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h: Recategory miselect, mireg, siselect, sireg,
	vsiselect and vsireg CSRs. (CSR_MIREG2, CSR_MIREG3, CSR_MIREG4,
	CSR_MIREG5, CSR_MIREG6, CSR_SIREG2, CSR_SIREG3, CSR_SIREG4,
	CSR_SIREG5, CSR_SIREG6, CSR_VSIREG2, CSR_VSIREG3, CSR_VSIREG3,
	CSR_VSIREG5, CSR_VSIREG6): Add new.
---
 bfd/elfxx-riscv.c                           |   4 +
 gas/config/tc-riscv.c                       |  30 ++++++
 gas/testsuite/gas/riscv/csr-dw-regnums.d    |  15 +++
 gas/testsuite/gas/riscv/csr-dw-regnums.s    |  17 ++++
 gas/testsuite/gas/riscv/csr-version-1p10.d  |  30 ++++++
 gas/testsuite/gas/riscv/csr-version-1p10.l  | 104 +++++++++++++++++---
 gas/testsuite/gas/riscv/csr-version-1p11.d  |  30 ++++++
 gas/testsuite/gas/riscv/csr-version-1p11.l  | 104 +++++++++++++++++---
 gas/testsuite/gas/riscv/csr-version-1p12.d  |  30 ++++++
 gas/testsuite/gas/riscv/csr-version-1p12.l  | 104 +++++++++++++++++---
 gas/testsuite/gas/riscv/csr-version-1p9p1.d |  30 ++++++
 gas/testsuite/gas/riscv/csr-version-1p9p1.l | 104 +++++++++++++++++---
 gas/testsuite/gas/riscv/csr.s               |  19 ++++
 include/opcode/riscv-opc.h                  |  46 +++++++--
 14 files changed, 613 insertions(+), 54 deletions(-)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 019d0cd1d06..806f54d703c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1223,10 +1223,12 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] =
   {"zihpm", "zicsr",	check_implicit_compat_counter_to_zicsr},
   {"smaia", "ssaia",		check_implicit_always},
   {"smcntrpmf", "zicsr",	check_implicit_always},
+  {"smcsrind", "zicsr",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
   {"ssaia", "zicsr",		check_implicit_always},
   {"sscofpmf", "zicsr",		check_implicit_always},
+  {"sscsrind", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
   {"svadu", "zicsr",		check_implicit_always},
@@ -1378,10 +1380,12 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
   {"smaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smcntrpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smcsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smepmp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"sscsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svadu",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 724d58ddd6e..9a0cef09374 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -78,14 +78,20 @@ enum riscv_csr_class
   CSR_CLASS_H_32,	/* hypervisor, rv32 only */
   CSR_CLASS_SMAIA,		/* Smaia */
   CSR_CLASS_SMAIA_32,		/* Smaia, rv32 only */
+  CSR_CLASS_SMAIA_OR_SMCSRIND,	/* Smaia or Smcsrind */
   CSR_CLASS_SMCNTRPMF,		/* Smcntrpmf */
   CSR_CLASS_SMCNTRPMF_32,	/* Smcntrpmf, rv32 only */
+  CSR_CLASS_SMCSRIND,		/* Smcsrind */
   CSR_CLASS_SMSTATEEN,		/* Smstateen only */
   CSR_CLASS_SMSTATEEN_32,	/* Smstateen RV32 only */
   CSR_CLASS_SSAIA,		/* Ssaia */
   CSR_CLASS_SSAIA_AND_H,	/* Ssaia with H */
   CSR_CLASS_SSAIA_32,		/* Ssaia, rv32 only */
   CSR_CLASS_SSAIA_AND_H_32,	/* Ssaia with H, rv32 only */
+  CSR_CLASS_SSAIA_OR_SSCSRIND,		/* Ssaia or Sscsrind */
+  CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H,	/* Ssaia or Sscsrind (with H) */
+  CSR_CLASS_SSCSRIND,		/* Sscsrind */
+  CSR_CLASS_SSCSRIND_AND_H,	/* Sscsrind (with H) */
   CSR_CLASS_SSSTATEEN,		/* S[ms]stateen only */
   CSR_CLASS_SSSTATEEN_AND_H,	/* S[ms]stateen only (with H) */
   CSR_CLASS_SSSTATEEN_AND_H_32,	/* S[ms]stateen RV32 only (with H) */
@@ -1072,6 +1078,12 @@ riscv_csr_address (const char *csr_name,
     case CSR_CLASS_SMAIA:
       extension = "smaia";
       break;
+    case CSR_CLASS_SMAIA_OR_SMCSRIND:
+      is_csr_req_complex = true;
+      extension = _ ("smaia' or `smcsrind");
+      csr_ok = (riscv_subset_supports (&riscv_rps_as, "smaia")
+		|| riscv_subset_supports (&riscv_rps_as, "smcsrind"));
+      break;
     case CSR_CLASS_SMCNTRPMF_32:
       is_rv32_only = true;
       /* Fall through.  */
@@ -1079,6 +1091,9 @@ riscv_csr_address (const char *csr_name,
       need_check_version = true;
       extension = "smcntrpmf";
       break;
+    case CSR_CLASS_SMCSRIND:
+      extension = "smcsrind";
+      break;
     case CSR_CLASS_SMSTATEEN_32:
       is_rv32_only = true;
       /* Fall through.  */
@@ -1110,6 +1125,21 @@ riscv_csr_address (const char *csr_name,
     case CSR_CLASS_SSCOFPMF:
       extension = "sscofpmf";
       break;
+    case CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H:
+      is_h_required = true;
+      /* Fall through.  */
+    case CSR_CLASS_SSAIA_OR_SSCSRIND:
+      is_csr_req_complex = true;
+      extension = _ ("ssaia' or `sscsrind");
+      csr_ok = (riscv_subset_supports (&riscv_rps_as, "ssaia")
+		|| riscv_subset_supports (&riscv_rps_as, "sscsrind"));
+      break;
+    case CSR_CLASS_SSCSRIND_AND_H:
+      is_h_required = true;
+      /* Fall through.  */
+    case CSR_CLASS_SSCSRIND:
+      extension = "sscsrind";
+      break;
     case CSR_CLASS_SSTC:
     case CSR_CLASS_SSTC_AND_H:
     case CSR_CLASS_SSTC_32:
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index cabb7c71918..c75ea7d7d2d 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -328,6 +328,11 @@ Contents of the .* section:
   DW_CFA_offset_extended_sf: r4898 \(minstretcfg\) at cfa\+3208
   DW_CFA_offset_extended_sf: r5921 \(mcyclecfgh\) at cfa\+7300
   DW_CFA_offset_extended_sf: r5922 \(minstretcfgh\) at cfa\+7304
+  DW_CFA_offset_extended_sf: r4946 \(mireg2\) at cfa\+3400
+  DW_CFA_offset_extended_sf: r4947 \(mireg3\) at cfa\+3404
+  DW_CFA_offset_extended_sf: r4949 \(mireg4\) at cfa\+3412
+  DW_CFA_offset_extended_sf: r4950 \(mireg5\) at cfa\+3416
+  DW_CFA_offset_extended_sf: r4951 \(mireg6\) at cfa\+3420
   DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120
   DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124
   DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128
@@ -399,6 +404,16 @@ Contents of the .* section:
   DW_CFA_offset_extended_sf: r5949 \(mhpmevent29h\) at cfa\+7412
   DW_CFA_offset_extended_sf: r5950 \(mhpmevent30h\) at cfa\+7416
   DW_CFA_offset_extended_sf: r5951 \(mhpmevent31h\) at cfa\+7420
+  DW_CFA_offset_extended_sf: r4434 \(sireg2\) at cfa\+1352
+  DW_CFA_offset_extended_sf: r4435 \(sireg3\) at cfa\+1356
+  DW_CFA_offset_extended_sf: r4437 \(sireg4\) at cfa\+1364
+  DW_CFA_offset_extended_sf: r4438 \(sireg5\) at cfa\+1368
+  DW_CFA_offset_extended_sf: r4439 \(sireg6\) at cfa\+1372
+  DW_CFA_offset_extended_sf: r4690 \(vsireg2\) at cfa\+2376
+  DW_CFA_offset_extended_sf: r4691 \(vsireg3\) at cfa\+2380
+  DW_CFA_offset_extended_sf: r4693 \(vsireg4\) at cfa\+2388
+  DW_CFA_offset_extended_sf: r4694 \(vsireg5\) at cfa\+2392
+  DW_CFA_offset_extended_sf: r4695 \(vsireg6\) at cfa\+2396
   DW_CFA_offset_extended_sf: r4429 \(stimecmp\) at cfa\+1332
   DW_CFA_offset_extended_sf: r4445 \(stimecmph\) at cfa\+1396
   DW_CFA_offset_extended_sf: r4685 \(vstimecmp\) at cfa\+2356
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index 428d0770779..dfe73b94ca3 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -326,6 +326,12 @@ _start:
 	.cfi_offset minstretcfg, 3208
 	.cfi_offset mcyclecfgh, 7300
 	.cfi_offset minstretcfgh, 7304
+	# Smcsrind extension (except miselect/mireg in Smaia)
+	.cfi_offset mireg2, 3400
+	.cfi_offset mireg3, 3404
+	.cfi_offset mireg4, 3412
+	.cfi_offset mireg5, 3416
+	.cfi_offset mireg6, 3420
 	# Smstateen extension
 	.cfi_offset mstateen0, 3120
 	.cfi_offset mstateen1, 3124
@@ -400,6 +406,17 @@ _start:
 	.cfi_offset mhpmevent29h, 7412
 	.cfi_offset mhpmevent30h, 7416
 	.cfi_offset mhpmevent31h, 7420
+	# Sscsrind extension (except {v,}si{select,reg} in Ssaia)
+	.cfi_offset sireg2, 1352
+	.cfi_offset sireg3, 1356
+	.cfi_offset sireg4, 1364
+	.cfi_offset sireg5, 1368
+	.cfi_offset sireg6, 1372
+	.cfi_offset vsireg2, 2376
+	.cfi_offset vsireg3, 2380
+	.cfi_offset vsireg4, 2388
+	.cfi_offset vsireg5, 2392
+	.cfi_offset vsireg6, 2396
 	# Sstc extension
 	.cfi_offset stimecmp, 1332
 	.cfi_offset stimecmph, 1396
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index dbdc077adac..6a889dea952 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -631,6 +631,16 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+72159073[ 	]+csrw[ 	]+mcyclecfgh,a1
 [ 	]+[0-9a-f]+:[ 	]+72202573[ 	]+csrr[ 	]+a0,minstretcfgh
 [ 	]+[0-9a-f]+:[ 	]+72259073[ 	]+csrw[ 	]+minstretcfgh,a1
+[ 	]+[0-9a-f]+:[ 	]+35202573[ 	]+csrr[ 	]+a0,mireg2
+[ 	]+[0-9a-f]+:[ 	]+35259073[ 	]+csrw[ 	]+mireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+35302573[ 	]+csrr[ 	]+a0,mireg3
+[ 	]+[0-9a-f]+:[ 	]+35359073[ 	]+csrw[ 	]+mireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+35502573[ 	]+csrr[ 	]+a0,mireg4
+[ 	]+[0-9a-f]+:[ 	]+35559073[ 	]+csrw[ 	]+mireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+35602573[ 	]+csrr[ 	]+a0,mireg5
+[ 	]+[0-9a-f]+:[ 	]+35659073[ 	]+csrw[ 	]+mireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+35702573[ 	]+csrr[ 	]+a0,mireg6
+[ 	]+[0-9a-f]+:[ 	]+35759073[ 	]+csrw[ 	]+mireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
@@ -773,6 +783,26 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+73e59073[ 	]+csrw[ 	]+mhpmevent30h,a1
 [ 	]+[0-9a-f]+:[ 	]+73f02573[ 	]+csrr[ 	]+a0,mhpmevent31h
 [ 	]+[0-9a-f]+:[ 	]+73f59073[ 	]+csrw[ 	]+mhpmevent31h,a1
+[ 	]+[0-9a-f]+:[ 	]+15202573[ 	]+csrr[ 	]+a0,sireg2
+[ 	]+[0-9a-f]+:[ 	]+15259073[ 	]+csrw[ 	]+sireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+15302573[ 	]+csrr[ 	]+a0,sireg3
+[ 	]+[0-9a-f]+:[ 	]+15359073[ 	]+csrw[ 	]+sireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+15502573[ 	]+csrr[ 	]+a0,sireg4
+[ 	]+[0-9a-f]+:[ 	]+15559073[ 	]+csrw[ 	]+sireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+15602573[ 	]+csrr[ 	]+a0,sireg5
+[ 	]+[0-9a-f]+:[ 	]+15659073[ 	]+csrw[ 	]+sireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+15702573[ 	]+csrr[ 	]+a0,sireg6
+[ 	]+[0-9a-f]+:[ 	]+15759073[ 	]+csrw[ 	]+sireg6,a1
+[ 	]+[0-9a-f]+:[ 	]+25202573[ 	]+csrr[ 	]+a0,vsireg2
+[ 	]+[0-9a-f]+:[ 	]+25259073[ 	]+csrw[ 	]+vsireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+25302573[ 	]+csrr[ 	]+a0,vsireg3
+[ 	]+[0-9a-f]+:[ 	]+25359073[ 	]+csrw[ 	]+vsireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+25502573[ 	]+csrr[ 	]+a0,vsireg4
+[ 	]+[0-9a-f]+:[ 	]+25559073[ 	]+csrw[ 	]+vsireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+25602573[ 	]+csrr[ 	]+a0,vsireg5
+[ 	]+[0-9a-f]+:[ 	]+25659073[ 	]+csrw[ 	]+vsireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+25702573[ 	]+csrr[ 	]+a0,vsireg6
+[ 	]+[0-9a-f]+:[ 	]+25759073[ 	]+csrw[ 	]+vsireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+14d02573[ 	]+csrr[ 	]+a0,stimecmp
 [ 	]+[0-9a-f]+:[ 	]+14d59073[ 	]+csrw[ 	]+stimecmp,a1
 [ 	]+[0-9a-f]+:[ 	]+15d02573[ 	]+csrr[ 	]+a0,stimecmph
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 054179a416d..c9769e94213 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -823,13 +823,13 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsatp', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Warning: invalid CSR `mireg', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Warning: invalid CSR `mireg', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mtopei', needs `smaia' extension
 .*Info: macro .*
@@ -913,6 +913,26 @@
 .*Info: macro .*
 .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `mireg2', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg2', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg3', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg3', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg4', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg4', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg5', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg5', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg6', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg6', needs `smcsrind' extension
+.*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
@@ -1057,13 +1077,13 @@
 .*Info: macro .*
 .*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
 .*Info: macro .*
-.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Warning: invalid CSR `siselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Warning: invalid CSR `siselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Warning: invalid CSR `sireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Warning: invalid CSR `sireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `stopei', needs `ssaia' extension
 .*Info: macro .*
@@ -1125,19 +1145,19 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiselect', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Warning: invalid CSR `vsiselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsiselect', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Warning: invalid CSR `vsiselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsireg', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Warning: invalid CSR `vsireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsireg', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Warning: invalid CSR `vsireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vstopei', needs `h' extension
 .*Info: macro .*
@@ -1479,6 +1499,66 @@
 .*Info: macro .*
 .*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `sireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension
+.*Info: macro .*
 .*Warning: invalid CSR `stimecmp', needs `sstc' extension
 .*Info: macro .*
 .*Warning: invalid CSR `stimecmp', needs `sstc' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index 7ba88b6d1d5..56e22bc1bf7 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -631,6 +631,16 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+72159073[ 	]+csrw[ 	]+mcyclecfgh,a1
 [ 	]+[0-9a-f]+:[ 	]+72202573[ 	]+csrr[ 	]+a0,minstretcfgh
 [ 	]+[0-9a-f]+:[ 	]+72259073[ 	]+csrw[ 	]+minstretcfgh,a1
+[ 	]+[0-9a-f]+:[ 	]+35202573[ 	]+csrr[ 	]+a0,mireg2
+[ 	]+[0-9a-f]+:[ 	]+35259073[ 	]+csrw[ 	]+mireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+35302573[ 	]+csrr[ 	]+a0,mireg3
+[ 	]+[0-9a-f]+:[ 	]+35359073[ 	]+csrw[ 	]+mireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+35502573[ 	]+csrr[ 	]+a0,mireg4
+[ 	]+[0-9a-f]+:[ 	]+35559073[ 	]+csrw[ 	]+mireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+35602573[ 	]+csrr[ 	]+a0,mireg5
+[ 	]+[0-9a-f]+:[ 	]+35659073[ 	]+csrw[ 	]+mireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+35702573[ 	]+csrr[ 	]+a0,mireg6
+[ 	]+[0-9a-f]+:[ 	]+35759073[ 	]+csrw[ 	]+mireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
@@ -773,6 +783,26 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+73e59073[ 	]+csrw[ 	]+mhpmevent30h,a1
 [ 	]+[0-9a-f]+:[ 	]+73f02573[ 	]+csrr[ 	]+a0,mhpmevent31h
 [ 	]+[0-9a-f]+:[ 	]+73f59073[ 	]+csrw[ 	]+mhpmevent31h,a1
+[ 	]+[0-9a-f]+:[ 	]+15202573[ 	]+csrr[ 	]+a0,sireg2
+[ 	]+[0-9a-f]+:[ 	]+15259073[ 	]+csrw[ 	]+sireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+15302573[ 	]+csrr[ 	]+a0,sireg3
+[ 	]+[0-9a-f]+:[ 	]+15359073[ 	]+csrw[ 	]+sireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+15502573[ 	]+csrr[ 	]+a0,sireg4
+[ 	]+[0-9a-f]+:[ 	]+15559073[ 	]+csrw[ 	]+sireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+15602573[ 	]+csrr[ 	]+a0,sireg5
+[ 	]+[0-9a-f]+:[ 	]+15659073[ 	]+csrw[ 	]+sireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+15702573[ 	]+csrr[ 	]+a0,sireg6
+[ 	]+[0-9a-f]+:[ 	]+15759073[ 	]+csrw[ 	]+sireg6,a1
+[ 	]+[0-9a-f]+:[ 	]+25202573[ 	]+csrr[ 	]+a0,vsireg2
+[ 	]+[0-9a-f]+:[ 	]+25259073[ 	]+csrw[ 	]+vsireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+25302573[ 	]+csrr[ 	]+a0,vsireg3
+[ 	]+[0-9a-f]+:[ 	]+25359073[ 	]+csrw[ 	]+vsireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+25502573[ 	]+csrr[ 	]+a0,vsireg4
+[ 	]+[0-9a-f]+:[ 	]+25559073[ 	]+csrw[ 	]+vsireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+25602573[ 	]+csrr[ 	]+a0,vsireg5
+[ 	]+[0-9a-f]+:[ 	]+25659073[ 	]+csrw[ 	]+vsireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+25702573[ 	]+csrr[ 	]+a0,vsireg6
+[ 	]+[0-9a-f]+:[ 	]+25759073[ 	]+csrw[ 	]+vsireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+14d02573[ 	]+csrr[ 	]+a0,stimecmp
 [ 	]+[0-9a-f]+:[ 	]+14d59073[ 	]+csrw[ 	]+stimecmp,a1
 [ 	]+[0-9a-f]+:[ 	]+15d02573[ 	]+csrr[ 	]+a0,stimecmph
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index cc365f1df41..cedee254cc5 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -819,13 +819,13 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsatp', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Warning: invalid CSR `mireg', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Warning: invalid CSR `mireg', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mtopei', needs `smaia' extension
 .*Info: macro .*
@@ -909,6 +909,26 @@
 .*Info: macro .*
 .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `mireg2', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg2', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg3', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg3', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg4', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg4', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg5', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg5', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg6', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg6', needs `smcsrind' extension
+.*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
@@ -1053,13 +1073,13 @@
 .*Info: macro .*
 .*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
 .*Info: macro .*
-.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Warning: invalid CSR `siselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Warning: invalid CSR `siselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Warning: invalid CSR `sireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Warning: invalid CSR `sireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `stopei', needs `ssaia' extension
 .*Info: macro .*
@@ -1121,19 +1141,19 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiselect', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Warning: invalid CSR `vsiselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsiselect', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Warning: invalid CSR `vsiselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsireg', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Warning: invalid CSR `vsireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsireg', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Warning: invalid CSR `vsireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vstopei', needs `h' extension
 .*Info: macro .*
@@ -1475,6 +1495,66 @@
 .*Info: macro .*
 .*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `sireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension
+.*Info: macro .*
 .*Warning: invalid CSR `stimecmp', needs `sstc' extension
 .*Info: macro .*
 .*Warning: invalid CSR `stimecmp', needs `sstc' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index 677820b9526..604de160fe0 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -631,6 +631,16 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+72159073[ 	]+csrw[ 	]+mcyclecfgh,a1
 [ 	]+[0-9a-f]+:[ 	]+72202573[ 	]+csrr[ 	]+a0,minstretcfgh
 [ 	]+[0-9a-f]+:[ 	]+72259073[ 	]+csrw[ 	]+minstretcfgh,a1
+[ 	]+[0-9a-f]+:[ 	]+35202573[ 	]+csrr[ 	]+a0,mireg2
+[ 	]+[0-9a-f]+:[ 	]+35259073[ 	]+csrw[ 	]+mireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+35302573[ 	]+csrr[ 	]+a0,mireg3
+[ 	]+[0-9a-f]+:[ 	]+35359073[ 	]+csrw[ 	]+mireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+35502573[ 	]+csrr[ 	]+a0,mireg4
+[ 	]+[0-9a-f]+:[ 	]+35559073[ 	]+csrw[ 	]+mireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+35602573[ 	]+csrr[ 	]+a0,mireg5
+[ 	]+[0-9a-f]+:[ 	]+35659073[ 	]+csrw[ 	]+mireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+35702573[ 	]+csrr[ 	]+a0,mireg6
+[ 	]+[0-9a-f]+:[ 	]+35759073[ 	]+csrw[ 	]+mireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
@@ -773,6 +783,26 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+73e59073[ 	]+csrw[ 	]+mhpmevent30h,a1
 [ 	]+[0-9a-f]+:[ 	]+73f02573[ 	]+csrr[ 	]+a0,mhpmevent31h
 [ 	]+[0-9a-f]+:[ 	]+73f59073[ 	]+csrw[ 	]+mhpmevent31h,a1
+[ 	]+[0-9a-f]+:[ 	]+15202573[ 	]+csrr[ 	]+a0,sireg2
+[ 	]+[0-9a-f]+:[ 	]+15259073[ 	]+csrw[ 	]+sireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+15302573[ 	]+csrr[ 	]+a0,sireg3
+[ 	]+[0-9a-f]+:[ 	]+15359073[ 	]+csrw[ 	]+sireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+15502573[ 	]+csrr[ 	]+a0,sireg4
+[ 	]+[0-9a-f]+:[ 	]+15559073[ 	]+csrw[ 	]+sireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+15602573[ 	]+csrr[ 	]+a0,sireg5
+[ 	]+[0-9a-f]+:[ 	]+15659073[ 	]+csrw[ 	]+sireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+15702573[ 	]+csrr[ 	]+a0,sireg6
+[ 	]+[0-9a-f]+:[ 	]+15759073[ 	]+csrw[ 	]+sireg6,a1
+[ 	]+[0-9a-f]+:[ 	]+25202573[ 	]+csrr[ 	]+a0,vsireg2
+[ 	]+[0-9a-f]+:[ 	]+25259073[ 	]+csrw[ 	]+vsireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+25302573[ 	]+csrr[ 	]+a0,vsireg3
+[ 	]+[0-9a-f]+:[ 	]+25359073[ 	]+csrw[ 	]+vsireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+25502573[ 	]+csrr[ 	]+a0,vsireg4
+[ 	]+[0-9a-f]+:[ 	]+25559073[ 	]+csrw[ 	]+vsireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+25602573[ 	]+csrr[ 	]+a0,vsireg5
+[ 	]+[0-9a-f]+:[ 	]+25659073[ 	]+csrw[ 	]+vsireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+25702573[ 	]+csrr[ 	]+a0,vsireg6
+[ 	]+[0-9a-f]+:[ 	]+25759073[ 	]+csrw[ 	]+vsireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+14d02573[ 	]+csrr[ 	]+a0,stimecmp
 [ 	]+[0-9a-f]+:[ 	]+14d59073[ 	]+csrw[ 	]+stimecmp,a1
 [ 	]+[0-9a-f]+:[ 	]+15d02573[ 	]+csrr[ 	]+a0,stimecmph
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 7a7f5f717c5..8b7bc60edc2 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -543,13 +543,13 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsatp', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Warning: invalid CSR `mireg', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Warning: invalid CSR `mireg', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mtopei', needs `smaia' extension
 .*Info: macro .*
@@ -633,6 +633,26 @@
 .*Info: macro .*
 .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `mireg2', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg2', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg3', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg3', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg4', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg4', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg5', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg5', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg6', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg6', needs `smcsrind' extension
+.*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
@@ -777,13 +797,13 @@
 .*Info: macro .*
 .*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
 .*Info: macro .*
-.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Warning: invalid CSR `siselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Warning: invalid CSR `siselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Warning: invalid CSR `sireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Warning: invalid CSR `sireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `stopei', needs `ssaia' extension
 .*Info: macro .*
@@ -845,19 +865,19 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiselect', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Warning: invalid CSR `vsiselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsiselect', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Warning: invalid CSR `vsiselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsireg', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Warning: invalid CSR `vsireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsireg', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Warning: invalid CSR `vsireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vstopei', needs `h' extension
 .*Info: macro .*
@@ -1199,6 +1219,66 @@
 .*Info: macro .*
 .*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `sireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension
+.*Info: macro .*
 .*Warning: invalid CSR `stimecmp', needs `sstc' extension
 .*Info: macro .*
 .*Warning: invalid CSR `stimecmp', needs `sstc' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index f4d2b04ca6a..93911e20339 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -631,6 +631,16 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+72159073[ 	]+csrw[ 	]+0x721,a1
 [ 	]+[0-9a-f]+:[ 	]+72202573[ 	]+csrr[ 	]+a0,0x722
 [ 	]+[0-9a-f]+:[ 	]+72259073[ 	]+csrw[ 	]+0x722,a1
+[ 	]+[0-9a-f]+:[ 	]+35202573[ 	]+csrr[ 	]+a0,mireg2
+[ 	]+[0-9a-f]+:[ 	]+35259073[ 	]+csrw[ 	]+mireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+35302573[ 	]+csrr[ 	]+a0,mireg3
+[ 	]+[0-9a-f]+:[ 	]+35359073[ 	]+csrw[ 	]+mireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+35502573[ 	]+csrr[ 	]+a0,mireg4
+[ 	]+[0-9a-f]+:[ 	]+35559073[ 	]+csrw[ 	]+mireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+35602573[ 	]+csrr[ 	]+a0,mireg5
+[ 	]+[0-9a-f]+:[ 	]+35659073[ 	]+csrw[ 	]+mireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+35702573[ 	]+csrr[ 	]+a0,mireg6
+[ 	]+[0-9a-f]+:[ 	]+35759073[ 	]+csrw[ 	]+mireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
@@ -773,6 +783,26 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+73e59073[ 	]+csrw[ 	]+mhpmevent30h,a1
 [ 	]+[0-9a-f]+:[ 	]+73f02573[ 	]+csrr[ 	]+a0,mhpmevent31h
 [ 	]+[0-9a-f]+:[ 	]+73f59073[ 	]+csrw[ 	]+mhpmevent31h,a1
+[ 	]+[0-9a-f]+:[ 	]+15202573[ 	]+csrr[ 	]+a0,sireg2
+[ 	]+[0-9a-f]+:[ 	]+15259073[ 	]+csrw[ 	]+sireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+15302573[ 	]+csrr[ 	]+a0,sireg3
+[ 	]+[0-9a-f]+:[ 	]+15359073[ 	]+csrw[ 	]+sireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+15502573[ 	]+csrr[ 	]+a0,sireg4
+[ 	]+[0-9a-f]+:[ 	]+15559073[ 	]+csrw[ 	]+sireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+15602573[ 	]+csrr[ 	]+a0,sireg5
+[ 	]+[0-9a-f]+:[ 	]+15659073[ 	]+csrw[ 	]+sireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+15702573[ 	]+csrr[ 	]+a0,sireg6
+[ 	]+[0-9a-f]+:[ 	]+15759073[ 	]+csrw[ 	]+sireg6,a1
+[ 	]+[0-9a-f]+:[ 	]+25202573[ 	]+csrr[ 	]+a0,vsireg2
+[ 	]+[0-9a-f]+:[ 	]+25259073[ 	]+csrw[ 	]+vsireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+25302573[ 	]+csrr[ 	]+a0,vsireg3
+[ 	]+[0-9a-f]+:[ 	]+25359073[ 	]+csrw[ 	]+vsireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+25502573[ 	]+csrr[ 	]+a0,vsireg4
+[ 	]+[0-9a-f]+:[ 	]+25559073[ 	]+csrw[ 	]+vsireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+25602573[ 	]+csrr[ 	]+a0,vsireg5
+[ 	]+[0-9a-f]+:[ 	]+25659073[ 	]+csrw[ 	]+vsireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+25702573[ 	]+csrr[ 	]+a0,vsireg6
+[ 	]+[0-9a-f]+:[ 	]+25759073[ 	]+csrw[ 	]+vsireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+14d02573[ 	]+csrr[ 	]+a0,stimecmp
 [ 	]+[0-9a-f]+:[ 	]+14d59073[ 	]+csrw[ 	]+stimecmp,a1
 [ 	]+[0-9a-f]+:[ 	]+15d02573[ 	]+csrr[ 	]+a0,stimecmph
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
index 7fcd73ab7dd..25fc8272e37 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
@@ -923,13 +923,13 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsatp', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Warning: invalid CSR `mireg', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Warning: invalid CSR `mireg', needs `smaia' or `smcsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mtopei', needs `smaia' extension
 .*Info: macro .*
@@ -1029,6 +1029,26 @@
 .*Info: macro .*
 .*Warning: invalid CSR `minstretcfgh' for the privileged spec `1.9.1'
 .*Info: macro .*
+.*Warning: invalid CSR `mireg2', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg2', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg3', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg3', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg4', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg4', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg5', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg5', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg6', needs `smcsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mireg6', needs `smcsrind' extension
+.*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
@@ -1173,13 +1193,13 @@
 .*Info: macro .*
 .*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
 .*Info: macro .*
-.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Warning: invalid CSR `siselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Warning: invalid CSR `siselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Warning: invalid CSR `sireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
-.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Warning: invalid CSR `sireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `stopei', needs `ssaia' extension
 .*Info: macro .*
@@ -1241,19 +1261,19 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiselect', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Warning: invalid CSR `vsiselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsiselect', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Warning: invalid CSR `vsiselect', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsireg', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Warning: invalid CSR `vsireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vsireg', needs `h' extension
 .*Info: macro .*
-.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Warning: invalid CSR `vsireg', needs `ssaia' or `sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `vstopei', needs `h' extension
 .*Info: macro .*
@@ -1595,6 +1615,66 @@
 .*Info: macro .*
 .*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `sireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `h' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension
+.*Info: macro .*
 .*Warning: invalid CSR `stimecmp', needs `sstc' extension
 .*Info: macro .*
 .*Warning: invalid CSR `stimecmp', needs `sstc' extension
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index 3d8da5488a0..e20d7224264 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -356,6 +356,13 @@
 	csr mcyclecfgh
 	csr minstretcfgh
 
+	# Smcsrind extension (except miselect/mireg in Smaia)
+	csr mireg2
+	csr mireg3
+	csr mireg4
+	csr mireg5
+	csr mireg6
+
 	# Smstateen/Ssstateen extensions
 	csr mstateen0
 	csr mstateen1
@@ -433,6 +440,18 @@
 	csr mhpmevent30h
 	csr mhpmevent31h
 
+	# Sscsrind extension (except {v,}si{select,reg} in Ssaia)
+	csr sireg2
+	csr sireg3
+	csr sireg4
+	csr sireg5
+	csr sireg6
+	csr vsireg2
+	csr vsireg3
+	csr vsireg4
+	csr vsireg5
+	csr vsireg6
+
 	# Sstc extension
 	csr stimecmp
 	csr stimecmph
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index b50a30587b5..2ebd0a7a078 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2883,6 +2883,12 @@
 #define CSR_MINSTRETCFG  0x322
 #define CSR_MCYCLECFGH   0x721
 #define CSR_MINSTRETCFGH 0x722
+/* Smcsrind extension.  */
+#define CSR_MIREG2 0x352
+#define CSR_MIREG3 0x353
+#define CSR_MIREG4 0x355
+#define CSR_MIREG5 0x356
+#define CSR_MIREG6 0x357
 /* Smstateen extension */
 #define CSR_MSTATEEN0 0x30c
 #define CSR_MSTATEEN1 0x30d
@@ -2957,6 +2963,17 @@
 #define CSR_MHPMEVENT29H 0x73d
 #define CSR_MHPMEVENT30H 0x73e
 #define CSR_MHPMEVENT31H 0x73f
+/* Sscsrind extension.  */
+#define CSR_SIREG2 0x152
+#define CSR_SIREG3 0x153
+#define CSR_SIREG4 0x155
+#define CSR_SIREG5 0x156
+#define CSR_SIREG6 0x157
+#define CSR_VSIREG2 0x252
+#define CSR_VSIREG3 0x253
+#define CSR_VSIREG4 0x255
+#define CSR_VSIREG5 0x256
+#define CSR_VSIREG6 0x257
 /* Sstc extension */
 #define CSR_STIMECMP 0x14d
 #define CSR_STIMECMPH 0x15d
@@ -3858,8 +3875,8 @@ DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLA
 DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Smaia extension */
-DECLARE_CSR(miselect, CSR_MISELECT, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
-DECLARE_CSR(mireg, CSR_MIREG, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(miselect, CSR_MISELECT, CSR_CLASS_SMAIA_OR_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mireg, CSR_MIREG, CSR_CLASS_SMAIA_OR_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mtopei, CSR_MTOPEI, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mtopi, CSR_MTOPI, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mvien, CSR_MVIEN, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
@@ -3874,6 +3891,12 @@ DECLARE_CSR(mcyclecfg, CSR_MCYCLECFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10,
 DECLARE_CSR(minstretcfg, CSR_MINSTRETCFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(mcyclecfgh, CSR_MCYCLECFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(minstretcfgh, CSR_MINSTRETCFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+/* Smcsrind extension.  */
+DECLARE_CSR(mireg2, CSR_MIREG2, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mireg3, CSR_MIREG3, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mireg4, CSR_MIREG4, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mireg5, CSR_MIREG5, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mireg6, CSR_MIREG6, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Smstateen/Ssstateen extensions.  */
 DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
@@ -3896,8 +3919,8 @@ DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_
 DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Ssaia extension */
-DECLARE_CSR(siselect, CSR_SISELECT, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
-DECLARE_CSR(sireg, CSR_SIREG, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(siselect, CSR_SISELECT, CSR_CLASS_SSAIA_OR_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(sireg, CSR_SIREG, CSR_CLASS_SSAIA_OR_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(stopei, CSR_STOPEI, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(stopi, CSR_STOPI, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(sieh, CSR_SIEH, CSR_CLASS_SSAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
@@ -3906,8 +3929,8 @@ DECLARE_CSR(hvien, CSR_HVIEN, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_
 DECLARE_CSR(hvictl, CSR_HVICTL, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(hviprio1, CSR_HVIPRIO1, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(hviprio2, CSR_HVIPRIO2, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
-DECLARE_CSR(vsiselect, CSR_VSISELECT, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
-DECLARE_CSR(vsireg, CSR_VSIREG, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vsiselect, CSR_VSISELECT, CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vsireg, CSR_VSIREG, CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vstopei, CSR_VSTOPEI, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vstopi, CSR_VSTOPI, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(hidelegh, CSR_HIDELEGH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
@@ -3948,6 +3971,17 @@ DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLA
 DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Sscsrind extension.  */
+DECLARE_CSR(sireg2, CSR_SIREG2, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(sireg3, CSR_SIREG3, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(sireg4, CSR_SIREG4, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(sireg5, CSR_SIREG5, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(sireg6, CSR_SIREG6, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vsireg2, CSR_VSIREG2, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vsireg3, CSR_VSIREG3, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vsireg4, CSR_VSIREG4, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vsireg5, CSR_VSIREG5, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vsireg6, CSR_VSIREG6, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Sstc extension */
 DECLARE_CSR(stimecmp, CSR_STIMECMP, CSR_CLASS_SSTC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(stimecmph, CSR_STIMECMPH, CSR_CLASS_SSTC_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)

From e7d54eb58dce4d0bbf6a7c56a5de2897adce70a7 Mon Sep 17 00:00:00 2001
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Mon, 7 Aug 2023 02:40:37 +0000
Subject: [PATCH 5/5] UNRATIFIED RISC-V: Add supervisor counter delegation
 extensions

[DO NOT MERGE]
Until the Supervisor Counter Delegation Architecture Extension is frozen /
ratified and final version number is determined, this patch should not be
merged upstream. This commit uses version 0.1 as a placeholder because
there's no version number in the current documentation.

This commit adds support for two extensions from the Supervisor Counter
Delegation Architecture Extension specification ('Smcdeleg' and 'Ssccfg')
based on the latest documentation (as of 2023-08-07):
<https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add related implications
	including the ones to 'Zicsr' for compatibility and excluding
	the ones to counter extensions that require *either* 'Zicntr' or
	'Zihpm'.
	(riscv_supported_std_s_ext): Add 'Smcdeleg' and 'Ssccfg' extensions
	to the supported 'S' extension list.
	(riscv_parse_check_conflicts): Check existence of either 'Zicntr' or
	'Zihpm' if either 'Smcdeleg' or 'Ssccfg' is enabled.
---
 bfd/elfxx-riscv.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 806f54d703c..9fa6e5ec2b7 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1222,11 +1222,15 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] =
   {"zicntr", "zicsr",	check_implicit_compat_counter_to_zicsr},
   {"zihpm", "zicsr",	check_implicit_compat_counter_to_zicsr},
   {"smaia", "ssaia",		check_implicit_always},
+  {"smcdeleg", "zicsr",		check_implicit_always}, /* Compat.  */
+  {"smcdeleg", "sscsrind",	check_implicit_always},
   {"smcntrpmf", "zicsr",	check_implicit_always},
   {"smcsrind", "zicsr",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
   {"ssaia", "zicsr",		check_implicit_always},
+  {"ssccfg", "zicsr",		check_implicit_always}, /* Compat.  */
+  {"ssccfg", "sscsrind",	check_implicit_always},
   {"sscofpmf", "zicsr",		check_implicit_always},
   {"sscsrind", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
@@ -1379,11 +1383,13 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
 static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
   {"smaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smcdeleg",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
   {"smcntrpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smcsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smepmp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"ssccfg",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sscsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -2029,6 +2035,24 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
       no_conflict = false;
     }
 
+  bool support_counters = (riscv_subset_supports (rps, "zicntr")
+			   || riscv_subset_supports (rps, "zihpm"));
+  if (!support_counters)
+    {
+      if (riscv_subset_supports(rps, "smcdeleg"))
+	{
+	  rps->error_handler
+	    (_("`smcdeleg' requires either `zicntr' or `zihpm' extension"));
+	  no_conflict = false;
+	}
+      if (riscv_subset_supports(rps, "ssccfg"))
+	{
+	  rps->error_handler
+	    (_("`ssccfg' requires either `zicntr' or `zihpm' extension"));
+	  no_conflict = false;
+	}
+    }
+
   bool support_zve = false;
   bool support_zvl = false;
   riscv_subset_t *s = rps->subset_list->head;