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[AArch64][SVE] Use FeatureUseFixedOverScalableIfEqualCost for A320 (llvm#152156)
With this new A320 in-order core, we follow adding the FeatureUseFixedOverScalableIfEqualCost feature to A510 and A520 (llvm#132246), which reaps the same code generation benefits of preferring fixed over scalable when the cost is equal. So when we have: ``` void foo(float* a, float* b, float* dst, unsigned n) { for (unsigned i = 0; i < n; ++i) dst[i] = a[i] + b[i]; } ``` When compiling without the feature enabled, we get: ``` ... ld1b { z0.b }, p0/z, [x0, x10] ld1b { z2.b }, p0/z, [x1, x10] add x12, x0, x10 ldr z1, [x12, #1, mul vl] add x12, x1, x10 ldr z3, [x12, #1, mul vl] fadd z0.s, z2.s, z0.s add x12, x2, x10 fadd z1.s, z3.s, z1.s dech x11 st1b { z0.b }, p0, [x2, x10] incb x10, all, mul #2 str z1, [x12, #1, mul vl] ... ``` When compiling with, we get: ``` ... ldp q0, q1, [x12, #-16] ldp q2, q3, [x11, #-16] subs x13, x13, llvm#8 fadd v0.4s, v2.4s, v0.4s fadd v1.4s, v3.4s, v1.4s add x11, x11, llvm#32 add x12, x12, llvm#32 stp q0, q1, [x10, #-16] add x10, x10, llvm#32 ... ```
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‎llvm/lib/Target/AArch64/AArch64Processors.td

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,8 @@ def TuneA320 : SubtargetFeature<"a320", "ARMProcFamily", "CortexA320",
2222
FeatureFuseAES,
2323
FeatureFuseAdrpAdd,
2424
FeaturePostRAScheduler,
25-
FeatureUseWzrToVecMove]>;
25+
FeatureUseWzrToVecMove,
26+
FeatureUseFixedOverScalableIfEqualCost]>;
2627

2728
def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
2829
"Cortex-A53 ARM processors", [
@@ -45,15 +46,17 @@ def TuneA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
4546
FeatureFuseAES,
4647
FeatureFuseAdrpAdd,
4748
FeaturePostRAScheduler,
48-
FeatureUseWzrToVecMove
49+
FeatureUseWzrToVecMove,
50+
FeatureUseFixedOverScalableIfEqualCost
4951
]>;
5052

5153
def TuneA520 : SubtargetFeature<"a520", "ARMProcFamily", "CortexA520",
5254
"Cortex-A520 ARM processors", [
5355
FeatureFuseAES,
5456
FeatureFuseAdrpAdd,
5557
FeaturePostRAScheduler,
56-
FeatureUseWzrToVecMove]>;
58+
FeatureUseWzrToVecMove,
59+
FeatureUseFixedOverScalableIfEqualCost]>;
5760

5861
def TuneA520AE : SubtargetFeature<"a520ae", "ARMProcFamily", "CortexA520",
5962
"Cortex-A520AE ARM processors", [
@@ -756,7 +759,6 @@ def ProcessorFeatures {
756759
FeatureSB, FeaturePAuth, FeatureSSBS, FeatureSVE, FeatureSVE2,
757760
FeatureComplxNum, FeatureCRC, FeatureDotProd,
758761
FeatureFPARMv8,FeatureFullFP16, FeatureJS, FeatureLSE,
759-
FeatureUseFixedOverScalableIfEqualCost,
760762
FeatureRAS, FeatureRCPC, FeatureRDM, FeatureFPAC];
761763
list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
762764
FeatureMTE, FeatureETE, FeatureSVEBitPerm,
@@ -766,7 +768,6 @@ def ProcessorFeatures {
766768
FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC,
767769
FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS,
768770
FeatureNEON, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM,
769-
FeatureUseFixedOverScalableIfEqualCost,
770771
FeatureDotProd, FeatureFPAC];
771772
list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
772773
FeatureMTE, FeatureETE, FeatureSVEBitPerm,

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-fixed-width-inorder-core.ll

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
22
; RUN: opt < %s -mtriple=aarch64-none-elf -mcpu=cortex-a510 -mattr=+sve -passes=loop-vectorize -S | FileCheck %s --check-prefix=CHECK-CA510
33
; RUN: opt < %s -mtriple=aarch64-none-elf -mcpu=cortex-a520 -mattr=+sve -passes=loop-vectorize -S | FileCheck %s --check-prefix=CHECK-CA520
4+
; RUN: opt < %s -mtriple=aarch64-none-elf -mcpu=cortex-a320 -mattr=+sve -passes=loop-vectorize -S | FileCheck %s --check-prefix=CHECK-CA320
45

56
define void @sve_add(ptr %dst, ptr %a, ptr %b, i64 %n) {
67
; CHECK-CA510-LABEL: define void @sve_add(
@@ -131,6 +132,70 @@ define void @sve_add(ptr %dst, ptr %a, ptr %b, i64 %n) {
131132
; CHECK-CA520: [[FOR_COND_CLEANUP]]:
132133
; CHECK-CA520-NEXT: ret void
133134
;
135+
; CHECK-CA320-LABEL: define void @sve_add(
136+
; CHECK-CA320-SAME: ptr [[DST:%.*]], ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
137+
; CHECK-CA320-NEXT: [[ENTRY:.*:]]
138+
; CHECK-CA320-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
139+
; CHECK-CA320-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
140+
; CHECK-CA320-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64
141+
; CHECK-CA320-NEXT: [[CMP9_NOT:%.*]] = icmp eq i64 [[N]], 0
142+
; CHECK-CA320-NEXT: br i1 [[CMP9_NOT]], label %[[FOR_COND_CLEANUP:.*]], label %[[FOR_BODY_PREHEADER:.*]]
143+
; CHECK-CA320: [[FOR_BODY_PREHEADER]]:
144+
; CHECK-CA320-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
145+
; CHECK-CA320-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
146+
; CHECK-CA320: [[VECTOR_MEMCHECK]]:
147+
; CHECK-CA320-NEXT: [[TMP0:%.*]] = sub i64 [[DST1]], [[A2]]
148+
; CHECK-CA320-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
149+
; CHECK-CA320-NEXT: [[TMP1:%.*]] = sub i64 [[DST1]], [[B3]]
150+
; CHECK-CA320-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
151+
; CHECK-CA320-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
152+
; CHECK-CA320-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
153+
; CHECK-CA320: [[VECTOR_PH]]:
154+
; CHECK-CA320-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8
155+
; CHECK-CA320-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
156+
; CHECK-CA320-NEXT: br label %[[VECTOR_BODY:.*]]
157+
; CHECK-CA320: [[VECTOR_BODY]]:
158+
; CHECK-CA320-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
159+
; CHECK-CA320-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX]]
160+
; CHECK-CA320-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP2]], i32 4
161+
; CHECK-CA320-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
162+
; CHECK-CA320-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP3]], align 4
163+
; CHECK-CA320-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw float, ptr [[B]], i64 [[INDEX]]
164+
; CHECK-CA320-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP4]], i32 4
165+
; CHECK-CA320-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP4]], align 4
166+
; CHECK-CA320-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x float>, ptr [[TMP5]], align 4
167+
; CHECK-CA320-NEXT: [[TMP6:%.*]] = fadd fast <4 x float> [[WIDE_LOAD6]], [[WIDE_LOAD]]
168+
; CHECK-CA320-NEXT: [[TMP7:%.*]] = fadd fast <4 x float> [[WIDE_LOAD7]], [[WIDE_LOAD5]]
169+
; CHECK-CA320-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw float, ptr [[DST]], i64 [[INDEX]]
170+
; CHECK-CA320-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i32 4
171+
; CHECK-CA320-NEXT: store <4 x float> [[TMP6]], ptr [[TMP8]], align 4
172+
; CHECK-CA320-NEXT: store <4 x float> [[TMP7]], ptr [[TMP9]], align 4
173+
; CHECK-CA320-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
174+
; CHECK-CA320-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
175+
; CHECK-CA320-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
176+
; CHECK-CA320: [[MIDDLE_BLOCK]]:
177+
; CHECK-CA320-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
178+
; CHECK-CA320-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]], label %[[SCALAR_PH]]
179+
; CHECK-CA320: [[SCALAR_PH]]:
180+
; CHECK-CA320-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
181+
; CHECK-CA320-NEXT: br label %[[FOR_BODY:.*]]
182+
; CHECK-CA320: [[FOR_BODY]]:
183+
; CHECK-CA320-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
184+
; CHECK-CA320-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDVARS_IV]]
185+
; CHECK-CA320-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX]], align 4
186+
; CHECK-CA320-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[B]], i64 [[INDVARS_IV]]
187+
; CHECK-CA320-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
188+
; CHECK-CA320-NEXT: [[ADD:%.*]] = fadd fast float [[TMP12]], [[TMP11]]
189+
; CHECK-CA320-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[DST]], i64 [[INDVARS_IV]]
190+
; CHECK-CA320-NEXT: store float [[ADD]], ptr [[ARRAYIDX4]], align 4
191+
; CHECK-CA320-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
192+
; CHECK-CA320-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]]
193+
; CHECK-CA320-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
194+
; CHECK-CA320: [[FOR_COND_CLEANUP_LOOPEXIT]]:
195+
; CHECK-CA320-NEXT: br label %[[FOR_COND_CLEANUP]]
196+
; CHECK-CA320: [[FOR_COND_CLEANUP]]:
197+
; CHECK-CA320-NEXT: ret void
198+
;
134199
entry:
135200
%cmp9.not = icmp eq i64 %n, 0
136201
br i1 %cmp9.not, label %for.cond.cleanup, label %for.body
@@ -160,3 +225,8 @@ for.cond.cleanup: ; preds = %for.cond.cleanup.lo
160225
; CHECK-CA520: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
161226
; CHECK-CA520: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
162227
;.
228+
; CHECK-CA320: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
229+
; CHECK-CA320: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
230+
; CHECK-CA320: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
231+
; CHECK-CA320: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
232+
;.

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