support += for complex floats

Author: WalterBright

compiler/src/dmd/backend/arm/cod1.d

@@ -1371,6 +1371,7 @@ void fixresult(ref CodeBuilder cdb, elem* e, regm_t retregs, ref regm_t outretre
     regm_t forccs = outretregs & mPSW;
     regm_t forregs = outretregs & (INSTR.ALLREGS | INSTR.FLOATREGS);
     tym_t tym = tybasic(e.Ety);
+    bool isPair = isRegisterPair(true, tym, 0);
 
     if (tym == TYstruct)
     {
@@ -1388,8 +1389,32 @@ void fixresult(ref CodeBuilder cdb, elem* e, regm_t retregs, ref regm_t outretre
         outretregs = retregs;
     else if (forregs)             // if return the result in registers
     {
-        bool opsflag = false;
-        if (tyfloating(tym))
+        if (isPair)
+        {
+            sz /= 2;
+            reg_t msreg = findreg(retregs & INSTR.MSW);
+            reg_t lsreg = findreg(retregs & INSTR.LSW);
+
+            allocreg(cdb, outretregs, tym);  // allocate return regs
+            reg_t msrreg = findreg(outretregs & INSTR.MSW);
+            reg_t lsrreg = findreg(outretregs & INSTR.LSW);
+
+            // should fix genmovreg() to do this work
+            if (tyfloating(tym))
+            {
+                const uint ftype = INSTR.szToFtype(sz);
+                assert((msreg & lsreg & msrreg & lsrreg) & 32);      // ensure all fp registers
+                cdb.gen1(INSTR.fmov(ftype,msreg,msrreg));            // FMOV msrreg,msreg
+                cdb.gen1(INSTR.fmov(ftype,lsreg,lsrreg));            // FMOV lsrreg,lsreg
+            }
+            else
+            {
+                assert(((msreg | lsreg | msrreg | lsrreg) & 32) == 0); // ensure all gp registers
+                cdb.gen1(INSTR.mov_register(sz == 8,msreg,msrreg));  // MOV msrreg,msreg
+                cdb.gen1(INSTR.mov_register(sz == 8,lsreg,lsrreg));  // MOV lsrreg,lsreg
+            }
+        }
+        else if (tyfloating(tym))
         {
             assert(outretregs & INSTR.FLOATREGS);
             reg_t Vn = findreg(retregs);
@@ -1405,25 +1430,13 @@ void fixresult(ref CodeBuilder cdb, elem* e, regm_t retregs, ref regm_t outretre
                 cdb.gen1(INSTR.fmov(ftype,Vn,Vd));  // FMOV Vd,Vn
             }
         }
-        else if (sz > REGSIZE)
-        {
-            reg_t msreg = findreg(retregs & INSTR.MSW);
-            reg_t lsreg = findreg(retregs & INSTR.LSW);
-
-            allocreg(cdb, outretregs, tym);  // allocate return regs
-            reg_t msrreg = findreg(outretregs & INSTR.MSW);
-            reg_t lsrreg = findreg(outretregs & INSTR.LSW);
-
-            cdb.gen1(INSTR.mov_register(sz == 8,msreg,msrreg));  // MOV msrreg,msreg
-            cdb.gen1(INSTR.mov_register(sz == 8,lsreg,lsrreg));  // MOV lsrreg,lsreg
-        }
         else
         {
             reg_t reg = findreg(retregs & INSTR.ALLREGS);
             reg_t rreg = allocreg(cdb, outretregs, tym);     // allocate return regs
             cdb.gen1(INSTR.mov_register(sz == 8,reg,rreg));  // MOV rreg,reg
         }
-        cssave(e,retregs | outretregs,opsflag);
+        cssave(e,retregs | outretregs,false);
         // Commented out due to Bugzilla 8840
         //forregs = 0;    // don't care about result in reg cuz real result is in rreg
         retregs = outretregs & ~mPSW;

compiler/src/dmd/backend/arm/cod4.d

@@ -592,7 +592,9 @@ void floatOpAss(ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
         if (isregvar(e1,varregm,varreg) && // if lvalue is register variable
             doinreg(e1.Vsym,e2)            // and we can compute directly into it
            )
-        {   regvar = true;
+        {
+            assert(!isPair);            // TODO AArch64
+            regvar = true;
             retregs = varregm;
             reg = varreg;               // evaluate directly in target register
             getregs(cdb,retregs);       // destroy these regs
@@ -605,12 +607,58 @@ void floatOpAss(ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
         retregs = pretregs & INSTR.FLOATREGS & ~rretregs;
         if (!retregs)
             retregs = INSTR.FLOATREGS & ~rretregs;
-        reg = allocreg(cdb,retregs,ty1);
-        loadFromEA(cs,reg,sz1,sz1);
+        allocreg(cdb,retregs,ty1);
+        reg = findreg(isPair ? retregs & INSTR.LSW : retregs);
+        if (isPair)
+            loadFromEA(cs,reg,sz1 / 2,sz1 / 2);
+        else
+            loadFromEA(cs,reg,sz1,sz1);
         cdb.gen(&cs);
     }
 
-    if (sz1 == 16)      // 128 bit float
+    if (isPair)
+    {
+        sz1 /= 2;
+        rreg = findreg(rretregs & INSTR.LSW);
+        reg_t Rd = reg, Rn = rreg, Rm = reg;    // reg = rreg + reg
+        const uint ftype = INSTR.szToFtype(sz1);
+        switch (e.Eoper)
+        {
+            // FADD/FSUB (extended register)
+            // http://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#floatdp2
+            case OPaddass:
+                cdb.gen1(INSTR.fadd_float(ftype,Rn,Rm,Rd));     // FADD Rd,Rn,Rm
+                if (!regvar)
+                {
+                    storeToEA(cs,reg,sz1);
+                    cdb.gen(&cs);
+                }
+
+                reg  = findreg(retregs  & INSTR.MSW);
+                rreg = findreg(rretregs & INSTR.MSW);
+                if (cs.reg == NOREG)
+                    cs.IEV1.Voffset += sz1;
+                else
+                    cs.reg = reg;
+                loadFromEA(cs,reg,sz1,sz1);
+                cdb.gen(&cs);
+                Rd = reg, Rn = rreg, Rm = reg;                  // reg = rreg + reg
+                cdb.gen1(INSTR.fadd_float(ftype,Rn,Rm,Rd));     // FADD Rd,Rn,Rm
+                break;
+
+            case OPminass:
+                cdb.gen1(INSTR.fsub_float(ftype,Rn,Rm,Rd));     // FSUB Rd,Rn,Rm
+                break;
+
+            case OPmulass:
+            case OPdivass:
+                assert(0); // TODO AArch64
+
+            default:
+                assert(0);
+        }
+    }
+    else if (sz1 == 16)      // 128 bit float
     {
         CLIB_A clib;
         switch (e.Eoper)
@@ -631,7 +679,7 @@ void floatOpAss(ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
     }
     else
     {
-        reg_t Rd = reg, Rn = rreg, Rm = reg;
+        const reg_t Rd = reg, Rn = rreg, Rm = reg;
         uint ftype = INSTR.szToFtype(sz1);
         switch (e.Eoper)
         {