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fix clippy
1 parent a2690f7 commit 74d3fe3

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5 files changed

+14
-8
lines changed

5 files changed

+14
-8
lines changed

Cargo.toml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ mio = { version = "1.0", default-features = false }
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cfg-if = "1.0.0"
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polling = "2.8.0"
3535
educe = "0.6.0"
36+
num-conv = "0.1.0"
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libc = "0.2"
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rand = "0.9"

core/Cargo.toml

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,9 @@ mio = { workspace = true, features = [
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nix = { workspace = true, features = ["signal"] }
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libc.workspace = true
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48+
[target.'cfg(all(any(target_os = "linux", target_os = "android"), target_arch = "x86"))'.dependencies]
49+
num-conv.workspace = true
50+
4851
[target.'cfg(target_os = "linux")'.dependencies]
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io-uring = { workspace = true, optional = true }
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core/src/common/ordered_work_steal.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -347,7 +347,7 @@ impl<'l, T: Debug> OrderedLocalQueue<'l, T> {
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/// ```
348348
pub fn pop(&self) -> Option<T> {
349349
//每从本地弹出61次,就从全局队列弹出
350-
if self.tick() % 61 == 0 {
350+
if self.tick().is_multiple_of(61) {
351351
if let Some(val) = self.shared.pop() {
352352
return Some(val);
353353
}

core/src/common/work_steal.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -278,7 +278,7 @@ impl<'l, T: Debug> LocalQueue<'l, T> {
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/// ```
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pub fn pop(&self) -> Option<T> {
280280
//每从本地弹出61次,就从全局队列弹出
281-
if self.tick() % 61 == 0 {
281+
if self.tick().is_multiple_of(61) {
282282
if let Some(val) = self.shared.pop() {
283283
return Some(val);
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}

core/src/coroutine/korosensei.rs

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@ use crate::{catch, warn};
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use corosensei::stack::{DefaultStack, Stack};
88
use corosensei::trap::TrapHandlerRegs;
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use corosensei::CoroutineResult;
10+
#[cfg(all(any(target_os = "linux", target_os = "android"), target_arch = "x86"))]
11+
use num_conv::CastUnsigned;
1012
use std::cell::{Cell, RefCell, UnsafeCell};
1113
use std::collections::VecDeque;
1214
use std::ffi::c_longlong;
@@ -57,7 +59,7 @@ impl<'c, Param, Yield, Return> Coroutine<'c, Param, Yield, Return> {
5759
any(target_os = "linux", target_os = "android"),
5860
target_arch = "x86",
5961
))] {
60-
let sp = u64::from(std::mem::transmute::<_, std::ffi::c_uint>(context.uc_mcontext.gregs[usize::try_from(libc::REG_ESP).expect("overflow")]));
62+
let sp = u64::cast_unsigned(context.uc_mcontext.gregs[usize::try_from(libc::REG_ESP).expect("overflow")].try_into().unwrap());
6163
} else if #[cfg(all(target_vendor = "apple", target_arch = "x86_64"))] {
6264
let sp = u64::try_from((*context.uc_mcontext).__ss.__rsp).expect("overflow");
6365
} else if #[cfg(all(
@@ -108,11 +110,11 @@ impl<'c, Param, Yield, Return> Coroutine<'c, Param, Yield, Return> {
108110
target_arch = "x86",
109111
))] {
110112
let TrapHandlerRegs { eip, esp, ebp, ecx, edx } = regs;
111-
context.uc_mcontext.gregs[usize::try_from(libc::REG_EIP).expect("overflow")] = std::mem::transmute(eip);
112-
context.uc_mcontext.gregs[usize::try_from(libc::REG_ESP).expect("overflow")] = std::mem::transmute(esp);
113-
context.uc_mcontext.gregs[usize::try_from(libc::REG_EBP).expect("overflow")] = std::mem::transmute(ebp);
114-
context.uc_mcontext.gregs[usize::try_from(libc::REG_ECX).expect("overflow")] = std::mem::transmute(ecx);
115-
context.uc_mcontext.gregs[usize::try_from(libc::REG_EDX).expect("overflow")] = std::mem::transmute(edx);
113+
context.uc_mcontext.gregs[usize::try_from(libc::REG_EIP).expect("overflow")] = u32::cast_signed(eip);
114+
context.uc_mcontext.gregs[usize::try_from(libc::REG_ESP).expect("overflow")] = u32::cast_signed(esp);
115+
context.uc_mcontext.gregs[usize::try_from(libc::REG_EBP).expect("overflow")] = u32::cast_signed(ebp);
116+
context.uc_mcontext.gregs[usize::try_from(libc::REG_ECX).expect("overflow")] = u32::cast_signed(ecx);
117+
context.uc_mcontext.gregs[usize::try_from(libc::REG_EDX).expect("overflow")] = u32::cast_signed(edx);
116118
} else if #[cfg(all(target_vendor = "apple", target_arch = "x86_64"))] {
117119
let TrapHandlerRegs { rip, rsp, rbp, rdi, rsi } = regs;
118120
(*context.uc_mcontext).__ss.__rip = rip;

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