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prenticedavidprenticedavid
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rename PORT_t to avoid conflict with AVR8X io.h headers
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‎Adafruit_SPITFT.h‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -28,30 +28,30 @@
2828
// HARDWARE CONFIG ---------------------------------------------------------
2929

3030
#if defined(__AVR__)
31-
typedef uint8_t PORT_t; ///< PORT values are 8-bit
31+
typedef uint8_t ADAGFX_PORT_t; ///< PORT values are 8-bit
3232
#define USE_FAST_PINIO ///< Use direct PORT register access
3333
#elif defined(ARDUINO_STM32_FEATHER) // WICED
3434
typedef class HardwareSPI SPIClass; ///< SPI is a bit odd on WICED
35-
typedef uint32_t PORT_t; ///< PORT values are 32-bit
35+
typedef uint32_t ADAGFX_PORT_t; ///< PORT values are 32-bit
3636
#elif defined(__arm__)
3737
#if defined(ARDUINO_ARCH_SAMD)
3838
// Adafruit M0, M4
39-
typedef uint32_t PORT_t; ///< PORT values are 32-bit
39+
typedef uint32_t ADAGFX_PORT_t; ///< PORT values are 32-bit
4040
#define USE_FAST_PINIO ///< Use direct PORT register access
4141
#define HAS_PORT_SET_CLR ///< PORTs have set & clear registers
4242
#elif defined(CORE_TEENSY)
4343
// PJRC Teensy 4.x
4444
#if defined(__IMXRT1052__) || defined(__IMXRT1062__) // Teensy 4.x
45-
typedef uint32_t PORT_t; ///< PORT values are 32-bit
45+
typedef uint32_t ADAGFX_PORT_t; ///< PORT values are 32-bit
4646
// PJRC Teensy 3.x
4747
#else
48-
typedef uint8_t PORT_t; ///< PORT values are 8-bit
48+
typedef uint8_t ADAGFX_PORT_t; ///< PORT values are 8-bit
4949
#endif
5050
#define USE_FAST_PINIO ///< Use direct PORT register access
5151
#define HAS_PORT_SET_CLR ///< PORTs have set & clear registers
5252
#else
5353
// Arduino Due?
54-
typedef uint32_t PORT_t; ///< PORT values are 32-bit
54+
typedef uint32_t ADAGFX_PORT_t; ///< PORT values are 32-bit
5555
// USE_FAST_PINIO not available here (yet)...Due has a totally different
5656
// GPIO register set and will require some changes elsewhere (e.g. in
5757
// constructors especially).
@@ -61,9 +61,9 @@
6161
// but don't worry about it too much...the digitalWrite() implementation
6262
// on these platforms is reasonably efficient and already RAM-resident,
6363
// only gotcha then is no parallel connection support for now.
64-
typedef uint32_t PORT_t; ///< PORT values are 32-bit
64+
typedef uint32_t ADAGFX_PORT_t; ///< PORT values are 32-bit
6565
#endif // end !ARM
66-
typedef volatile PORT_t* PORTreg_t; ///< PORT register type
66+
typedef volatile ADAGFX_PORT_t* PORTreg_t; ///< PORT register type
6767

6868
#if defined(__AVR__)
6969
#define DEFAULT_SPI_FREQ 8000000L ///< Hardware SPI default speed
@@ -412,19 +412,19 @@ class Adafruit_SPITFT : public Adafruit_GFX {
412412
PORTreg_t sckPortSet; ///< PORT register for SCK SET
413413
PORTreg_t sckPortClr; ///< PORT register for SCK CLEAR
414414
#if !defined(KINETISK)
415-
PORT_t mosiPinMask; ///< Bitmask for MOSI
416-
PORT_t sckPinMask; ///< Bitmask for SCK
415+
ADAGFX_PORT_t mosiPinMask; ///< Bitmask for MOSI
416+
ADAGFX_PORT_t sckPinMask; ///< Bitmask for SCK
417417
#endif // end !KINETISK
418418
#else // !HAS_PORT_SET_CLR
419419
PORTreg_t mosiPort; ///< PORT register for MOSI
420420
PORTreg_t sckPort; ///< PORT register for SCK
421-
PORT_t mosiPinMaskSet; ///< Bitmask for MOSI SET (OR)
422-
PORT_t mosiPinMaskClr; ///< Bitmask for MOSI CLEAR (AND)
423-
PORT_t sckPinMaskSet; ///< Bitmask for SCK SET (OR bitmask)
424-
PORT_t sckPinMaskClr; ///< Bitmask for SCK CLEAR (AND)
421+
ADAGFX_PORT_t mosiPinMaskSet; ///< Bitmask for MOSI SET (OR)
422+
ADAGFX_PORT_t mosiPinMaskClr; ///< Bitmask for MOSI CLEAR (AND)
423+
ADAGFX_PORT_t sckPinMaskSet; ///< Bitmask for SCK SET (OR bitmask)
424+
ADAGFX_PORT_t sckPinMaskClr; ///< Bitmask for SCK CLEAR (AND)
425425
#endif // end HAS_PORT_SET_CLR
426426
#if !defined(KINETISK)
427-
PORT_t misoPinMask; ///< Bitmask for MISO
427+
ADAGFX_PORT_t misoPinMask; ///< Bitmask for MISO
428428
#endif // end !KINETISK
429429
#endif // end USE_FAST_PINIO
430430
int8_t _mosi; ///< MOSI pin #
@@ -456,19 +456,19 @@ class Adafruit_SPITFT : public Adafruit_GFX {
456456
PORTreg_t rdPortSet; ///< PORT register for read strobe SET
457457
PORTreg_t rdPortClr; ///< PORT register for read strobe CLEAR
458458
#if !defined(KINETISK)
459-
PORT_t wrPinMask; ///< Bitmask for write strobe
459+
ADAGFX_PORT_t wrPinMask; ///< Bitmask for write strobe
460460
#endif // end !KINETISK
461-
PORT_t rdPinMask; ///< Bitmask for read strobe
461+
ADAGFX_PORT_t rdPinMask; ///< Bitmask for read strobe
462462
#else // !HAS_PORT_SET_CLR
463463
// Port direction register pointer is always 8-bit regardless of
464464
// PORTreg_t -- even if 32-bit port, we modify a byte-aligned 8 bits.
465465
volatile uint8_t *portDir; ///< PORT direction register
466466
PORTreg_t wrPort; ///< PORT register for write strobe
467467
PORTreg_t rdPort; ///< PORT register for read strobe
468-
PORT_t wrPinMaskSet; ///< Bitmask for write strobe SET (OR)
469-
PORT_t wrPinMaskClr; ///< Bitmask for write strobe CLEAR (AND)
470-
PORT_t rdPinMaskSet; ///< Bitmask for read strobe SET (OR)
471-
PORT_t rdPinMaskClr; ///< Bitmask for read strobe CLEAR (AND)
468+
ADAGFX_PORT_t wrPinMaskSet; ///< Bitmask for write strobe SET (OR)
469+
ADAGFX_PORT_t wrPinMaskClr; ///< Bitmask for write strobe CLEAR (AND)
470+
ADAGFX_PORT_t rdPinMaskSet; ///< Bitmask for read strobe SET (OR)
471+
ADAGFX_PORT_t rdPinMaskClr; ///< Bitmask for read strobe CLEAR (AND)
472472
#endif // end HAS_PORT_SET_CLR
473473
#endif // end USE_FAST_PINIO
474474
int8_t _d0; ///< Data pin 0 #
@@ -492,14 +492,14 @@ class Adafruit_SPITFT : public Adafruit_GFX {
492492
#if defined(USE_FAST_PINIO)
493493
#if defined(HAS_PORT_SET_CLR)
494494
#if !defined(KINETISK)
495-
PORT_t csPinMask; ///< Bitmask for chip select
496-
PORT_t dcPinMask; ///< Bitmask for data/command
495+
ADAGFX_PORT_t csPinMask; ///< Bitmask for chip select
496+
ADAGFX_PORT_t dcPinMask; ///< Bitmask for data/command
497497
#endif // end !KINETISK
498498
#else // !HAS_PORT_SET_CLR
499-
PORT_t csPinMaskSet; ///< Bitmask for chip select SET (OR)
500-
PORT_t csPinMaskClr; ///< Bitmask for chip select CLEAR (AND)
501-
PORT_t dcPinMaskSet; ///< Bitmask for data/command SET (OR)
502-
PORT_t dcPinMaskClr; ///< Bitmask for data/command CLEAR (AND)
499+
ADAGFX_PORT_t csPinMaskSet; ///< Bitmask for chip select SET (OR)
500+
ADAGFX_PORT_t csPinMaskClr; ///< Bitmask for chip select CLEAR (AND)
501+
ADAGFX_PORT_t dcPinMaskSet; ///< Bitmask for data/command SET (OR)
502+
ADAGFX_PORT_t dcPinMaskClr; ///< Bitmask for data/command CLEAR (AND)
503503
#endif // end HAS_PORT_SET_CLR
504504
#endif // end USE_FAST_PINIO
505505
uint8_t connection; ///< TFT_HARD_SPI, TFT_SOFT_SPI, etc.

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