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Commit 1743043

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author
brentru
committed
refactor two write methods into 1
1 parent e3566c8 commit 1743043

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+17
-28
lines changed

1 file changed

+17
-28
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adafruit_wiznet5k/adafruit_wiznet5k.py

Lines changed: 17 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -164,9 +164,12 @@ def __init__(self, spi_bus, cs, reset=None,
164164
reset.value = False
165165
time.sleep(0.1)
166166

167-
# Buffer for reading from module
167+
# Buffer for reading params from module
168168
self._pbuff = bytearray(8)
169169

170+
171+
self._rbuf = bytearray(1)
172+
170173
# attempt to initialize the module
171174
self._ch_base_msb = 0
172175
assert self._w5100_init() == 1, "Failed to initialize WIZnet module."
@@ -246,7 +249,7 @@ def mac_address(self, address):
246249
:param tuple address: Hardware MAC address.
247250
248251
"""
249-
self._write_n(REG_SHAR, 0x04, address)
252+
self.write(REG_SHAR, 0x04, address)
250253

251254
def pretty_mac(self, mac): # pylint: disable=no-self-use, invalid-name
252255
"""Converts a bytearray MAC address to a
@@ -301,7 +304,7 @@ def ifconfig(self, params):
301304
ip_address, subnet_mask, gateway_address, dns_server = params
302305

303306
# Set IP Address
304-
self._write_n(REG_SIPR, 0x04, ip_address)
307+
self.write(REG_SIPR, 0x04, ip_address)
305308

306309
# set subnet and gateway addresses
307310
for octet in range(0, 4):
@@ -385,40 +388,26 @@ def read(self, addr, callback, length=1, buffer=None):
385388
bus_device.write(bytes([addr & 0xFF]))
386389
bus_device.write(bytes([callback]))
387390
if buffer is None:
388-
result = bytearray(length)
389-
bus_device.readinto(result)
390-
return result
391+
self._rxbuf = bytearray(length)
392+
bus_device.readinto(self._rxbuf)
393+
return self._rxbuf
391394
bus_device.readinto(buffer, end=length)
392395
return buffer
393396

394397
def write(self, addr, callback, data):
395-
"""Writes data to a register address.
396-
:param int addr: Register address.
397-
:param int cb: Common register block (?)
398-
:param int data: Data to write to the register.
399-
400-
"""
401398
with self._device as bus_device:
402399
bus_device.write(bytes([addr >> 8]))
403400
bus_device.write(bytes([addr & 0xFF]))
404401
bus_device.write(bytes([callback]))
405-
bus_device.write(bytes([data]))
406402

407-
def _write_n(self, addr, callback, data):
408-
"""Writes data to a register address.
409-
:param int addr: Register address.
410-
:param int data: Data to write to the register.
411-
:param int len: Length of data to write.
412-
413-
"""
414-
with self._device as bus_device:
415-
bus_device.write(bytes([addr >> 8]))
416-
bus_device.write(bytes([addr & 0xFF]))
417-
bus_device.write(bytes([callback]))
418-
for i, _ in enumerate(data):
419-
bus_device.write(bytes([data[i]]))
403+
if hasattr(data,'from_bytes'):
404+
bus_device.write(bytes([data]))
405+
else:
406+
for i, _ in enumerate(data):
407+
bus_device.write(bytes([data[i]]))
420408
return len
421409

410+
422411
# Socket-Register API
423412

424413
def _udp_remaining(self):
@@ -689,7 +678,7 @@ def socket_write(self, socket_num, buffer):
689678
self._write_sntx_wr(socket_num, ptr)
690679

691680
cntl_byte = (0x14+(socket_num<<5))
692-
self._write_n(dst_addr, cntl_byte, buffer)
681+
self.write(dst_addr, cntl_byte, buffer)
693682

694683
self._write_sncr(socket_num, CMD_SOCK_SEND)
695684
self._read_sncr(socket_num)
@@ -815,7 +804,7 @@ def _write_socket(self, sock, address, data, length=None):
815804
cntl_byte = (sock<<5)+0x0C
816805
if length is None:
817806
return self.write(base + sock * CH_SIZE + address, cntl_byte, data)
818-
return self._write_n(base + sock * CH_SIZE + address, cntl_byte, data)
807+
return self.write(base + sock * CH_SIZE + address, cntl_byte, data)
819808

820809
def _read_socket(self, sock, address):
821810
"""Read a W5k socket register.

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