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7 | 7 | {
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8 | 8 | FLASH (rx) : ORIGIN = 0x1c000, LENGTH = 0x64000
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9 | 9 |
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10 |
| - /* ATTR SIZE = 0x0580, (central, prph, sec) = (0, 1, 0) */ |
11 |
| - /* RAM (rwx) : ORIGIN = 0x20002080, LENGTH = 0xdf80 */ |
12 |
| - |
13 |
| - /* ATTR SIZE = 0x1000, (central, prph, sec) = (0, 1, 0) */ |
14 |
| - /* RAM (rwx) : ORIGIN = 0x20002B00, LENGTH = 0xD500 */ |
| 10 | + /* SRAM required by S132 depend on |
| 11 | + * - Attribute Table Size |
| 12 | + * - Number of concurrent connection central + peripherl + secure links |
| 13 | + * Several configuration with different SRAM config is included for reference |
| 14 | + */ |
15 | 15 |
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16 | 16 | /* ATTR SIZE = 0x0B00, (central, prph, sec) = (0, 1, 0) */
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17 |
| - /*RAM (rwx) : ORIGIN = 0x20001B00 + 0x0B00, LENGTH = 0xE500 - 0x0B00*/ |
| 17 | + /* RAM (rwx) : ORIGIN = 0x20001B00 + 0x0B00, LENGTH = 0xE500 - 0x0B00 */ |
18 | 18 |
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19 | 19 | /* ATTR SIZE = 0x0B00, (central, prph, sec) = (4, 1, 1) */
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20 |
| - RAM (rwx) : ORIGIN = 0x20001B00 + 0x0B00 + 0x1280, LENGTH = 0xE500 - 0x0B00 - 0x1280 |
| 20 | + RAM (rwx) : ORIGIN = 0x20001B00 + (0x0B00 + 0x1280), LENGTH = 0xE500 - (0x0B00 + 0x1280) |
21 | 21 |
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22 | 22 | /* ATTR SIZE = 0x0B00, (central, prph, sec) = (7, 1, 1) */
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23 |
| - /* RAM (rwx) : ORIGIN = 0x20001B00 + 0x0B00 + 0x1F08, LENGTH = 0xE500 - 0x0B00 - 0x1F08 */ |
| 23 | + /* RAM (rwx) : ORIGIN = 0x20001B00 + (0x0B00 + 0x1F08), LENGTH = 0xE500 - (0x0B00 + 0x1F08) */ |
24 | 24 | }
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25 | 25 |
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26 | 26 | SECTIONS
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