DM: oops committed wrong stuff, actually fixed DPLL problems

Author: deanm1278

cores/arduino/startup.c

@@ -34,6 +34,9 @@
 //USE DPLL0 for 120MHZ
 #define MAIN_CLOCK_SOURCE				  GCLK_GENCTRL_SRC_DPLL0
 
+#define GENERIC_CLOCK_GENERATOR_1M		  (5u)
+#define CRYSTALLESS
+
 #else
 
 #define GENERIC_CLOCK_GENERATOR_XOSC32K   (1u)
@@ -52,7 +55,7 @@ void SystemInit( void )
   NVMCTRL->CTRLA.reg |= NVMCTRL_CTRLA_RWS(0);
 
   #if defined(CRYSTALLESS)
-  //TODO:
+   
 
 	#else // has crystal
 
@@ -132,30 +135,41 @@ void SystemInit( void )
 	{
 		/* Wait for synchronization */
 	}
+
+	GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_1M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_DIV(24u);
+
+	while ( GCLK->SYNCBUSY.bit.GENCTRL5 ){
+		/* Wait for synchronization */
+	}
+	
 
   /* ------------------------------------------------------------------------
   * Set up the PLLs
   */
 
 	//PLL0 is 120MHz
-   OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x32) | OSCCTRL_DPLLRATIO_LDR(0xe4a); //120 Mhz
+   GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
+	
+   OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(59); //120 Mhz
 
    while(OSCCTRL->Dpll[0].DPLLSYNCBUSY.bit.DPLLRATIO);
 
    //MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51
-   OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 | OSCCTRL_DPLLCTRLB_LBYPASS;
+   OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
 
    OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
 
    while( OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK == 0 );
 
    //PLL1 is 100MHz
-   OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0xc) | OSCCTRL_DPLLRATIO_LDR(0xbea); //120 Mhz
+   GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
+   
+   OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(0x49); //100 Mhz
 
    while(OSCCTRL->Dpll[1].DPLLSYNCBUSY.bit.DPLLRATIO);
 
    //MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51
-   OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 | OSCCTRL_DPLLCTRLB_LBYPASS;
+   OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
 
    OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;