Skip to content

Commit d8f4bf4

Browse files
authored
Merge pull request #366 from rlcamp/master
add missing _Val suffix on arguments to GCLK_GENCTRL_SRC()
2 parents 05e83bc + a67d5be commit d8f4bf4

File tree

1 file changed

+4
-4
lines changed

1 file changed

+4
-4
lines changed

cores/arduino/startup.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@
3535
#define GENERIC_CLOCK_GENERATOR_12M_SYNC GCLK_SYNCBUSY_GENCTRL4
3636

3737
//USE DPLL0 for 120MHZ
38-
#define MAIN_CLOCK_SOURCE GCLK_GENCTRL_SRC_DPLL0
38+
#define MAIN_CLOCK_SOURCE GCLK_GENCTRL_SRC_DPLL0_Val
3939

4040
#define GENERIC_CLOCK_GENERATOR_1M (5u)
4141
//#define CRYSTALLESS
@@ -82,13 +82,13 @@ void SystemInit( void )
8282
/* ----------------------------------------------------------------------------------------------
8383
* 2) Put XOSC32K as source of Generic Clock Generator 3
8484
*/
85-
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_XOSC32K) | //generic clock gen 3
85+
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_XOSC32K_Val) | //generic clock gen 3
8686
GCLK_GENCTRL_GENEN;
8787
#else
8888
/* ----------------------------------------------------------------------------------------------
8989
* 2) Put OSCULP32K as source of Generic Clock Generator 3
9090
*/
91-
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN; //generic clock gen 3
91+
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K_Val) | GCLK_GENCTRL_GENEN; //generic clock gen 3
9292
#endif
9393

9494

@@ -99,7 +99,7 @@ void SystemInit( void )
9999
/* ----------------------------------------------------------------------------------------------
100100
* 3) Put OSCULP32K as source for Generic Clock Generator 0
101101
*/
102-
GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN;
102+
GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K_Val) | GCLK_GENCTRL_GENEN;
103103

104104
/* ----------------------------------------------------------------------------------------------
105105
* 4) Enable DFLL48M clock

0 commit comments

Comments
 (0)