DM: fixed dpll1 freq

Author: deanm1278

cores/arduino/SERCOM.cpp

@@ -741,7 +741,7 @@ void SERCOM::initClockNVIC( void )
   NVIC_EnableIRQ(IdNvic);
 
 #if defined(__SAMD51__)
-  GCLK->PCHCTRL[clk_core].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //TODO: use 48mhz for now although this should work up to 100mhz
+  GCLK->PCHCTRL[clk_core].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
   GCLK->PCHCTRL[clk_slow].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
 
 #else

cores/arduino/SERCOM.h

@@ -21,8 +21,7 @@
 
 #include "sam.h"
 
-//TODO: sercom should really work up to 100Mhz...
-#define SERCOM_FREQ_REF 48000000
+#define SERCOM_FREQ_REF 48000000ul
 
 typedef enum
 {

cores/arduino/startup.c

@@ -164,7 +164,7 @@ void SystemInit( void )
    //PLL1 is 100MHz
    GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
 
-   OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(0x49); //100 Mhz
+   OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(49); //100 Mhz
 
    while(OSCCTRL->Dpll[1].DPLLSYNCBUSY.bit.DPLLRATIO);