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raspberrypi I2SOut: fix flipped stereo channels
1 parent fdc4abf commit 122ea2f

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5 files changed

+172
-73
lines changed

5 files changed

+172
-73
lines changed

ports/raspberrypi/common-hal/audiobusio/I2SOut.c

Lines changed: 72 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -27,70 +27,107 @@ const uint16_t i2s_program[] = {
2727
; /--- LRCLK
2828
; |/-- BCLK
2929
; ||
30+
pull noblock side 0b11 ; Loads OSR with the next FIFO value or X
31+
mov x osr side 0b11 ; Save the new value in case we need it again
32+
set y 14 side 0b11
33+
bitloop1:
34+
out pins 1 side 0b10 [2]
35+
jmp y-- bitloop1 side 0b11 [2]
36+
out pins 1 side 0b00 [2]
37+
set y 14 side 0b01 [2]
38+
bitloop0:
39+
out pins 1 side 0b00 [2]
40+
jmp y-- bitloop0 side 0b01 [2]
41+
out pins 1 side 0b10 [2]
42+
*/
43+
// Above assembled with pioasm.
44+
0x9880, // 0: pull noblock side 3
45+
0xb827, // 1: mov x, osr side 3
46+
0xf84e, // 2: set y, 14 side 3
47+
0x7201, // 3: out pins, 1 side 2 [2]
48+
0x1a83, // 4: jmp y--, 3 side 3 [2]
49+
0x6201, // 5: out pins, 1 side 0 [2]
50+
0xea4e, // 6: set y, 14 side 1 [2]
51+
0x6201, // 7: out pins, 1 side 0 [2]
52+
0x0a87, // 8: jmp y--, 7 side 1 [2]
53+
0x7201, // 9: out pins, 1 side 2 [2]
54+
};
55+
56+
57+
const uint16_t i2s_program_left_justified[] = {
58+
/*
59+
.program i2s
60+
.side_set 2
61+
62+
; Load the next set of samples
63+
; /--- LRCLK
64+
; |/-- BCLK
65+
; ||
3066
pull noblock side 0b01 ; Loads OSR with the next FIFO value or X
3167
mov x osr side 0b01 ; Save the new value in case we need it again
3268
set y 14 side 0b01
3369
bitloop1:
34-
out pins 1 side 0b00 [2]
35-
jmp y-- bitloop1 side 0b01 [2]
70+
out pins 1 side 0b10 [2]
71+
jmp y-- bitloop1 side 0b11 [2]
3672
out pins 1 side 0b10 [2]
3773
set y 14 side 0b11 [2]
3874
bitloop0:
39-
out pins 1 side 0b10 [2]
40-
jmp y-- bitloop0 side 0b11 [2]
75+
out pins 1 side 0b00 [2]
76+
jmp y-- bitloop0 side 0b01 [2]
4177
out pins 1 side 0b00 [2]
4278
*/
4379
// Above assembled with pioasm.
4480
0x8880, // 0: pull noblock side 1
4581
0xa827, // 1: mov x, osr side 1
4682
0xe84e, // 2: set y, 14 side 1
47-
0x6201, // 3: out pins, 1 side 0 [2]
48-
0x0a83, // 4: jmp y--, 3 side 1 [2]
83+
0x7201, // 3: out pins, 1 side 2 [2]
84+
0x1a83, // 4: jmp y--, 3 side 3 [2]
4985
0x7201, // 5: out pins, 1 side 2 [2]
5086
0xfa4e, // 6: set y, 14 side 3 [2]
51-
0x7201, // 7: out pins, 1 side 2 [2]
52-
0x1a87, // 8: jmp y--, 7 side 3 [2]
87+
0x6201, // 7: out pins, 1 side 0 [2]
88+
0x0a87, // 8: jmp y--, 7 side 1 [2]
5389
0x6201, // 9: out pins, 1 side 0 [2]
5490
};
5591

56-
57-
const uint16_t i2s_program_left_justified[] = {
92+
// Another version of i2s_program with the LRCLC and BCLK pin swapped
93+
const uint16_t i2s_program_swap[] = {
5894
/*
5995
.program i2s
6096
.side_set 2
6197
6298
; Load the next set of samples
63-
; /--- LRCLK
64-
; |/-- BCLK
65-
; ||
99+
; /--- BCLK
100+
; |/-- LRCLK
101+
; ||
66102
pull noblock side 0b11 ; Loads OSR with the next FIFO value or X
67103
mov x osr side 0b11 ; Save the new value in case we need it again
68104
set y 14 side 0b11
69105
bitloop1:
106+
out pins 1 side 0b01 [2]
107+
jmp y-- bitloop1 side 0b11 [2]
70108
out pins 1 side 0b00 [2]
71-
jmp y-- bitloop1 side 0b01 [2]
72-
out pins 1 side 0b00 [2]
73-
set y 14 side 0b01 [2]
109+
set y 14 side 0b10 [2]
74110
bitloop0:
75-
out pins 1 side 0b10 [2]
76-
jmp y-- bitloop0 side 0b11 [2]
77-
out pins 1 side 0b10 [2]
111+
out pins 1 side 0b00 [2]
112+
jmp y-- bitloop0 side 0b10 [2]
113+
out pins 1 side 0b01 [2]
78114
*/
79115
// Above assembled with pioasm.
80116
0x9880, // 0: pull noblock side 3
81117
0xb827, // 1: mov x, osr side 3
82118
0xf84e, // 2: set y, 14 side 3
83-
0x6201, // 3: out pins, 1 side 0 [2]
84-
0x0a83, // 4: jmp y--, 3 side 1 [2]
119+
0x6a01, // 3: out pins, 1 side 1 [2]
120+
0x1a83, // 4: jmp y--, 3 side 3 [2]
85121
0x6201, // 5: out pins, 1 side 0 [2]
86-
0xea4e, // 6: set y, 14 side 1 [2]
87-
0x7201, // 7: out pins, 1 side 2 [2]
88-
0x1a87, // 8: jmp y--, 7 side 3 [2]
89-
0x7201, // 9: out pins, 1 side 2 [2]
122+
0xf24e, // 6: set y, 14 side 2 [2]
123+
0x6201, // 7: out pins, 1 side 0 [2]
124+
0x1287, // 8: jmp y--, 7 side 2 [2]
125+
0x6a01, // 9: out pins, 1 side 1 [2]
90126
};
91127

92-
// Another version of i2s_program with the LRCLC and BCLK pin swapped
93-
const uint16_t i2s_program_swap[] = {
128+
// Another version of i2s_program_left_justified with the LRCLC and BCLK pin
129+
// swapped.
130+
const uint16_t i2s_program_left_justified_swap[] = {
94131
/*
95132
.program i2s
96133
.side_set 2
@@ -103,64 +140,26 @@ const uint16_t i2s_program_swap[] = {
103140
mov x osr side 0b10 ; Save the new value in case we need it again
104141
set y 14 side 0b10
105142
bitloop1:
106-
out pins 1 side 0b00 [2]
107-
jmp y-- bitloop1 side 0b10 [2]
143+
out pins 1 side 0b01 [2]
144+
jmp y-- bitloop1 side 0b11 [2]
108145
out pins 1 side 0b01 [2]
109146
set y 14 side 0b11 [2]
110147
bitloop0:
111-
out pins 1 side 0b01 [2]
112-
jmp y-- bitloop0 side 0b11 [2]
148+
out pins 1 side 0b00 [2]
149+
jmp y-- bitloop0 side 0b10 [2]
113150
out pins 1 side 0b00 [2]
114151
*/
115152
// Above assembled with pioasm.
116153
0x9080, // 0: pull noblock side 2
117154
0xb027, // 1: mov x, osr side 2
118155
0xf04e, // 2: set y, 14 side 2
119-
0x6201, // 3: out pins, 1 side 0 [2]
120-
0x1283, // 4: jmp y--, 3 side 2 [2]
156+
0x6a01, // 3: out pins, 1 side 1 [2]
157+
0x1a83, // 4: jmp y--, 3 side 3 [2]
121158
0x6a01, // 5: out pins, 1 side 1 [2]
122159
0xfa4e, // 6: set y, 14 side 3 [2]
123-
0x6a01, // 7: out pins, 1 side 1 [2]
124-
0x1a87, // 8: jmp y--, 7 side 3 [2]
160+
0x6201, // 7: out pins, 1 side 0 [2]
161+
0x1287, // 8: jmp y--, 7 side 2 [2]
125162
0x6201, // 9: out pins, 1 side 0 [2]
126-
127-
};
128-
129-
// Another version of i2s_program_left_justified with the LRCLC and BCLK pin
130-
// swapped.
131-
const uint16_t i2s_program_left_justified_swap[] = {
132-
/*
133-
.program i2s
134-
.side_set 2
135-
136-
; Load the next set of samples
137-
; /--- BCLK
138-
; |/-- LRCLK
139-
; ||
140-
pull noblock side 0b11 ; Loads OSR with the next FIFO value or X
141-
mov x osr side 0b11 ; Save the new value in case we need it again
142-
set y 14 side 0b11
143-
bitloop1:
144-
out pins 1 side 0b00 [2]
145-
jmp y-- bitloop1 side 0b10 [2]
146-
out pins 1 side 0b00 [2]
147-
set y 14 side 0b10 [2]
148-
bitloop0:
149-
out pins 1 side 0b01 [2]
150-
jmp y-- bitloop0 side 0b11 [2]
151-
out pins 1 side 0b01 [2]
152-
*/
153-
// Above assembled with pioasm.
154-
0x9880, // 0: pull noblock side 3
155-
0xb827, // 1: mov x, osr side 3
156-
0xf84e, // 2: set y, 14 side 3
157-
0x6201, // 3: out pins, 1 side 0 [2]
158-
0x1283, // 4: jmp y--, 3 side 2 [2]
159-
0x6201, // 5: out pins, 1 side 0 [2]
160-
0xf24e, // 6: set y, 14 side 2 [2]
161-
0x6a01, // 7: out pins, 1 side 1 [2]
162-
0x1a87, // 8: jmp y--, 7 side 3 [2]
163-
0x6a01, // 9: out pins, 1 side 1 [2]
164163
};
165164

166165
void i2sout_reset(void) {
Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
; This file is part of the CircuitPython project: https://circuitpython.org
2+
;
3+
; SPDX-FileCopyrightText: Copyright (c) 2025 Dan Halbert for Adafruit Industries
4+
;
5+
; SPDX-License-Identifier: MIT
6+
7+
.program i2s
8+
.side_set 2
9+
10+
; Load the next set of samples
11+
; /--- LRCLK
12+
; |/-- BCLK
13+
; ||
14+
pull noblock side 0b11 ; Loads OSR with the next FIFO value or X
15+
mov x osr side 0b11 ; Save the new value in case we need it again
16+
set y 14 side 0b11
17+
bitloop1:
18+
out pins 1 side 0b10 [2]
19+
jmp y-- bitloop1 side 0b11 [2]
20+
out pins 1 side 0b00 [2]
21+
set y 14 side 0b01 [2]
22+
bitloop0:
23+
out pins 1 side 0b00 [2]
24+
jmp y-- bitloop0 side 0b01 [2]
25+
out pins 1 side 0b10 [2]
Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
; This file is part of the CircuitPython project: https://circuitpython.org
2+
;
3+
; SPDX-FileCopyrightText: Copyright (c) 2025 Dan Halbert for Adafruit Industries
4+
;
5+
; SPDX-License-Identifier: MIT
6+
7+
.program i2s
8+
.side_set 2
9+
10+
; Load the next set of samples
11+
; /--- LRCLK
12+
; |/-- BCLK
13+
; ||
14+
pull noblock side 0b01 ; Loads OSR with the next FIFO value or X
15+
mov x osr side 0b01 ; Save the new value in case we need it again
16+
set y 14 side 0b01
17+
bitloop1:
18+
out pins 1 side 0b10 [2]
19+
jmp y-- bitloop1 side 0b11 [2]
20+
out pins 1 side 0b10 [2]
21+
set y 14 side 0b11 [2]
22+
bitloop0:
23+
out pins 1 side 0b00 [2]
24+
jmp y-- bitloop0 side 0b01 [2]
25+
out pins 1 side 0b00 [2]
Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
; This file is part of the CircuitPython project: https://circuitpython.org
2+
;
3+
; SPDX-FileCopyrightText: Copyright (c) 2025 Dan Halbert for Adafruit Industries
4+
;
5+
; SPDX-License-Identifier: MIT
6+
7+
.program i2s
8+
.side_set 2
9+
10+
; Load the next set of samples
11+
; /--- BCLK
12+
; |/-- LRCLK
13+
; ||
14+
pull noblock side 0b11 ; Loads OSR with the next FIFO value or X
15+
mov x osr side 0b11 ; Save the new value in case we need it again
16+
set y 14 side 0b11
17+
bitloop1:
18+
out pins 1 side 0b01 [2]
19+
jmp y-- bitloop1 side 0b11 [2]
20+
out pins 1 side 0b00 [2]
21+
set y 14 side 0b10 [2]
22+
bitloop0:
23+
out pins 1 side 0b00 [2]
24+
jmp y-- bitloop0 side 0b10 [2]
25+
out pins 1 side 0b01 [2]
Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
; This file is part of the CircuitPython project: https://circuitpython.org
2+
;
3+
; SPDX-FileCopyrightText: Copyright (c) 2025 Dan Halbert for Adafruit Industries
4+
;
5+
; SPDX-License-Identifier: MIT
6+
7+
.program i2s
8+
.side_set 2
9+
10+
; Load the next set of samples
11+
; /--- BCLK
12+
; |/-- LRCLK
13+
; ||
14+
pull noblock side 0b10 ; Loads OSR with the next FIFO value or X
15+
mov x osr side 0b10 ; Save the new value in case we need it again
16+
set y 14 side 0b10
17+
bitloop1:
18+
out pins 1 side 0b01 [2]
19+
jmp y-- bitloop1 side 0b11 [2]
20+
out pins 1 side 0b01 [2]
21+
set y 14 side 0b11 [2]
22+
bitloop0:
23+
out pins 1 side 0b00 [2]
24+
jmp y-- bitloop0 side 0b10 [2]
25+
out pins 1 side 0b00 [2]

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