Wait for the DFLL to be stable.

tannewt · tannewt · commit 383bf9a59e16 · 2018-06-08T12:56:32.000-07:00
diff --git a/ports/atmel-samd/peripherals/samd21/clocks.c b/ports/atmel-samd/peripherals/samd21/clocks.c
@@ -130,6 +130,9 @@ static void init_clock_source_dfll48m_xosc(void) {
                             SYSCTRL_DFLLCTRL_ENABLE;
     while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}
     while (GCLK->STATUS.bit.SYNCBUSY) {}
+
+    // Wait for the fine lock on the DFLL.
+    while (!SYSCTRL->PCLKSR.bit.DFLLLCKC || !SYSCTRL->PCLKSR.bit.DFLLLCKF) {}
 }
 
 static void init_clock_source_dfll48m_usb(void) {

Original file line number	Diff line number	Diff line change
`@@ -130,6 +130,9 @@ static void init_clock_source_dfll48m_xosc(void) {`
`130`	`130`	`SYSCTRL_DFLLCTRL_ENABLE;`
`131`	`131`	`while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}`
`132`	`132`	`while (GCLK->STATUS.bit.SYNCBUSY) {}`
	`133`	`+`
	`134`	`+ // Wait for the fine lock on the DFLL.`
	`135`	`+ while (!SYSCTRL->PCLKSR.bit.DFLLLCKC \|\| !SYSCTRL->PCLKSR.bit.DFLLLCKF) {}`
`133`	`136`	`}`
`134`	`137`
`135`	`138`	`static void init_clock_source_dfll48m_usb(void) {`