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bradanlanebradanlane
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initial m0 coin build
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‎ports/atmel-samd/boards/bradanlanestudio_coin_m0/board.c

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// This file is part of the CircuitPython project: https://circuitpython.org
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//
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// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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//
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// SPDX-License-Identifier: MIT
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#include "supervisor/board.h"
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// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here.

‎ports/atmel-samd/boards/bradanlanestudio_coin_m0/flash_config.c_txt

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# This file is part of the CircuitPython project: https://circuitpython.org
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#
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# SPDX-FileCopyrightText: Copyright (c) 2024 Bradán Lane STUDIO
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#
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# SPDX-License-Identifier: MIT
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#include "boards/flash_config.h"
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#include "xip/fsl_flexspi_nor_boot.h"
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// Config for W25Q32JVSSIQ with QSPI routed.
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__attribute__((section(".boot_hdr.conf")))
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const flexspi_nor_config_t qspiflash_config = {
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz,
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.blockSize = 0x00010000,
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.isUniformBlockSize = false,
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromSckPad,
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.csHoldTime = 3u,
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.csSetupTime = 3u,
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.busyOffset = 0u, // Status bit 0 indicates busy.
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.busyBitPolarity = 0u, // Busy when the bit is 1.
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.deviceModeCfgEnable = 1u,
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.deviceModeType = kDeviceConfigCmdType_QuadEnable,
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.deviceModeSeq = {
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.seqId = 4u,
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.seqNum = 1u,
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},
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.deviceModeArg = 0x40,
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.deviceType = kFLEXSPIDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFLEXSPISerialClk_60MHz,
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.sflashA1Size = 8u * 1024u * 1024u,
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.lookupTable =
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{
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// FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
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// The high 16 bits is command 1 and the low are command 0.
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// Within a command, the top 6 bits are the opcode, the next two are the number
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// of pads and then last byte is the operand. The operand's meaning changes
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// per opcode.
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// Indices with ROM should always have the same function because the ROM
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// bootloader uses it.
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// 0: ROM: Read LUTs
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// Quad version
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SEQUENCE(
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FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
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RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
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FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
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READ_SDR, FLEXSPI_4PAD, 0x04),
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// Single fast read version, good for debugging.
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// FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
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// RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
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// FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
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// READ_SDR, FLEXSPI_1PAD, 0x04),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 1: ROM: Read status
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SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
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READ_SDR, FLEXSPI_1PAD, 0x02),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 2: Empty
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EMPTY_SEQUENCE,
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// 3: ROM: Write Enable
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SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
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STOP, FLEXSPI_1PAD, 0x00),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 4: Config: Write Status
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SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */,
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WRITE_SDR, FLEXSPI_1PAD, 0x01),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 5: ROM: Erase Sector
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SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
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RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 6: Empty
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EMPTY_SEQUENCE,
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// 7: Empty
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EMPTY_SEQUENCE,
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// 8: Block Erase
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SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
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RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 9: ROM: Page program
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SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
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RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
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FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
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STOP, FLEXSPI_1PAD, 0),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 10: Empty
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EMPTY_SEQUENCE,
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// 11: ROM: Chip erase
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SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
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STOP, FLEXSPI_1PAD, 0),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 12: Empty
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EMPTY_SEQUENCE,
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// 13: ROM: Read SFDP
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EMPTY_SEQUENCE,
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// 14: ROM: Restore no cmd
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EMPTY_SEQUENCE,
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// 15: ROM: Dummy
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EMPTY_SEQUENCE
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},
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},
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};

‎ports/atmel-samd/boards/bradanlanestudio_coin_m0/mpconfigboard.h

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// This file is part of the CircuitPython project: https://circuitpython.org
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//
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// SPDX-FileCopyrightText: Copyright (c) 2024 Bradán Lane STUDIO
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//
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// SPDX-License-Identifier: MIT
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#pragma once
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#define MICROPY_HW_BOARD_NAME "Bradán Lane STUDIO M0 Coin"
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#define MICROPY_HW_MCU_NAME "samd21g18"
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#define MICROPY_HW_LED_STATUS (&pin_PA17)
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#define SPI_FLASH_MOSI_PIN &pin_PB22
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#define SPI_FLASH_MISO_PIN &pin_PB03
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#define SPI_FLASH_SCK_PIN &pin_PB23
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#define SPI_FLASH_CS_PIN &pin_PA27
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// USB is always used internally so skip the pin objects for it.
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// Not connected
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#define IGNORE_PIN_PA13 1
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#define IGNORE_PIN_PA28 1
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#define IGNORE_PIN_PA00 1
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#define IGNORE_PIN_PA01 1
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// PIN_PA02 = A0
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#define IGNORE_PIN_PA03 1
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#define IGNORE_PIN_PA04 1
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#define IGNORE_PIN_PA05 1
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#define IGNORE_PIN_PA06 1
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#define IGNORE_PIN_PA07 1
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#define IGNORE_PIN_PA08 1
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#define IGNORE_PIN_PA09 1
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#define IGNORE_PIN_PA10 1
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#define IGNORE_PIN_PA11 1
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#define IGNORE_PIN_PA12 1
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#define IGNORE_PIN_PA13 1
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#define IGNORE_PIN_PA14 1
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#define IGNORE_PIN_PA15 1
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#define IGNORE_PIN_PA20 1
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#define IGNORE_PIN_PA21 1
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#define IGNORE_PIN_PA22 1
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#define IGNORE_PIN_PA23 1
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#define IGNORE_PIN_PA24 1 // USB_D+
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#define IGNORE_PIN_PA25 1 // USB_D-
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// PIN_PA27 = SPI_FLASH_CS
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#define IGNORE_PIN_PA28 1
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#define IGNORE_PIN_PA30 1 // SWCLK
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#define IGNORE_PIN_PA31 1 // SWDIO
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// PIN_PB02 = A5
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// PIN_PB03 = SPI_FLASH_MISO
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// PIN_PB08 = A1
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// PIN_PB09 = A2
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#define IGNORE_PIN_PB10 1 // MOSI
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#define IGNORE_PIN_PB11 1 // SCK
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// PIN_PB22 = SPI_FLASH_MOSI
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// PIN_PB23 = SPI_FLASH_SCK

‎ports/atmel-samd/boards/bradanlanestudio_coin_m0/mpconfigboard.mk

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# This file is part of the CircuitPython project: https://circuitpython.org
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#
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# SPDX-FileCopyrightText: Copyright (c) 2024 Bradán Lane STUDIO
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#
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# SPDX-License-Identifier: MIT
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# TODO new VID:PID not yet approved via pidcodes.github.com
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USB_VID = 0x1209
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USB_PID = 0x5687
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USB_PRODUCT = "M0 Coin"
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USB_MANUFACTURER = "Bradán Lane STUDIO"
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CHIP_VARIANT = SAMD21G18A
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CHIP_FAMILY = samd21
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CIRCUITPY_BUILD_EXTENSIONS = bin,uf2
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#INTERNAL_FLASH_FILESYSTEM = 1
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#LONGINT_IMPL = NONE
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#CIRCUITPY_FULL_BUILD = 0
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SPI_FLASH_FILESYSTEM = 1
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EXTERNAL_FLASH_DEVICES = "W25Q32JVxQ"
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LONGINT_IMPL = MPZ
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CIRCUITPY_PULSEIO = 0
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CIRCUITPY_AUDIOIO = 0
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CIRCUITPY_AUDIOBUSIO = 0
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# Include these Python libraries in firmware.
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#FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel
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#FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_HID

‎ports/atmel-samd/boards/bradanlanestudio_coin_m0/pins.c

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// This file is part of the CircuitPython project: https://circuitpython.org
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//
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// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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//
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// SPDX-License-Identifier: MIT
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#include "shared-bindings/board/__init__.h"
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static const mp_rom_map_elem_t board_module_globals_table[] = {
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CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
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// { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA11) },
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// { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA11) },
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// { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA10) },
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// { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA10) },
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// { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA14) },
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// { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA09) },
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// { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA08) },
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// { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA15) },
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// { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA20) },
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// { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA21) },
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// { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) },
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// { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) },
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{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) },
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{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) },
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{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) },
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{ MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PA17) },
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{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) },
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// { MP_ROM_QSTR(MP_QSTR_L), MP_ROM_PTR(&pin_PA17) }, // a.k.a D13
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{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) },
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{ MP_ROM_QSTR(MP_QSTR_BUZZER), MP_ROM_PTR(&pin_PA02) },
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{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PB08) },
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{ MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_PB08) },
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{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PB09) },
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{ MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_PB09) },
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// { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA04) },
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// { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA05) },
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{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB02) },
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{ MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_PB02) },
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// { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB10) },
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// { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA12) },
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// { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB11) },
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// { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA23) },
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// { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) },
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// { MP_ROM_QSTR(MP_QSTR_APA102_MOSI), MP_ROM_PTR(&pin_PA01) },
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// { MP_ROM_QSTR(MP_QSTR_DOTSTAR_DATA), MP_ROM_PTR(&pin_PA01) },
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// { MP_ROM_QSTR(MP_QSTR_APA102_SCK), MP_ROM_PTR(&pin_PA00) },
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// { MP_ROM_QSTR(MP_QSTR_DOTSTAR_CLOCK), MP_ROM_PTR(&pin_PA00) },
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// { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
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// { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
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// { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
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};
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MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);

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