Merge branch 'master' into stm32-temperature-us

Author: hierophect

.github/workflows/build.yml

@@ -219,6 +219,7 @@ jobs:
         - "stm32f411ce_blackpill"
         - "stm32f411ve_discovery"
         - "stm32f412zg_discovery"
+        - "stm32f4_discovery"
         - "stringcar_m0_express"
         - "teensy40"
         - "teknikio_bluebird"

ports/nrf/boards/common.template.ld

@@ -22,7 +22,9 @@ MEMORY
     /* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.
     /* To measure the minimum required amount of memory for given configuration, set this number
        high enough to work and then check the mutation of the value done by sd_ble_enable. */
-    RAM (xrw)       : ORIGIN = 0x20000000 + 64K, LENGTH = 256K - 64K
+    SPIM3_RAM (rw)  : ORIGIN = 0x20000000 + 64K, LENGTH = 8K
+    RAM (xrw)       : ORIGIN = 0x20000000 + 64K + 8K, LENGTH = 256K - 64K -8K
+
 }
 
 /* produce a link error if there is not this amount of RAM available */
@@ -37,6 +39,10 @@ _estack = ORIGIN(RAM) + LENGTH(RAM);
 _ram_end = ORIGIN(RAM) + LENGTH(RAM);
 _heap_end = 0x20020000; /* tunable */
 
+/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. */
+_spim3_ram = ORIGIN(SPIM3_RAM);
+_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);
+
 /* define output sections */
 SECTIONS
 {

ports/nrf/common-hal/busio/SPI.c

@@ -22,47 +22,55 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <string.h>
+
 #include "shared-bindings/busio/SPI.h"
 #include "py/mperrno.h"
 #include "py/runtime.h"
 
 #include "nrfx_spim.h"
 #include "nrf_gpio.h"
 
+// These are in order from ighest available frequency to lowest (32MHz first, then 8MHz).
 STATIC spim_peripheral_t spim_peripherals[] = {
 #if NRFX_CHECK(NRFX_SPIM3_ENABLED)
     // SPIM3 exists only on nRF52840 and supports 32MHz max. All other SPIM's are only 8MHz max.
     // Allocate SPIM3 first.
     { .spim = NRFX_SPIM_INSTANCE(3),
-      .max_frequency_MHz = 32,
+      .max_frequency = 32000000,
       .max_xfer_size = SPIM3_EASYDMA_MAXCNT_SIZE,
     },
 #endif
 #if NRFX_CHECK(NRFX_SPIM2_ENABLED)
     // SPIM2 is not shared with a TWIM, so allocate before the shared ones.
     { .spim = NRFX_SPIM_INSTANCE(2),
-      .max_frequency_MHz = 8,
+      .max_frequency = 8000000,
       .max_xfer_size = SPIM2_EASYDMA_MAXCNT_SIZE,
     },
 #endif
 #if NRFX_CHECK(NRFX_SPIM1_ENABLED)
     // SPIM1 and TWIM1 share an address.
     { .spim = NRFX_SPIM_INSTANCE(1),
-      .max_frequency_MHz = 8,
+      .max_frequency = 8000000,
       .max_xfer_size = SPIM1_EASYDMA_MAXCNT_SIZE,
     },
 #endif
 #if NRFX_CHECK(NRFX_SPIM0_ENABLED)
     // SPIM0 and TWIM0 share an address.
     { .spim = NRFX_SPIM_INSTANCE(0),
-      .max_frequency_MHz = 8,
+      .max_frequency = 8000000,
       .max_xfer_size = SPIM0_EASYDMA_MAXCNT_SIZE,
     },
 #endif
 };
 
 STATIC bool never_reset[MP_ARRAY_SIZE(spim_peripherals)];
 
+// Separate RAM area for SPIM3 transmit buffer to avoid SPIM3 hardware errata.
+// https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF52840_Rev2%2FERR%2FnRF52840%2FRev2%2Flatest%2Fanomaly_840_198.html
+extern uint32_t _spim3_ram;
+STATIC uint8_t *spim3_transmit_buffer = (uint8_t *) &_spim3_ram;
+
 void spi_reset(void) {
     for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) {
         if (never_reset[i]) {
@@ -122,7 +130,7 @@ static nrf_spim_frequency_t baudrate_to_spim_frequency(const uint32_t baudrate)
 }
 
 void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi, const mcu_pin_obj_t * miso) {
-    // Find a free instance.
+    // Find a free instance, with most desirable (highest freq and not shared) allocated first.
     self->spim_peripheral = NULL;
     for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) {
         if ((spim_peripherals[i].spim.p_reg->ENABLE & SPIM_ENABLE_ENABLE_Msk) == 0) {
@@ -137,7 +145,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t *
 
     nrfx_spim_config_t config = NRFX_SPIM_DEFAULT_CONFIG(NRFX_SPIM_PIN_NOT_USED, NRFX_SPIM_PIN_NOT_USED,
                                                          NRFX_SPIM_PIN_NOT_USED, NRFX_SPIM_PIN_NOT_USED);
-    config.frequency = NRF_SPIM_FREQ_8M;
+
+    config.frequency = baudrate_to_spim_frequency(self->spim_peripheral->max_frequency);
 
     config.sck_pin = clock->number;
     self->clock_pin_number = clock->number;
@@ -189,8 +198,7 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self, uint32_t baudrate, ui
 
     // Set desired frequency, rounding down, and don't go above available frequency for this SPIM.
     nrf_spim_frequency_set(self->spim_peripheral->spim.p_reg,
-                           baudrate_to_spim_frequency(MIN(baudrate,
-                                                          self->spim_peripheral->max_frequency_MHz * 1000000)));
+                           baudrate_to_spim_frequency(MIN(baudrate, self->spim_peripheral->max_frequency)));
 
     nrf_spim_mode_t mode = NRF_SPIM_MODE_0;
     if (polarity) {
@@ -224,21 +232,36 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
 }
 
 bool common_hal_busio_spi_write(busio_spi_obj_t *self, const uint8_t *data, size_t len) {
-    if (len == 0)
+    if (len == 0) {
         return true;
+    }
+
+    const bool is_spim3 = self->spim_peripheral->spim.p_reg == NRF_SPIM3;
 
     const uint32_t max_xfer_size = self->spim_peripheral->max_xfer_size;
     const uint32_t parts = len / max_xfer_size;
     const uint32_t remainder = len % max_xfer_size;
 
     for (uint32_t i = 0; i < parts; ++i) {
-        const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(data + i * max_xfer_size, max_xfer_size);
+        uint8_t *start = (uint8_t *) (data + i * max_xfer_size);
+        if (is_spim3) {
+            // If SPIM3, copy into unused RAM block, and do DMA from there.
+            memcpy(spim3_transmit_buffer, start, max_xfer_size);
+            start = spim3_transmit_buffer;
+        }
+        const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(start, max_xfer_size);
         if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS)
             return false;
     }
 
     if (remainder > 0) {
-        const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(data + parts * max_xfer_size, remainder);
+        uint8_t *start = (uint8_t *) (data + parts * max_xfer_size);
+        if (is_spim3) {
+            // If SPIM3, copy into unused RAM block, and do DMA from there.
+            memcpy(spim3_transmit_buffer, start, remainder);
+            start = spim3_transmit_buffer;
+        }
+        const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(start, remainder);
         if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS)
             return false;
     }
@@ -247,8 +270,9 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self, const uint8_t *data, size
 }
 
 bool common_hal_busio_spi_read(busio_spi_obj_t *self, uint8_t *data, size_t len, uint8_t write_value) {
-    if (len == 0)
+    if (len == 0) {
         return true;
+    }
 
     const uint32_t max_xfer_size = self->spim_peripheral->max_xfer_size;
     const uint32_t parts = len / max_xfer_size;
@@ -270,23 +294,37 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self, uint8_t *data, size_t len,
 }
 
 bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, uint8_t *data_out, uint8_t *data_in, size_t len) {
-    if (len == 0)
+    if (len == 0) {
         return true;
+    }
 
+    const bool is_spim3 = self->spim_peripheral->spim.p_reg == NRF_SPIM3;
 
     const uint32_t max_xfer_size = self->spim_peripheral->max_xfer_size;
     const uint32_t parts = len / max_xfer_size;
     const uint32_t remainder = len % max_xfer_size;
 
     for (uint32_t i = 0; i < parts; ++i) {
-        const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(data_out + i * max_xfer_size, max_xfer_size,
+        uint8_t *out_start = (uint8_t *) (data_out + i * max_xfer_size);
+        if (is_spim3) {
+            // If SPIM3, copy into unused RAM block, and do DMA from there.
+            memcpy(spim3_transmit_buffer, out_start, max_xfer_size);
+            out_start = spim3_transmit_buffer;
+        }
+        const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(out_start, max_xfer_size,
             data_in + i * max_xfer_size, max_xfer_size);
         if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS)
             return false;
     }
 
     if (remainder > 0) {
-        const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(data_out + parts * max_xfer_size, remainder,
+        uint8_t *out_start = (uint8_t *) (data_out + parts * max_xfer_size);
+        if (is_spim3) {
+            // If SPIM3, copy into unused RAM block, and do DMA from there.
+            memcpy(spim3_transmit_buffer, out_start, remainder);
+            out_start = spim3_transmit_buffer;
+        }
+        const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(out_start, remainder,
             data_in + parts * max_xfer_size, remainder);
         if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS)
             return false;
@@ -325,9 +363,9 @@ uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) {
 }
 
 uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) {
-    return 0;
+    return (self->spim_peripheral->spim.p_reg->CONFIG & SPIM_CONFIG_CPHA_Msk) >> SPIM_CONFIG_CPHA_Pos;
 }
 
 uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) {
-    return 0;
+    return (self->spim_peripheral->spim.p_reg->CONFIG & SPIM_CONFIG_CPOL_Msk) >> SPIM_CONFIG_CPOL_Pos;
 }

ports/nrf/common-hal/busio/SPI.h

@@ -32,7 +32,7 @@
 
 typedef struct {
     nrfx_spim_t spim;
-    uint8_t max_frequency_MHz;
+    uint32_t max_frequency;
     uint8_t max_xfer_size;
 } spim_peripheral_t;
 

ports/nrf/nrfx_config.h

@@ -26,10 +26,9 @@
 
 // CIRCUITPY_NRF_NUM_I2C is 1 or 2 to choose how many I2C (TWIM) peripherals
 // to provide.
-// This can go away once we have SPIM3 working: then we can have two
-// I2C and two SPI.
+// With SPIM3 working we can have two I2C and two SPI.
 #ifndef CIRCUITPY_NRF_NUM_I2C
-#define CIRCUITPY_NRF_NUM_I2C 1
+#define CIRCUITPY_NRF_NUM_I2C 2
 #endif
 
 #if CIRCUITPY_NRF_NUM_I2C != 1 && CIRCUITPY_NRF_NUM_I2C != 2
@@ -42,13 +41,12 @@
 #define NRFX_SPIM1_ENABLED 1
 #endif
 #define NRFX_SPIM2_ENABLED 1
-// DON'T ENABLE SPIM3 DUE TO ANOMALY WORKAROUND FAILURE (SEE ABOVE).
-// #ifdef NRF52840_XXAA
-//     #define NRFX_SPIM_EXTENDED_ENABLED 1
-//     #define NRFX_SPIM3_ENABLED 1
-// #else
-//     #define NRFX_SPIM3_ENABLED 0
-// #endif
+#ifdef NRF52840_XXAA
+    #define NRFX_SPIM_EXTENDED_ENABLED 1
+    #define NRFX_SPIM3_ENABLED 1
+#else
+    #define NRFX_SPIM3_ENABLED 0
+#endif
 
 
 #define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7

ports/stm32f4/boards/STM32F407_fs.ld

@@ -0,0 +1,108 @@
+/*
+    GNU linker script for STM32F405 via Micropython
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K /* entire flash */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
+    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 48K /* sectors 1,2,3 are 16K */
+    FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 960K /* sector 4 is 64K, sectors 5,6,7 are 128K */
+    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 64K
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+
+/* Define tho top end of the stack.  The stack is full descending so begins just
+   above last byte of RAM.  Note that EABI requires the stack to be 8-byte
+   aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+
+ENTRY(Reset_Handler)
+
+/* define output sections */
+SECTIONS
+{
+    /* The startup code goes first into FLASH */
+    .isr_vector :
+    {
+        . = ALIGN(4);
+        KEEP(*(.isr_vector)) /* Startup code */
+
+        /* This first flash block is 16K annd the isr vectors only take up
+           about 400 bytes. Micropython pads this with files, but this didn't
+           work with the size of Circuitpython's ff object. */
+
+        . = ALIGN(4);
+    } >FLASH_ISR
+
+    /* The program code and other data goes into FLASH */
+    .text :
+    {
+        . = ALIGN(4);
+        *(.text*)          /* .text* sections (code) */
+        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    /*  *(.glue_7)   */    /* glue arm to thumb code */
+    /*  *(.glue_7t)  */    /* glue thumb to arm code */
+
+        . = ALIGN(4);
+        _etext = .;        /* define a global symbol at end of code */
+    } >FLASH_TEXT
+
+    /* used by the startup to initialize data */
+    _sidata = LOADADDR(.data);
+
+    /* This is the initialized data section
+    The program executes knowing that the data is in the RAM
+    but the loader puts the initial values in the FLASH (inidata).
+    It is one task of the startup to copy the initial values from FLASH to RAM. */
+    .data :
+    {
+        . = ALIGN(4);
+        _sdata = .;        /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
+        *(.data*)          /* .data* sections */
+
+        . = ALIGN(4);
+        _edata = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
+    } >RAM AT> FLASH_TEXT
+
+    /* Uninitialized data section */
+    .bss :
+    {
+        . = ALIGN(4);
+        _sbss = .;         /* define a global symbol at bss start; used by startup code */
+        *(.bss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        _ebss = .;         /* define a global symbol at bss end; used by startup code and GC */
+    } >RAM
+
+    /* this is to define the start of the heap, and make sure we have a minimum size */
+    .heap :
+    {
+        . = ALIGN(4);
+        . = . + _minimum_heap_size;
+        . = ALIGN(4);
+    } >RAM
+
+    /* this just checks there is enough RAM for the stack */
+    .stack :
+    {
+        . = ALIGN(4);
+        . = . + _minimum_stack_size;
+        . = ALIGN(4);
+    } >RAM
+
+    .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+

ports/stm32f4/boards/feather_stm32f405_express/mpconfigboard.h

@@ -34,6 +34,8 @@
 
 #define MICROPY_HW_NEOPIXEL (&pin_PC00)
 
+#define BOARD_OSC_DIV 12
+
 // On-board flash
 #define SPI_FLASH_MOSI_PIN          (&pin_PB05)
 #define SPI_FLASH_MISO_PIN          (&pin_PB04)

ports/stm32f4/boards/pyboard_v11/mpconfigboard.h

@@ -32,6 +32,7 @@
 #define FLASH_SIZE                  (0x100000)
 #define FLASH_PAGE_SIZE             (0x4000)
 
+#define BOARD_OSC_DIV 12
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PB06)
 #define DEFAULT_I2C_BUS_SDA (&pin_PB07)