Manual pre-commit fix for all requisite files.

U-ANALOG\BHurst · U-ANALOG\BHurst · commit 5541ae345abd · 2024-09-27T09:46:38.000-07:00
diff --git a/ports/analog/boards/max32690evkit/pins.c b/ports/analog/boards/max32690evkit/pins.c
@@ -9,7 +9,7 @@
 
 static const mp_rom_map_elem_t board_module_globals_table[] = {
     CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
-    //P0
+    // P0
     { MP_ROM_QSTR(MP_QSTR_P0_00), MP_ROM_PTR(&pin_P0_00) },
     { MP_ROM_QSTR(MP_QSTR_P0_01), MP_ROM_PTR(&pin_P0_01) },
     { MP_ROM_QSTR(MP_QSTR_P0_02), MP_ROM_PTR(&pin_P0_02) },
@@ -42,7 +42,7 @@ static const mp_rom_map_elem_t board_module_globals_table[] = {
     { MP_ROM_QSTR(MP_QSTR_P0_29), MP_ROM_PTR(&pin_P0_29) },
     { MP_ROM_QSTR(MP_QSTR_P0_30), MP_ROM_PTR(&pin_P0_30) },
     { MP_ROM_QSTR(MP_QSTR_P0_31), MP_ROM_PTR(&pin_P0_31) },
-    //P1
+    // P1
     { MP_ROM_QSTR(MP_QSTR_P1_00), MP_ROM_PTR(&pin_P1_00) },
     { MP_ROM_QSTR(MP_QSTR_P1_01), MP_ROM_PTR(&pin_P1_01) },
     { MP_ROM_QSTR(MP_QSTR_P1_02), MP_ROM_PTR(&pin_P1_02) },
@@ -75,7 +75,7 @@ static const mp_rom_map_elem_t board_module_globals_table[] = {
     { MP_ROM_QSTR(MP_QSTR_P1_29), MP_ROM_PTR(&pin_P1_29) },
     { MP_ROM_QSTR(MP_QSTR_P1_30), MP_ROM_PTR(&pin_P1_30) },
     { MP_ROM_QSTR(MP_QSTR_P1_31), MP_ROM_PTR(&pin_P1_31) },
-    //P2
+    // P2
     { MP_ROM_QSTR(MP_QSTR_P2_00), MP_ROM_PTR(&pin_P2_00) },
     { MP_ROM_QSTR(MP_QSTR_P2_01), MP_ROM_PTR(&pin_P2_01) },
     { MP_ROM_QSTR(MP_QSTR_P2_02), MP_ROM_PTR(&pin_P2_02) },
@@ -108,7 +108,7 @@ static const mp_rom_map_elem_t board_module_globals_table[] = {
     { MP_ROM_QSTR(MP_QSTR_P2_29), MP_ROM_PTR(&pin_P2_29) },
     { MP_ROM_QSTR(MP_QSTR_P2_30), MP_ROM_PTR(&pin_P2_30) },
     { MP_ROM_QSTR(MP_QSTR_P2_31), MP_ROM_PTR(&pin_P2_31) },
-    //P3
+    // P3
     { MP_ROM_QSTR(MP_QSTR_P3_00), MP_ROM_PTR(&pin_P3_00) },
     { MP_ROM_QSTR(MP_QSTR_P3_01), MP_ROM_PTR(&pin_P3_01) },
     { MP_ROM_QSTR(MP_QSTR_P3_02), MP_ROM_PTR(&pin_P3_02) },
@@ -119,7 +119,7 @@ static const mp_rom_map_elem_t board_module_globals_table[] = {
     { MP_ROM_QSTR(MP_QSTR_P3_07), MP_ROM_PTR(&pin_P3_07) },
     { MP_ROM_QSTR(MP_QSTR_P3_08), MP_ROM_PTR(&pin_P3_08) },
     { MP_ROM_QSTR(MP_QSTR_P3_09), MP_ROM_PTR(&pin_P3_09) },
-    //P4
+    // P4
     { MP_ROM_QSTR(MP_QSTR_P4_00), MP_ROM_PTR(&pin_P4_00) },
     { MP_ROM_QSTR(MP_QSTR_P4_01), MP_ROM_PTR(&pin_P4_01) },
 };
diff --git a/ports/analog/max32_port.h b/ports/analog/max32_port.h
@@ -42,4 +42,4 @@ extern uint32_t SystemCoreClock;
 #define SUBSEC_PER_TICK 4
 #endif
 
-#endif //MAX32_PORT_H
+#endif // MAX32_PORT_H
diff --git a/ports/analog/supervisor/internal_flash.c b/ports/analog/supervisor/internal_flash.c
@@ -75,8 +75,9 @@ static uint32_t page_buffer[FLASH_PAGE_SIZE / 4] = {0x0};
 static inline int32_t block2addr(uint32_t block) {
     if (block >= 0 && block < INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS) {
         return CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR + block * FILESYSTEM_BLOCK_SIZE;
+    } else {
+        return -1;
     }
-    else return -1;
 }
 
 // Get index, start addr, & size of the flash sector where addr lies
@@ -91,15 +92,13 @@ int flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size) {
             }
             if (start_addr) {
                 *start_addr = flash_layout[0].base_addr + (sector_index * flash_layout[0].sector_size);
-            }
-            else {
+            } else {
                 return -1; // start_addr is NULL
             }
             if (size) {
                 *size = flash_layout[0].sector_size;
-            }
-            else {
-                return -1; //size is NULL
+            } else {
+                return -1; // size is NULL
             }
             return sector_index;
         }
@@ -176,7 +175,7 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n
     /** NOTE:   The MXC_FLC_Read function executes from SRAM and does some more error checking
     *          than memcpy does. Will use it for now.
     */
-    MXC_FLC_Read( src_addr, dest, FILESYSTEM_BLOCK_SIZE * num_blocks );
+    MXC_FLC_Read(src_addr, dest, FILESYSTEM_BLOCK_SIZE * num_blocks);
 
     return 0; // success
 }
@@ -205,12 +204,12 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num,
         MXC_ICC_Disable(MXC_ICC0);
 
         // Buffer the page of flash to erase
-        MXC_FLC_Read(page_start , page_buffer, page_size);
+        MXC_FLC_Read(page_start, page_buffer, page_size);
 
         // Erase flash page
         MXC_CRITICAL(
             error = MXC_FLC_PageErase(dest_addr);
-        );
+            );
         if (error != E_NO_ERROR) {
             // lock flash & reset
             MXC_FLC0->ctrl = (MXC_FLC0->ctrl & ~MXC_F_FLC_REVA_CTRL_UNLOCK) | MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED;
@@ -220,12 +219,12 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num,
         // Copy new src data into the page buffer
         // fill the new data in at the offset dest_addr - page_start
         // account for uint32_t page_buffer vs uint8_t src
-        memcpy( (page_buffer + (dest_addr - page_start) / 4), src, count * FILESYSTEM_BLOCK_SIZE);
+        memcpy((page_buffer + (dest_addr - page_start) / 4), src, count * FILESYSTEM_BLOCK_SIZE);
 
         // Write new page buffer back into flash
         MXC_CRITICAL(
             error = MXC_FLC_Write(page_start, page_size, page_buffer);
-        );
+            );
         if (error != E_NO_ERROR) {
             // lock flash & reset
             MXC_FLC0->ctrl = (MXC_FLC0->ctrl & ~MXC_F_FLC_REVA_CTRL_UNLOCK) | MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED;
diff --git a/ports/analog/supervisor/port.c b/ports/analog/supervisor/port.c
@@ -46,8 +46,8 @@
 
 // msec to RTC subsec ticks (4 kHz)
 #define MSEC_TO_SS_ALARM(x) \
-    (0 - ((x * 4096) /  \
-          1000)) /* Converts a time in milleseconds to the equivalent RSSA register value. */
+        (0 - ((x * 4096) /  \
+    1000))       /* Converts a time in milleseconds to the equivalent RSSA register value. */
 
 // Externs defined by linker .ld file
 extern uint32_t _stack, _heap, _estack, _eheap;
@@ -70,7 +70,7 @@ safe_mode_t port_init(void) {
     int err = E_NO_ERROR;
 
     // Enable GPIO (enables clocks + common init for ports)
-    for (int i = 0; i < MXC_CFG_GPIO_INSTANCES; i++){
+    for (int i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) {
         err = MXC_GPIO_Init(0x1 << i);
         if (err) {
             return SAFE_MODE_PROGRAMMATIC;
@@ -93,22 +93,28 @@ safe_mode_t port_init(void) {
 
     // Enable clock to RTC peripheral
     MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN;
-    while(!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERTCO_RDY));
+    while (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERTCO_RDY)) {
+        ;
+    }
 
     NVIC_EnableIRQ(RTC_IRQn);
     NVIC_EnableIRQ(USB_IRQn);
 
     // Init RTC w/ 0sec, 0subsec
     // Driven by 32.768 kHz ERTCO, with ssec= 1/4096 s
-    while( MXC_RTC_Init(0,0) != E_SUCCESS ) {};
+    while (MXC_RTC_Init(0, 0) != E_SUCCESS) {
+    }
+    ;
 
     // enable 1 sec RTC SSEC alarm
     MXC_RTC_DisableInt(MXC_F_RTC_CTRL_SSEC_ALARM_IE);
     MXC_RTC_SetSubsecondAlarm(MSEC_TO_SS_ALARM(1000));
     MXC_RTC_EnableInt(MXC_F_RTC_CTRL_SSEC_ALARM_IE);
 
     // Enable RTC
-    while ( MXC_RTC_Start() != E_SUCCESS ) {};
+    while (MXC_RTC_Start() != E_SUCCESS) {
+    }
+    ;
 
     return SAFE_MODE_NONE;
 }
@@ -191,9 +197,10 @@ uint64_t port_get_raw_ticks(uint8_t *subticks) {
     __disable_irq();
     if (MXC_RTC->ctrl & MXC_F_RTC_CTRL_EN) {
         // NOTE: RTC_GetTime always returns BUSY if RTC is not running
-        while( (MXC_RTC_GetTime(&sec, &subsec)) != E_NO_ERROR );
-    }
-    else {
+        while ((MXC_RTC_GetTime(&sec, &subsec)) != E_NO_ERROR) {
+            ;
+        }
+    } else {
         sec = MXC_RTC->sec;
         subsec = MXC_RTC->ssec;
     }
@@ -232,15 +239,19 @@ void port_interrupt_after_ticks(uint32_t ticks) {
     ticks_msec = 1000 * ticks / TICKS_PER_SEC;
 
     while (MXC_RTC_DisableInt(MXC_F_RTC_CTRL_SSEC_ALARM_IE |
-                                MXC_F_RTC_CTRL_TOD_ALARM_IE) == E_BUSY) {};
+        MXC_F_RTC_CTRL_TOD_ALARM_IE) == E_BUSY) {
+    }
+    ;
 
     // Clear the flag to be set by the RTC Handler
     tick_flag = 0;
 
     // Subsec alarm is the starting/reload value of the SSEC counter.
     // ISR triggered when SSEC rolls over from 0xFFFF_FFFF to 0x0
-    while ( MXC_RTC_SetSubsecondAlarm(MSEC_TO_SS_ALARM(ticks_msec) ) == E_BUSY) {}
-    while (MXC_RTC_EnableInt(MXC_F_RTC_CTRL_SSEC_ALARM_IE) == E_BUSY) {}
+    while (MXC_RTC_SetSubsecondAlarm(MSEC_TO_SS_ALARM(ticks_msec)) == E_BUSY) {
+    }
+    while (MXC_RTC_EnableInt(MXC_F_RTC_CTRL_SSEC_ALARM_IE) == E_BUSY) {
+    }
 
     NVIC_EnableIRQ(RTC_IRQn);
 
@@ -249,10 +260,10 @@ void port_interrupt_after_ticks(uint32_t ticks) {
 
 void port_idle_until_interrupt(void) {
     #if CIRCUITPY_RTC
-        // Check if alarm triggers before we even got here
-        if (MXC_RTC_GetFlags() == (MXC_F_RTC_CTRL_TOD_ALARM | MXC_F_RTC_CTRL_SSEC_ALARM)) {
-            return;
-        }
+    // Check if alarm triggers before we even got here
+    if (MXC_RTC_GetFlags() == (MXC_F_RTC_CTRL_TOD_ALARM | MXC_F_RTC_CTRL_SSEC_ALARM)) {
+        return;
+    }
     #endif
 
     // Interrupts should be disabled to ensure the ISR queue is flushed
