canio: Fix implementation bugs in atmel-sam

Author: jepler

ports/atmel-samd/common-hal/canio/CAN.c

@@ -176,7 +176,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
 
     {
         CAN_TXBC_Type bc = {
-            .bit.TBSA = (uint32_t)self->state->tx_fifo,
+            .bit.TBSA = (uint32_t)self->state->tx_buffer,
             .bit.NDTB = COMMON_HAL_CANIO_TX_FIFO_SIZE,
             .bit.TFQM = 0, // Messages are transmitted in the order submitted
         };
@@ -192,7 +192,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
 
     {
         CAN_GFC_Type gfc = {
-            .bit.RRFE = 1,
+            .bit.RRFE = 0,
             .bit.ANFS = CAN_GFC_ANFS_REJECT_Val,
             .bit.ANFE = CAN_GFC_ANFE_REJECT_Val,
         };
@@ -333,13 +333,13 @@ void common_hal_canio_can_send(canio_can_obj_t *self, canio_message_obj_t *messa
     maybe_auto_restart(self);
 
     // We have just one dedicated TX buffer, use it!
-    canio_can_fifo_t *ent = &self->state->tx_fifo[0];
+    canio_can_tx_buffer_t *ent = &self->state->tx_buffer[0];
 
     ent->txb0.bit.ESI = false;
     ent->txb0.bit.XTD = message->extended;
     ent->txb0.bit.RTR = message->rtr;
     if (message->extended) {
-        ent->txb0.bit.ID = message->id << 18;
+        ent->txb0.bit.ID = message->id;
     } else {
         ent->txb0.bit.ID = message->id << 18; // short addresses are left-justified
     }

ports/atmel-samd/common-hal/canio/Listener.c

@@ -358,15 +358,15 @@ bool common_hal_canio_listener_readinto(canio_listener_obj_t *self, canio_messag
         } while (!common_hal_canio_listener_in_waiting(self));
     }
     int index = self->hw->RXFS.bit.F0GI;
-    canio_can_fifo_t *hw_message = &self->fifo[index];
-    message->extended = hw_message->rxb0.bit.XTD;
+    canio_can_rx_fifo_t *hw_message = &self->fifo[index];
+    message->extended = hw_message->rxf0.bit.XTD;
     if (message->extended) {
-        message->id = hw_message->rxb0.bit.ID;
+        message->id = hw_message->rxf0.bit.ID;
     } else {
-        message->id = hw_message->rxb0.bit.ID >> 18; // short addresses are left-justified
+        message->id = hw_message->rxf0.bit.ID >> 18; // short addresses are left-justified
     }
-    message->rtr = hw_message->rxb0.bit.RTR;
-    message->size = hw_message->rxb1.bit.DLC;
+    message->rtr = hw_message->rxf0.bit.RTR;
+    message->size = hw_message->rxf1.bit.DLC;
     if (!message->rtr) {
         memcpy(message->data, hw_message->data, message->size);
     }

ports/atmel-samd/common-hal/canio/Listener.h

@@ -38,7 +38,7 @@ typedef struct {
 typedef struct {
     mp_obj_base_t base;
     canio_can_obj_t *can;
-    canio_can_fifo_t *fifo;
+    canio_can_rx_fifo_t *fifo;
     canio_rxfifo_reg_t *hw;
     uint32_t timeout_ms;
     uint8_t fifo_idx;

ports/atmel-samd/common-hal/canio/__init__.h

@@ -42,26 +42,25 @@ typedef struct canio_listener canio_listener_t;
 typedef struct canio_can canio_can_t;
 
 typedef struct {
-    union {
-        CAN_RXBE_0_Type rxb0;
-        CAN_TXBE_0_Type txb0;
-        CAN_RXF0E_0_Type rxf0;
-    };
-    union {
-        CAN_RXBE_1_Type rxb1;
-        CAN_TXBE_1_Type txb1;
-        CAN_RXF0E_1_Type rxf1;
-    };
+    CAN_TXBE_0_Type txb0;
+    CAN_TXBE_1_Type txb1;
     COMPILER_ALIGNED(4)
     uint8_t data[COMMON_HAL_CANIO_MAX_MESSAGE_LENGTH];
-} canio_can_fifo_t;
+} canio_can_tx_buffer_t;
+
+typedef struct {
+    CAN_RXF0E_0_Type rxf0;
+    CAN_RXF0E_1_Type rxf1;
+    COMPILER_ALIGNED(4)
+    uint8_t data[COMMON_HAL_CANIO_MAX_MESSAGE_LENGTH];
+} canio_can_rx_fifo_t;
 
 typedef uint32_t canio_can_filter_t;
 
 typedef struct {
-    canio_can_fifo_t tx_fifo[COMMON_HAL_CANIO_TX_FIFO_SIZE];
-    canio_can_fifo_t rx0_fifo[COMMON_HAL_CANIO_RX_FIFO_SIZE];
-    canio_can_fifo_t rx1_fifo[COMMON_HAL_CANIO_RX_FIFO_SIZE];
+    canio_can_tx_buffer_t tx_buffer[COMMON_HAL_CANIO_TX_FIFO_SIZE];
+    canio_can_rx_fifo_t rx0_fifo[COMMON_HAL_CANIO_RX_FIFO_SIZE];
+    canio_can_rx_fifo_t rx1_fifo[COMMON_HAL_CANIO_RX_FIFO_SIZE];
     CanMramSidfe standard_rx_filter[COMMON_HAL_CANIO_RX_FILTER_SIZE];
     CanMramXifde extended_rx_filter[COMMON_HAL_CANIO_RX_FILTER_SIZE];
 } canio_can_state_t;