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Add Teensy 4.1 board definition
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‎.github/workflows/build.yml

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@@ -249,6 +249,7 @@ jobs:
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- "stm32f746g_discovery"
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- "stringcar_m0_express"
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- "teensy40"
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- "teensy41"
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- "teknikio_bluebird"
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- "thunderpack"
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- "trellis_m4_express"

‎ports/mimxrt10xx/boards/teensy41/board.c

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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
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* Copyright (c) 2019 Artur Pacholec
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "boards/board.h"
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#include "mpconfigboard.h"
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void board_init(void) {
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}
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bool board_requests_safe_mode(void) {
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return false;
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}
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void reset_board(void) {
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}

‎ports/mimxrt10xx/boards/teensy41/board.ld

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_ld_reserved_flash_size = 4K;

‎ports/mimxrt10xx/boards/teensy41/flash_config.c

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/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexspi_nor_boot.h"
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#include "fsl_flexspi_nor_config.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.xip_device"
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#endif
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__attribute__((section(".boot_hdr.ivt")))
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/*************************************
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* IVT Data
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*************************************/
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const ivt image_vector_table = {
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IVT_HEADER, /* IVT Header */
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IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
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IVT_RSVD, /* Reserved = 0 */
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(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
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(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
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(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
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(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
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IVT_RSVD /* Reserved = 0 */
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};
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__attribute__((section(".boot_hdr.boot_data")))
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/*************************************
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* Boot Data
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*************************************/
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const BOOT_DATA_T boot_data = {
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FLASH_BASE, /* boot start location */
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FLASH_SIZE, /* size */
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PLUGIN_FLAG, /* Plugin flag*/
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0xFFFFFFFF /* empty - extra data word */
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};
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__attribute__((section(".boot_hdr.conf")))
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// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
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const flexspi_nor_config_t qspiflash_config = {
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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.csHoldTime = 1u,
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.csSetupTime = 2u,
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// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
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.sflashA1Size = FLASH_SIZE,
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.lookupTable =
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{
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// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
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// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
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// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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// Read LUTs
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
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0,
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0,
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0x24040405,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x00000406,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x08180420,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x081804D8,
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0,
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0,
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0,
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0x08180402,
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0x00002004,
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0,
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0,
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0,
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0,
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0,
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0,
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0x00000460,
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
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.blockSize = 0x00010000,
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.isUniformBlockSize = false,
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};

‎ports/mimxrt10xx/boards/teensy41/mpconfigboard.h

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#define MICROPY_HW_BOARD_NAME "Teensy 4.1"
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#define MICROPY_HW_MCU_NAME "IMXRT1062DVJ6A"
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// If you change this, then make sure to update the linker scripts as well to
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// make sure you don't overwrite code
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#define CIRCUITPY_INTERNAL_NVM_SIZE 0
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#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
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#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_AD_B1_00)
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#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_AD_B1_01)
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#define DEFAULT_SPI_BUS_SCK (&pin_GPIO_B0_03)
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#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO_B0_02)
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#define DEFAULT_SPI_BUS_MISO (&pin_GPIO_B0_01)
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#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B0_03)
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#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B0_02)

‎ports/mimxrt10xx/boards/teensy41/mpconfigboard.mk

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USB_VID = 0x239A
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USB_PID = 0x80AE
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USB_PRODUCT = "Teensy 4.1"
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USB_MANUFACTURER = "PJRC"
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CHIP_VARIANT = MIMXRT1062DVJ6A
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CHIP_FAMILY = MIMXRT1062
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FLASH = W25Q64JV

‎ports/mimxrt10xx/boards/teensy41/pins.c

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#include "shared-bindings/board/__init__.h"
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#include "boards/board.h"
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STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
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// With USB on left. Bottom edge.
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_RX1), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_TX1), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_EMC_04) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_EMC_05) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_EMC_06) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_EMC_08) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_B0_10) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_B1_01) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_B1_00) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_B0_11) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_B0_00) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_B0_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO_B0_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_B0_01) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO_B0_01) },
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// Bottom Edge extended for 4.1
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_GPIO_EMC_32) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_GPIO_EMC_31) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_GPIO_EMC_37) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_GPIO_EMC_36) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_GPIO_B0_12) },
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// Top edge
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_B0_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO_B0_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA0), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL0), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
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// Top edge extended for Teensy 4.1
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_GPIO_EMC_07) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_GPIO_B1_13) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_GPIO_B1_12) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_GPIO_B1_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_GPIO_B1_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
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// SD Card slot
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{ MP_OBJ_NEW_QSTR(MP_QSTR_DAT1), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_DAT0), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_DAT3), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_DAT2), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D47), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
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// Flash expansion spot and PSRAM expansion spot on a shared QSPI BUS
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D48), MP_ROM_PTR(&pin_GPIO_EMC_24) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_PSRAM_CS), MP_ROM_PTR(&pin_GPIO_EMC_24) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D49), MP_ROM_PTR(&pin_GPIO_EMC_27) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_QSPI_IO1), MP_ROM_PTR(&pin_GPIO_EMC_27) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D50), MP_ROM_PTR(&pin_GPIO_EMC_28) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_QSPI_IO2), MP_ROM_PTR(&pin_GPIO_EMC_28) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D51), MP_ROM_PTR(&pin_GPIO_EMC_22) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_CS), MP_ROM_PTR(&pin_GPIO_EMC_22) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D52), MP_ROM_PTR(&pin_GPIO_EMC_26) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_QSPI_IO0), MP_ROM_PTR(&pin_GPIO_EMC_26) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D53), MP_ROM_PTR(&pin_GPIO_EMC_25) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_QSPI_CLK), MP_ROM_PTR(&pin_GPIO_EMC_25) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_D54), MP_ROM_PTR(&pin_GPIO_EMC_29) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_QSPI_IO3), MP_ROM_PTR(&pin_GPIO_EMC_29) },
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{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
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{ MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
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{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
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};
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MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);

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