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| 1 | +/* |
| 2 | + * This file is part of the Micro Python project, http://micropython.org/ |
| 3 | + * |
| 4 | + * The MIT License (MIT) |
| 5 | + * |
| 6 | + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries |
| 7 | + * |
| 8 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | + * of this software and associated documentation files (the "Software"), to deal |
| 10 | + * in the Software without restriction, including without limitation the rights |
| 11 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | + * copies of the Software, and to permit persons to whom the Software is |
| 13 | + * furnished to do so, subject to the following conditions: |
| 14 | + * |
| 15 | + * The above copyright notice and this permission notice shall be included in |
| 16 | + * all copies or substantial portions of the Software. |
| 17 | + * |
| 18 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 21 | + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | + * THE SOFTWARE. |
| 25 | + */ |
| 26 | + |
| 27 | +static bool stm_timer_reserved[MP_ARRAY_SIZE(mcu_tim_banks)]; |
| 28 | +static bool stm_timer_never_reset[MP_ARRAY_SIZE(mcu_tim_banks)]; |
| 29 | +static void *stm_timer_callback[MP_ARRAY_SIZE(mcu_tim_banks)](void); |
| 30 | + |
| 31 | +STATIC void tim_clock_enable(uint16_t mask); |
| 32 | +STATIC void tim_clock_disable(uint16_t mask); |
| 33 | + |
| 34 | +// Get the frequency (in Hz) of the source clock for the given timer. |
| 35 | +// On STM32F405/407/415/417 there are 2 cases for how the clock freq is set. |
| 36 | +// If the APB prescaler is 1, then the timer clock is equal to its respective |
| 37 | +// APB clock. Otherwise (APB prescaler > 1) the timer clock is twice its |
| 38 | +// respective APB clock. See DM00031020 Rev 4, page 115. |
| 39 | +STATIC uint32_t timer_get_source_freq(uint32_t tim_id) { |
| 40 | + uint32_t source, clk_div; |
| 41 | + if (tim_id == 1 || (8 <= tim_id && tim_id <= 11)) { |
| 42 | + // TIM{1,8,9,10,11} are on APB2 |
| 43 | + source = HAL_RCC_GetPCLK2Freq(); |
| 44 | + clk_div = RCC->CFGR & RCC_CFGR_PPRE2; |
| 45 | + } else { |
| 46 | + // TIM{2,3,4,5,6,7,12,13,14} are on APB1 |
| 47 | + source = HAL_RCC_GetPCLK1Freq(); |
| 48 | + clk_div = RCC->CFGR & RCC_CFGR_PPRE1; |
| 49 | + } |
| 50 | + if (clk_div != 0) { |
| 51 | + // APB prescaler for this timer is > 1 |
| 52 | + source *= 2; |
| 53 | + } |
| 54 | + return source; |
| 55 | +} |
| 56 | + |
| 57 | +TIM_TypeDef * stm_peripherals_find_timer(void) { |
| 58 | + // TODO: check for unreserved timers from already claimed pins |
| 59 | + |
| 60 | + // Work backwards - higher index timers have fewer pin allocations |
| 61 | + for (size_t i = MP_ARRAY_SIZE(stm_timer_reserved); i>=0; i--) { |
| 62 | + if ((!stm_timer_reserved[i]) && (mcu_tim_banks[i] != NULL)) { |
| 63 | + return mcu_tim_banks[i]; |
| 64 | + } |
| 65 | + } |
| 66 | + mp_raise_RuntimeError(translate("All timers in use")); |
| 67 | + return NULL; |
| 68 | +} |
| 69 | + |
| 70 | +void stm_peripherals_timer_set_callback(void(*callback)(void), TIM_TypeDef * timer) { |
| 71 | + stm_timer_callback[stm_peripherals_timer_get_index] |
| 72 | +} |
| 73 | + |
| 74 | +void stm_peripherals_timer_free(TIM_TypeDef * instance) { |
| 75 | + |
| 76 | +} |
| 77 | +void stm_peripherals_timer_never_reset(TIM_TypeDef * instance); |
| 78 | +void stm_peripherals_timer_reset_ok(TIM_TypeDef * instance); |
| 79 | +void stm_peripherals_timer_is_never_reset(TIM_TypeDef * instance); |
| 80 | +void stm_peripherals_timer_is_reserved(TIM_TypeDef * instance); |
| 81 | +size_t stm_peripherals_timer_get_index(TIM_TypeDef * instance); |
| 82 | + |
| 83 | +STATIC void tim_clock_enable(uint16_t mask) { |
| 84 | + #ifdef TIM1 |
| 85 | + if (mask & (1 << 0)) { |
| 86 | + __HAL_RCC_TIM1_CLK_ENABLE(); |
| 87 | + } |
| 88 | + #endif |
| 89 | + #ifdef TIM2 |
| 90 | + if (mask & (1 << 1)) { |
| 91 | + __HAL_RCC_TIM2_CLK_ENABLE(); |
| 92 | + } |
| 93 | + #endif |
| 94 | + #ifdef TIM3 |
| 95 | + if (mask & (1 << 2)) { |
| 96 | + __HAL_RCC_TIM3_CLK_ENABLE(); |
| 97 | + } |
| 98 | + #endif |
| 99 | + #ifdef TIM4 |
| 100 | + if (mask & (1 << 3)) { |
| 101 | + __HAL_RCC_TIM4_CLK_ENABLE(); |
| 102 | + } |
| 103 | + #endif |
| 104 | + #ifdef TIM5 |
| 105 | + if (mask & (1 << 4)) { |
| 106 | + __HAL_RCC_TIM5_CLK_ENABLE(); |
| 107 | + } |
| 108 | + #endif |
| 109 | + //6 and 7 are reserved ADC timers |
| 110 | + #ifdef TIM8 |
| 111 | + if (mask & (1 << 7)) { |
| 112 | + __HAL_RCC_TIM8_CLK_ENABLE(); |
| 113 | + } |
| 114 | + #endif |
| 115 | + #ifdef TIM9 |
| 116 | + if (mask & (1 << 8)) { |
| 117 | + __HAL_RCC_TIM9_CLK_ENABLE(); |
| 118 | + } |
| 119 | + #endif |
| 120 | + #ifdef TIM10 |
| 121 | + if (mask & (1 << 9)) { |
| 122 | + __HAL_RCC_TIM10_CLK_ENABLE(); |
| 123 | + } |
| 124 | + #endif |
| 125 | + #ifdef TIM11 |
| 126 | + if (mask & (1 << 10)) { |
| 127 | + __HAL_RCC_TIM11_CLK_ENABLE(); |
| 128 | + } |
| 129 | + #endif |
| 130 | + #ifdef TIM12 |
| 131 | + if (mask & (1 << 11)) { |
| 132 | + __HAL_RCC_TIM12_CLK_ENABLE(); |
| 133 | + } |
| 134 | + #endif |
| 135 | + #ifdef TIM13 |
| 136 | + if (mask & (1 << 12)) { |
| 137 | + __HAL_RCC_TIM13_CLK_ENABLE(); |
| 138 | + } |
| 139 | + #endif |
| 140 | + #ifdef TIM14 |
| 141 | + if (mask & (1 << 13)) { |
| 142 | + __HAL_RCC_TIM14_CLK_ENABLE(); |
| 143 | + } |
| 144 | + #endif |
| 145 | +} |
| 146 | + |
| 147 | +STATIC void tim_clock_disable(uint16_t mask) { |
| 148 | + #ifdef TIM1 |
| 149 | + if (mask & (1 << 0)) { |
| 150 | + __HAL_RCC_TIM1_CLK_DISABLE(); |
| 151 | + } |
| 152 | + #endif |
| 153 | + #ifdef TIM2 |
| 154 | + if (mask & (1 << 1)) { |
| 155 | + __HAL_RCC_TIM2_CLK_DISABLE(); |
| 156 | + } |
| 157 | + #endif |
| 158 | + #ifdef TIM3 |
| 159 | + if (mask & (1 << 2)) { |
| 160 | + __HAL_RCC_TIM3_CLK_DISABLE(); |
| 161 | + } |
| 162 | + #endif |
| 163 | + #ifdef TIM4 |
| 164 | + if (mask & (1 << 3)) { |
| 165 | + __HAL_RCC_TIM4_CLK_DISABLE(); |
| 166 | + } |
| 167 | + #endif |
| 168 | + #ifdef TIM5 |
| 169 | + if (mask & (1 << 4)) { |
| 170 | + __HAL_RCC_TIM5_CLK_DISABLE(); |
| 171 | + } |
| 172 | + #endif |
| 173 | + //6 and 7 are reserved ADC timers |
| 174 | + #ifdef TIM8 |
| 175 | + if (mask & (1 << 7)) { |
| 176 | + __HAL_RCC_TIM8_CLK_DISABLE(); |
| 177 | + } |
| 178 | + #endif |
| 179 | + #ifdef TIM9 |
| 180 | + if (mask & (1 << 8)) { |
| 181 | + __HAL_RCC_TIM9_CLK_DISABLE(); |
| 182 | + } |
| 183 | + #endif |
| 184 | + #ifdef TIM10 |
| 185 | + if (mask & (1 << 9)) { |
| 186 | + __HAL_RCC_TIM10_CLK_DISABLE(); |
| 187 | + } |
| 188 | + #endif |
| 189 | + #ifdef TIM11 |
| 190 | + if (mask & (1 << 10)) { |
| 191 | + __HAL_RCC_TIM11_CLK_DISABLE(); |
| 192 | + } |
| 193 | + #endif |
| 194 | + #ifdef TIM12 |
| 195 | + if (mask & (1 << 11)) { |
| 196 | + __HAL_RCC_TIM12_CLK_DISABLE(); |
| 197 | + } |
| 198 | + #endif |
| 199 | + #ifdef TIM13 |
| 200 | + if (mask & (1 << 12)) { |
| 201 | + __HAL_RCC_TIM13_CLK_DISABLE(); |
| 202 | + } |
| 203 | + #endif |
| 204 | + #ifdef TIM14 |
| 205 | + if (mask & (1 << 13)) { |
| 206 | + __HAL_RCC_TIM14_CLK_DISABLE(); |
| 207 | + } |
| 208 | + #endif |
| 209 | +} |
| 210 | + |
| 211 | +STATIC void callback_router(size_t index) { |
| 212 | + if (stm_timer_callback[index]) { |
| 213 | + (*stm_timer_callback[index])(); |
| 214 | + } |
| 215 | +} |
| 216 | + |
| 217 | +void TIM1_CC_IRQHandler(void) { // Advanced timer |
| 218 | + callback_router(1); |
| 219 | +} |
| 220 | +void TIM2_IRQHandler(void) { |
| 221 | + callback_router(2); |
| 222 | +} |
| 223 | +void TIM3_IRQHandler(void) { |
| 224 | + callback_router(3); |
| 225 | +} |
| 226 | +void TIM4_IRQHandler(void) { |
| 227 | + callback_router(4); |
| 228 | +} |
| 229 | +void TIM5_IRQHandler(void) { |
| 230 | + callback_router(5); |
| 231 | +} |
| 232 | +void TIM6_DAC_IRQHandler(void) { // Basic timer (DAC) |
| 233 | + callback_router(6); |
| 234 | +} |
| 235 | +void TIM7_IRQHandler(void) { // Basic timer |
| 236 | + callback_router(7); |
| 237 | +} |
| 238 | +void TIM8_CC_IRQHandler(void) { // Advanced timer |
| 239 | + callback_router(8); |
| 240 | +} |
| 241 | + |
| 242 | +// Advanced timer interrupts are currently unused. |
| 243 | +void TIM1_BRK_TIM9_IRQHandler(void) { |
| 244 | + callback_router(9); |
| 245 | +} |
| 246 | +void TIM1_UP_TIM10_IRQHandler(void) { |
| 247 | + callback_router(10); |
| 248 | +} |
| 249 | +void TIM1_TRG_COM_TIM11_IRQHandler(void) { |
| 250 | + callback_router(11); |
| 251 | +} |
| 252 | +void TIM8_BRK_TIM12_IRQHandler(void) { |
| 253 | + callback_router(12); |
| 254 | +} |
| 255 | +void TIM8_UP_TIM13_IRQHandler(void) { |
| 256 | + callback_router(13); |
| 257 | +} |
| 258 | +void TIM8_TRG_COM_TIM14_IRQHandler(void) { |
| 259 | + callback_router(14); |
| 260 | +} |
| 261 | + |
| 262 | +#if (CPY_STM32H7) |
| 263 | +void TIM15_IRQHandler(void) { |
| 264 | + callback_router(15); |
| 265 | +} |
| 266 | +void TIM16_IRQHandler(void) { |
| 267 | + callback_router(16); |
| 268 | +} |
| 269 | +void TIM17_IRQHandler(void) { |
| 270 | + callback_router(17); |
| 271 | +} |
| 272 | +#endif |
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