Merge pull request #634 from dhalbert/3.0_UART

Implement UART for 3.0 + related fixes.

Author: kattni

ports/atmel-samd/Makefile

@@ -36,6 +36,7 @@ INC += -I. \
        -Iasf4/$(CHIP_FAMILY)/hal/utils/include \
        -Iasf4/$(CHIP_FAMILY)/hri \
        -Iasf4/$(CHIP_FAMILY)/hpl/core \
+       -Iasf4/$(CHIP_FAMILY)/hpl/gclk \
        -Iasf4/$(CHIP_FAMILY)/hpl/pm \
        -Iasf4/$(CHIP_FAMILY)/hpl/port \
        -Iasf4/$(CHIP_FAMILY)/hpl/tc \
@@ -96,6 +97,7 @@ ifeq ($(DEBUG), 1)
   # Turn on Python modules useful for debugging (e.g. uheap, ustack).
   CFLAGS += -ggdb
   CFLAGS += -flto
+  ## CFLAGS += -fno-inline
   ifeq ($(CHIP_FAMILY), samd21)
     CFLAGS += -DENABLE_MICRO_TRACE_BUFFER
   endif
@@ -178,6 +180,7 @@ SRC_ASF := \
 	hal/src/hal_sleep.c \
 	hal/src/hal_spi_m_sync.c \
 	hal/src/hal_timer.c \
+	hal/src/hal_usart_async.c \
 	hal/src/hal_usb_device.c \
 	hpl/adc/hpl_adc.c \
 	hpl/core/hpl_init.c \
@@ -194,6 +197,7 @@ SRC_ASF := \
 	usb/device/usbdc.c \
 	usb/usb_protocol.c \
 	hal/utils/src/utils_list.c \
+	hal/utils/src/utils_ringbuffer.c \
 
 ifeq ($(CHIP_FAMILY), samd21)
 SRC_ASF += \
@@ -263,6 +267,7 @@ SRC_COMMON_HAL = \
 	busio/__init__.c \
 	busio/I2C.c \
 	busio/SPI.c \
+	busio/UART.c \
 	digitalio/__init__.c \
 	digitalio/DigitalInOut.c \
 	microcontroller/__init__.c \
@@ -283,7 +288,6 @@ SRC_COMMON_HAL = \
 	audiobusio/PDMIn.c \
 	audioio/__init__.c \
 	audioio/AudioOut.c \
-	busio/UART.c \
 	nvm/__init__.c \
 	nvm/ByteArray.c \
 	touchio/__init__.c \

ports/atmel-samd/asf4

@@ -1,3 +1,14 @@
+// Circuit Python SAMD21 clock tree:
+// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK0
+//   GCLK0 (48MHz) -> peripherals
+
+// We'd like to use XOSC32K as a ref for DFLL48M on boards with a 32kHz crystal,
+// but haven't figured that out yet.
+
+// Used in hpl/core/hpl_init.c to define which clocks should be initialized first.
+#define CIRCUITPY_GCLK_INIT_1ST (1 << 0)
+
+
 /* Auto-generated config file hpl_gclk_config.h */
 #ifndef HPL_GCLK_CONFIG_H
 #define HPL_GCLK_CONFIG_H

ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h

@@ -3,14 +3,16 @@
 //
 // SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous
 // SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous
-// SERCOM2: USART with hal_usart_sync.c driver: usart synchronous
+// SERCOM2: USART with hal_usart_async.c driver: usart asynchronous
+// SERCOM3: SPI with hal_spi_m_dma.c: spi master DMA
 
 #define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0
 #define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY
 
 #define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1
-#define PROTOTYPE_SERCOM_USART_SYNC SERCOM2
 
+#define PROTOTYPE_SERCOM_USART_ASYNC SERCOM2
+#define PROTOTYPE_SERCOM_USART_ASYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM2_CORE_FREQUENCY
 
 /* Auto-generated config file hpl_sercom_config.h */
 #ifndef HPL_SERCOM_CONFIG_H
@@ -543,6 +545,188 @@
 #endif
 #endif
 
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_3_SPI_ENABLE
+#define CONF_SERCOM_3_SPI_ENABLE 1
+#endif
+
+//<o> SPI DMA TX Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_tx_channel
+#ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0
+#endif
+
+// <e> SPI RX Channel Enable
+// <id> spi_master_rx_channel
+#ifndef CONF_SERCOM_3_SPI_RX_CHANNEL
+#define CONF_SERCOM_3_SPI_RX_CHANNEL 1
+#endif
+
+//<o> DMA Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_rx_channel
+#ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1
+#endif
+
+// </e>
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_3_SPI_MODE
+#define CONF_SERCOM_3_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_3_SPI_RXEN
+#define CONF_SERCOM_3_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_3_SPI_CHSIZE
+#define CONF_SERCOM_3_SPI_CHSIZE 0x0
+#endif
+
+// <o> Baud rate <1-12000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_3_SPI_BAUD
+#define CONF_SERCOM_3_SPI_BAUD 50000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_3_SPI_ADVANCED
+#define CONF_SERCOM_3_SPI_ADVANCED 0
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE
+#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_3_SPI_DORD
+#define CONF_SERCOM_3_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_3_SPI_CPOL
+#define CONF_SERCOM_3_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_3_SPI_CPHA
+#define CONF_SERCOM_3_SPI_CPHA 0x0
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_3_SPI_IBON
+#define CONF_SERCOM_3_SPI_IBON 0x0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_3_SPI_RUNSTDBY
+#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_3_SPI_DBGSTOP
+#define CONF_SERCOM_3_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_3_SPI_AMODE_EN
+#define CONF_SERCOM_3_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_AMODE
+#define CONF_SERCOM_3_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_ADDR
+#define CONF_SERCOM_3_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_ADDRMASK
+#define CONF_SERCOM_3_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_SSDE
+#define CONF_SERCOM_3_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_MSSEN
+#define CONF_SERCOM_3_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_PLOADEN
+#define CONF_SERCOM_3_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_3_SPI_RXPO
+#define CONF_SERCOM_3_SPI_RXPO 0
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_3_SPI_TXPO
+#define CONF_SERCOM_3_SPI_TXPO 1
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_3_SPI_BAUD_RATE
+#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1
+#endif
+
 // <<< end of configuration section >>>
 
 #endif // HPL_SERCOM_CONFIG_H