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26 | 26 | #define GPIO4_PIN_MASK 0x00000003 |
27 | 27 | #define GPIO4_RESET_MASK 0xFFFFFF77 |
28 | 28 | #define GPIO4_OUTEN_MASK(mask) \ |
29 | | - (((mask & (1 << 0)) << MXC_F_MCR_GPIO4_CTRL_P40_OE_POS) | \ |
| 29 | + (((mask & (1 << 0)) << MXC_F_MCR_GPIO4_CTRL_P40_OE_POS) | \ |
30 | 30 | ((mask & (1 << 1)) << (MXC_F_MCR_GPIO4_CTRL_P41_OE_POS - 1))) |
31 | 31 | #define GPIO4_PULLDIS_MASK(mask) \ |
32 | | - (((mask & (1 << 0)) << MXC_F_MCR_GPIO4_CTRL_P40_PE_POS) | \ |
| 32 | + (((mask & (1 << 0)) << MXC_F_MCR_GPIO4_CTRL_P40_PE_POS) | \ |
33 | 33 | ((mask & (1 << 1)) << (MXC_F_MCR_GPIO4_CTRL_P41_PE_POS - 1))) |
34 | 34 | #define GPIO4_DATAOUT_MASK(mask) \ |
35 | | - (((mask & (1 << 0)) << MXC_F_MCR_GPIO4_CTRL_P40_DO_POS) | \ |
| 35 | + (((mask & (1 << 0)) << MXC_F_MCR_GPIO4_CTRL_P40_DO_POS) | \ |
36 | 36 | ((mask & (1 << 1)) << (MXC_F_MCR_GPIO4_CTRL_P41_DO_POS - 1))) |
37 | 37 | #define GPIO4_DATAOUT_GET_MASK(mask) \ |
38 | | - ((((MXC_MCR->gpio4_ctrl & MXC_F_MCR_GPIO4_CTRL_P40_DO) >> MXC_F_MCR_GPIO4_CTRL_P40_DO_POS) | \ |
| 38 | + ((((MXC_MCR->gpio4_ctrl & MXC_F_MCR_GPIO4_CTRL_P40_DO) >> MXC_F_MCR_GPIO4_CTRL_P40_DO_POS) | \ |
39 | 39 | ((MXC_MCR->gpio4_ctrl & MXC_F_MCR_GPIO4_CTRL_P41_DO) >> \ |
40 | | - (MXC_F_MCR_GPIO4_CTRL_P41_DO_POS - 1)))& \ |
| 40 | + (MXC_F_MCR_GPIO4_CTRL_P41_DO_POS - 1))) & \ |
41 | 41 | mask) |
42 | 42 | #define GPIO4_DATAIN_MASK(mask) \ |
43 | 43 | ((((MXC_MCR->gpio4_ctrl & MXC_F_MCR_GPIO4_CTRL_P40_IN) >> MXC_F_MCR_GPIO4_CTRL_P40_IN_POS) | \ |
44 | 44 | ((MXC_MCR->gpio4_ctrl & MXC_F_MCR_GPIO4_CTRL_P41_IN) >> \ |
45 | | - (MXC_F_MCR_GPIO4_CTRL_P41_IN_POS - 1)))& \ |
| 45 | + (MXC_F_MCR_GPIO4_CTRL_P41_IN_POS - 1))) & \ |
46 | 46 | mask) |
47 | 47 | #define GPIO4_AFEN_MASK(mask) \ |
48 | | - (((mask & (1 << 0)) << MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS) | \ |
| 48 | + (((mask & (1 << 0)) << MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS) | \ |
49 | 49 | ((mask & (1 << 1)) >> (MXC_F_MCR_OUTEN_SQWOUT_EN_POS + 1))) |
50 | 50 | /** END: GPIO4 Handling specific to MAX32690 */ |
51 | 51 |
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