Skip to content

Commit 82bae65

Browse files
iabdalkaderdpgeorge
iabdalkader
authored and
dpgeorge
committed
alif: Add support for pin alternate function selection.
Signed-off-by: iabdalkader <[email protected]>
1 parent 039df0c commit 82bae65

File tree

5 files changed

+242
-9
lines changed

5 files changed

+242
-9
lines changed

‎ports/alif/alif.mk

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ INC += -Itinyusb_port
5151
GEN_PIN_MKPINS = mcu/make-pins.py
5252
GEN_PIN_PREFIX = mcu/pins_prefix.c
5353
GEN_PINS_BOARD_CSV = $(BOARD_DIR)/pins.csv
54+
GEN_PINS_MCU_CSV = mcu/ensemble_pin_alt.csv
5455
GEN_PINS_SRC = $(BUILD)/pins_board.c
5556
GEN_PINS_HDR = $(HEADER_BUILD)/pins_board.h
5657

@@ -263,6 +264,7 @@ $(BUILD)/firmware.bin: $(BUILD)/firmware.elf
263264
$(BUILD)/%_board.c $(HEADER_BUILD)/%_board.h: $(BOARD_DIR)/%.csv $(GEN_PIN_MKPINS) $(GEN_PIN_PREFIX) | $(HEADER_BUILD)
264265
$(ECHO) "GEN $@"
265266
$(Q)$(PYTHON) $(GEN_PIN_MKPINS) \
267+
--af-csv $(GEN_PINS_MCU_CSV) \
266268
--board-csv $(GEN_PINS_BOARD_CSV) \
267269
--prefix $(GEN_PIN_PREFIX) \
268270
--output-source $(GEN_PINS_SRC) \

‎ports/alif/mcu/ensemble_pin_alt.csv

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,130 @@
1+
Pin,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7
2+
P0_0,,OSPI,UART,I3C,UT,LPCAM,CAM,ANA
3+
P0_1,,OSPI,UART,I3C,UT,LPCAM,CAM,ANA
4+
P0_2,,OSPI,UART,I2C,UT,LPCAM,CAM,ANA
5+
P0_3,,OSPI,UART,I2C,UT,LPCAM,CAM,ANA
6+
P0_4,,OSPI,UART,PDM,I2C,UT,,ANA
7+
P0_5,,OSPI,UART,PDM,I2C,UT,,ANA
8+
P0_6,,OSPI,UART,PDM,I2C,UT,,ANA
9+
P0_7,,OSPI,UART,PDM,I2C,UT,CDC,ANA
10+
P1_0,,UART,SPI,I2C,UT,LPCAM,ETH,ANA
11+
P1_1,,UART,SPI,I2C,UT,LPCAM,ETH,ANA
12+
P1_2,,UART,SPI,I3C,UT,LPCAM,ETH,ANA
13+
P1_3,,UART,SPI,I3C,UT,LPCAM,ETH,ANA
14+
P1_4,,OSPI,UART,SPI,UT,LPCAM,ETH,ANA
15+
P1_5,,OSPI,UART,SPI,UT,LPCAM,ETH,ANA
16+
P1_6,,OSPI,UART,I2S,UT,LPCAM,ETH,ANA
17+
P1_7,,OSPI,UART,I2S,UT,LPCAM,ETH,ANA
18+
P2_0,,OSPI,UART,LPPDM,UT,LPCAM,ETH,ANA
19+
P2_1,,OSPI,UART,LPPDM,UT,LPCAM,ETH,ANA
20+
P2_2,,OSPI,UART,LPPDM,UT,LPCAM,ETH,ANA
21+
P2_3,,OSPI,UART,LPPDM,UT,LPCAM,CDC,ANA
22+
P2_4,,OSPI,LPI2S,SPI,UT,LPCAM,CAM,ANA
23+
P2_5,,OSPI,LPI2S,SPI,UT,LPCAM,CAM,ANA
24+
P2_6,,OSPI,LPI2S,SPI,UT,LPCAM,CAM,ANA
25+
P2_7,,OSPI,LPI2S,SPI,UT,LPCAM,CAM,ANA
26+
P3_0,,OSPI,UART,PDM,I2S,QEC,LPCAM,CAM
27+
P3_1,,OSPI,UART,PDM,I2S,QEC,LPCAM,CAM
28+
P3_2,,OSPI,PDM,I2S,I3C,QEC,LPCAM,CAM
29+
P3_3,,OSPI,PDM,I2S,I3C,QEC,LPCAM,CAM
30+
P3_4,,OSPI,UART,LPPDM,I2S,I2C,QEC,CAM
31+
P3_5,,OSPI,UART,LPPDM,SPI,I2C,QEC,CAM
32+
P3_6,,HFXO,LPUART,LPPDM,SPI,I2C,QEC,CAM
33+
P3_7,,JTAG,LPUART,LPPDM,SPI,I2C,QEC,CAM
34+
P4_0,,JTAG,,I2S,SPI,QEC,CDC,CAM
35+
P4_1,,JTAG,I2S,SPI,QEC,SD,CDC,CAM
36+
P4_2,,JTAG,,I2S,SPI,QEC,SD,CAM
37+
P4_3,,JTAG,,I2S,SPI,QEC,SD,CAM
38+
P4_4,,JTAG,I2S,SPI,FAULT,,,
39+
P4_5,,JTAG,SPI,FAULT,,,,
40+
P4_6,,JTAG,SPI,FAULT,,,,
41+
P4_7,,JTAG,SPI,FAULT,,,,
42+
P5_0,,OSPI,UART,PDM,SPI,I2C,UT,SD
43+
P5_1,,OSPI,UART,PDM,SPI,I2C,UT,SD
44+
P5_2,,OSPI,UART,PDM,SPI,LPI2C,UT,SD
45+
P5_3,,OSPI,UART,SPI,LPI2C,UT,SD,CDC
46+
P5_4,,OSPI,UART,PDM,SPI,UT,SD,CDC
47+
P5_5,,OSPI,UART,PDM,UT,SD,ETH,CDC
48+
# P5_6 doesn't really have OSPI on AF1 but it's needed for P10_7 to be in OSPI mode
49+
P5_6,,OSPI,UART,I2C,UT,SD,ETH,CDC
50+
P5_7,,OSPI,UART,I2C,UT,SD,ETH,
51+
P6_0,,OSPI,UART,PDM,UT,SD,ETH,
52+
P6_1,,OSPI,UART,PDM,UT,SD,ETH,
53+
P6_2,,OSPI,UART,,PDM,UT,SD,ETH
54+
P6_3,,OSPI,UART,,PDM,UT,SD,ETH
55+
P6_4,,OSPI,UART,,SPI,UT,SD,ETH
56+
P6_5,,OSPI,UART,,SPI,UT,SD,ETH
57+
P6_6,,OSPI,UART,,SPI,UT,SD,ETH
58+
P6_7,,OSPI,UART,PDM,SPI,UT,SD,ETH
59+
P7_0,,,CMP,SPI,I2C,UT,SD,
60+
P7_1,,,CMP,SPI,I2C,UT,SD,
61+
P7_2,,,UART,CMP,SPI,I2C,UT,SD
62+
P7_3,,,UART,CMP,SPI,I2C,UT,
63+
P7_4,,,LPUART,LPPDM,LPSPI,LPI2C,UT,
64+
P7_5,,,LPUART,,LPPDM,LPSPI,LPI2C,UT
65+
P7_6,,,LPUART,,LPPDM,LPSPI,I3C,UT
66+
P7_7,,,LPUART,,LPPDM,LPSPI,I3C,UT
67+
P8_0,,OSPI,AUDIO,FAULT,LPCAM,SD,CDC,CAM
68+
P8_1,,I2S,FAULT,LPCAM,SD,CDC,CAM,
69+
P8_2,,I2S,SPI,FAULT,LPCAM,SD,CDC,CAM
70+
P8_3,,I2S,SPI,FAULT,LPCAM,SD,CDC,CAM
71+
P8_4,,I2S,SPI,QEC,LPCAM,SD,CDC,CAM
72+
P8_5,,,SPI,QEC,LPCAM,SD,CDC,CAM
73+
P8_6,,,I2S,QEC,LPCAM,SD,CDC,CAM
74+
P8_7,,,I2S,QEC,LPCAM,SD,CDC,CAM
75+
P9_0,,,I2S,QEC,SD,CDC,CAM,
76+
P9_1,,LPUART,I2S,QEC,SD,CDC,CAM,
77+
P9_2,,LPUART,I2S,SPI,QEC,SD,CDC,CAM
78+
P9_3,,HFXO,UART,I2S,SPI,QEC,CDC,CAM
79+
P9_4,,UART,I2S,SPI,I2C,QEC,CDC,CAM
80+
P9_5,,OSPI,I2S,SPI,I2C,QEC,CDC,CAM
81+
P9_6,,OSPI,AUDIO,SPI,I2C,QEC,CDC,CAM
82+
P9_7,,OSPI,UART,SPI,I2C,QEC,CDC,CAM
83+
P10_0,,OSPI,UART,SPI,UT,LPCAM,CDC,CAM
84+
P10_1,,OSPI,,LPI2S,UT,LPCAM,CDC,CAM
85+
P10_2,,OSPI,,LPI2S,UT,LPCAM,CDC,CAM
86+
P10_3,,OSPI,,LPI2S,UT,LPCAM,CDC,CAM
87+
P10_4,,OSPI,,LPI2S,I2C,UT,ETH,CDC
88+
P10_5,,UART,I2S,SPI,I2C,UT,ETH,CDC
89+
P10_6,,UART,I2S,SPI,I2C,UT,ETH,CDC
90+
P10_7,,UART,I2S,SPI,I2C,UT,CDC,OSPI
91+
P11_0,,OSPI,UART,I2S,SPI,UT,ETH,CDC
92+
P11_1,,OSPI,UART,SPI,UT,ETH,CDC,
93+
P11_2,,OSPI,UART,LPPDM,SPI,UT,ETH,CDC
94+
P11_3,,OSPI,UART,LPPDM,SPI,UT,ETH,CDC
95+
P11_4,,OSPI,UART,PDM,LPSPI,UT,ETH,CDC
96+
P11_5,,OSPI,UART,PDM,LPSPI,UT,ETH,CDC
97+
P11_6,,OSPI,UART,LPPDM,LPSPI,UT,ETH,CDC
98+
P11_7,,OSPI,UART,LPPDM,LPSPI,UT,ETH,CDC
99+
P12_0,,OSPI,AUDIO,I2S,UT,CDC,,
100+
P12_1,,OSPI,UART,I2S,UT,CDC,,
101+
P12_2,,OSPI,UART,I2S,UT,CDC,,
102+
P12_3,,OSPI,UART,I2S,UT,CDC,,
103+
P12_4,,OSPI,SPI,UT,,CDC,,
104+
P12_5,,,SPI,UT,,CDC,,
105+
P12_6,,,SPI,UT,,CDC,,
106+
P12_7,,OSPI,,SPI,UT,CDC,,
107+
P13_0,,OSPI,,SPI,QEC,SD,CDC,
108+
P13_1,,OSPI,SPI,QEC,SD,CDC,,
109+
P13_2,,OSPI,SPI,QEC,SD,CDC,,
110+
P13_3,,OSPI,SPI,QEC,SD,CDC,,
111+
P13_4,,OSPI,LPI2S,QEC,SD,CDC,,
112+
P13_5,,OSPI,LPI2S,QEC,SD,CDC,,
113+
P13_6,,OSPI,LPI2S,QEC,SD,CDC,,
114+
P13_7,,OSPI,LPI2S,QEC,SD,CDC,,
115+
P14_0,,OSPI,UART,QEC,SD,,,
116+
P14_1,,OSPI,UART,,QEC,SD,,
117+
P14_2,,OSPI,UART,,QEC,SD,,
118+
P14_3,,OSPI,UART,,QEC,,,
119+
P14_4,,CMP,SPI,FAULT,,,,
120+
P14_5,,CMP,SPI,FAULT,,,,
121+
P14_6,,CMP,SPI,FAULT,,,,
122+
P14_7,,CMP,SPI,FAULT,,,,
123+
P15_0,,LPTMR,,,,,,
124+
P15_1,,LPTMR,,,,,,
125+
P15_2,,LPTMR,,,,,,
126+
P15_3,,LPTMR,,,,,,
127+
P15_4,,,,,,,,
128+
P15_5,,,,,,,,
129+
P15_6,,,,,,,,
130+
P15_7,,,,,,,,

‎ports/alif/mcu/make-pins.py

Lines changed: 19 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -34,26 +34,36 @@
3434

3535

3636
class AlifPin(boardgen.Pin):
37+
def __init__(self, cpu_pin_name):
38+
super().__init__(cpu_pin_name)
39+
self._afs = ["MP_HAL_PIN_ALT_NONE"] * 8
40+
41+
# Called for each AF defined in the csv file for this pin.
42+
def add_af(self, af_idx, af_name, af):
43+
self._afs[af_idx] = f"MP_HAL_PIN_ALT_{af}"
44+
3745
# Emit the struct which contains the pin instance.
3846
def definition(self):
3947
port, pin = self.name()[1:].split("_")
4048
adc12_periph, adc12_channel = ADC12_ANA_MAP.get(self.name(), (3, 7))
4149
base = "LPGPIO_BASE" if port == "15" else "GPIO{}_BASE".format(port)
4250
return (
43-
"{{ "
44-
".base = {{ .type = &machine_pin_type }}, "
45-
".gpio = (GPIO_Type *){base}, "
46-
".port = PORT_{port}, "
47-
".pin = PIN_{pin}, "
48-
".adc12_periph = {adc12_periph}, "
49-
".adc12_channel = {adc12_channel}, "
50-
".name = MP_QSTR_P{port}_{pin} "
51+
"{{\n"
52+
" .name = MP_QSTR_P{port}_{pin},\n"
53+
" .base = {{ .type = &machine_pin_type }},\n"
54+
" .gpio = (GPIO_Type *){base},\n"
55+
" .port = PORT_{port},\n"
56+
" .pin = PIN_{pin},\n"
57+
" .adc12_periph = {adc12_periph},\n"
58+
" .adc12_channel = {adc12_channel},\n"
59+
" .alt = {{{alt}}},\n"
5160
"}}".format(
5261
port=port,
5362
pin=pin,
5463
base=base,
5564
adc12_periph=adc12_periph,
5665
adc12_channel=adc12_channel,
66+
alt=", ".join([f"{af}" for af in self._afs]),
5767
)
5868
)
5969

@@ -76,7 +86,7 @@ def validate_cpu_pin_name(cpu_pin_name):
7686
class AlifPinGenerator(boardgen.PinGenerator):
7787
def __init__(self):
7888
# Use custom pin type above.
79-
super().__init__(pin_type=AlifPin)
89+
super().__init__(pin_type=AlifPin, enable_af=True)
8090

8191
# Pre-define the pins (i.e. don't require them to be listed in pins.csv).
8292
for i in range(NUM_PORTS):

‎ports/alif/mphalport.c

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -169,6 +169,56 @@ uint64_t mp_hal_time_ns(void) {
169169
return 0;
170170
}
171171

172+
void mp_hal_pin_config(const machine_pin_obj_t *pin, uint32_t mode,
173+
uint32_t pull, uint32_t speed, uint32_t drive, uint32_t alt, bool ren) {
174+
uint8_t alt_func = PINMUX_ALTERNATE_FUNCTION_0;
175+
uint8_t pad_ctrl = drive | speed | (ren ? PADCTRL_READ_ENABLE : 0);
176+
177+
// Configure pull-up or pull-down.
178+
if (pull & MP_HAL_PIN_PULL_UP) {
179+
pad_ctrl |= PADCTRL_DRIVER_DISABLED_PULL_UP;
180+
}
181+
182+
if (pull & MP_HAL_PIN_PULL_DOWN) {
183+
pad_ctrl |= PADCTRL_DRIVER_DISABLED_PULL_DOWN;
184+
}
185+
186+
// Configure open-drain mode.
187+
if (mode == MP_HAL_PIN_MODE_OPEN_DRAIN) {
188+
pad_ctrl |= PADCTRL_DRIVER_OPEN_DRAIN;
189+
}
190+
191+
// For ALT mode, find alternate function.
192+
if (mode == MP_HAL_PIN_MODE_ALT) {
193+
for (mp_uint_t i = 0; i < MP_ARRAY_SIZE(pin->alt); i++) {
194+
if (alt == pin->alt[i]) {
195+
alt_func = i;
196+
break;
197+
}
198+
}
199+
if (alt_func == PINMUX_ALTERNATE_FUNCTION_0) {
200+
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid pin af: %d"), alt);
201+
}
202+
}
203+
204+
// Set pad config.
205+
pinconf_set(pin->port, pin->pin, alt_func, pad_ctrl);
206+
207+
// For INPUT/OUTPUT/OD modes, set the GPIO direction.
208+
switch (mode) {
209+
case MP_HAL_PIN_MODE_INPUT:
210+
gpio_set_direction_input(pin->gpio, pin->pin);
211+
break;
212+
case MP_HAL_PIN_MODE_OUTPUT:
213+
case MP_HAL_PIN_MODE_OPEN_DRAIN:
214+
gpio_set_direction_output(pin->gpio, pin->pin);
215+
break;
216+
default:
217+
break;
218+
}
219+
}
220+
221+
172222
void system_tick_schedule_callback(void) {
173223
pendsv_schedule_dispatch(PENDSV_DISPATCH_SOFT_TIMER, soft_timer_handler);
174224
}

‎ports/alif/mphalport.h

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,12 +74,49 @@ extern ringbuf_t stdin_ringbuf;
7474
#define MP_HAL_PIN_MODE_INPUT (0)
7575
#define MP_HAL_PIN_MODE_OUTPUT (1)
7676
#define MP_HAL_PIN_MODE_OPEN_DRAIN (2)
77+
#define MP_HAL_PIN_MODE_ALT (3)
7778
#define MP_HAL_PIN_PULL_NONE (0)
7879
#define MP_HAL_PIN_PULL_UP (1)
7980
#define MP_HAL_PIN_PULL_DOWN (2)
81+
#define MP_HAL_PIN_DRIVE_2MA (PADCTRL_OUTPUT_DRIVE_STRENGTH_2MA)
82+
#define MP_HAL_PIN_DRIVE_4MA (PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA)
83+
#define MP_HAL_PIN_DRIVE_8MA (PADCTRL_OUTPUT_DRIVE_STRENGTH_8MA)
84+
#define MP_HAL_PIN_DRIVE_12MA (PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA)
85+
#define MP_HAL_PIN_SPEED_LOW (0)
86+
#define MP_HAL_PIN_SPEED_HIGH (PADCTRL_SLEW_RATE_FAST)
8087

8188
#define mp_hal_pin_obj_t const machine_pin_obj_t *
8289

90+
enum {
91+
MP_HAL_PIN_ALT_NONE = 0,
92+
MP_HAL_PIN_ALT_ANA,
93+
MP_HAL_PIN_ALT_AUDIO,
94+
MP_HAL_PIN_ALT_CAM,
95+
MP_HAL_PIN_ALT_CDC,
96+
MP_HAL_PIN_ALT_CMP,
97+
MP_HAL_PIN_ALT_ETH,
98+
MP_HAL_PIN_ALT_FAULT,
99+
MP_HAL_PIN_ALT_HFXO,
100+
MP_HAL_PIN_ALT_I2C,
101+
MP_HAL_PIN_ALT_I2S,
102+
MP_HAL_PIN_ALT_I3C,
103+
MP_HAL_PIN_ALT_JTAG,
104+
MP_HAL_PIN_ALT_LPCAM,
105+
MP_HAL_PIN_ALT_LPI2C,
106+
MP_HAL_PIN_ALT_LPI2S,
107+
MP_HAL_PIN_ALT_LPPDM,
108+
MP_HAL_PIN_ALT_LPSPI,
109+
MP_HAL_PIN_ALT_LPTMR,
110+
MP_HAL_PIN_ALT_LPUART,
111+
MP_HAL_PIN_ALT_OSPI,
112+
MP_HAL_PIN_ALT_PDM,
113+
MP_HAL_PIN_ALT_QEC,
114+
MP_HAL_PIN_ALT_SD,
115+
MP_HAL_PIN_ALT_SPI,
116+
MP_HAL_PIN_ALT_UART,
117+
MP_HAL_PIN_ALT_UT,
118+
};
119+
83120
typedef struct _machine_pin_obj_t {
84121
mp_obj_base_t base;
85122
GPIO_Type *gpio;
@@ -88,6 +125,7 @@ typedef struct _machine_pin_obj_t {
88125
uint8_t adc12_periph : 2;
89126
uint8_t adc12_channel : 3;
90127
qstr name;
128+
const uint8_t alt[8];
91129
} machine_pin_obj_t;
92130

93131
mp_hal_pin_obj_t mp_hal_get_pin_obj(mp_obj_t pin_in);
@@ -149,5 +187,8 @@ static inline void mp_hal_wake_main_task_from_isr(void) {
149187
// Defined for tinyusb support, nothing needs to be done here.
150188
}
151189

190+
void mp_hal_pin_config(const machine_pin_obj_t *pin, uint32_t mode,
191+
uint32_t pull, uint32_t speed, uint32_t drive, uint32_t alt, bool ren);
192+
152193
// Include all the pin definitions.
153194
#include "genhdr/pins_board.h"

0 commit comments

Comments
 (0)