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| 1 | +/* |
| 2 | + * This file is part of the MicroPython project, http://micropython.org/ |
| 3 | + * |
| 4 | + * The MIT License (MIT) |
| 5 | + * |
| 6 | + * Copyright (c) 2020 microDev |
| 7 | + * Copyright (c) 2023 Bob Abeles |
| 8 | + * |
| 9 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 10 | + * of this software and associated documentation files (the "Software"), to deal |
| 11 | + * in the Software without restriction, including without limitation the rights |
| 12 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 13 | + * copies of the Software, and to permit persons to whom the Software is |
| 14 | + * furnished to do so, subject to the following conditions: |
| 15 | + * |
| 16 | + * The above copyright notice and this permission notice shall be included in |
| 17 | + * all copies or substantial portions of the Software. |
| 18 | + * |
| 19 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 20 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 21 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 22 | + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 23 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 24 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 25 | + * THE SOFTWARE. |
| 26 | + */ |
| 27 | + |
| 28 | +#include <string.h> |
| 29 | + |
| 30 | +#include "shared-bindings/memorymap/AddressRange.h" |
| 31 | + |
| 32 | +#include "py/runtime.h" |
| 33 | + |
| 34 | +#include "hardware/regs/addressmap.h" |
| 35 | + |
| 36 | +// RP2 address map ranges, must be arranged in order by ascending start address |
| 37 | +addressmap_rp2_range_t rp2_ranges[] = { |
| 38 | + {(uint8_t *)ROM_BASE, 0x00004000, ROM}, // boot ROM |
| 39 | + {(uint8_t *)XIP_BASE, 0x00100000, XIP}, // XIP normal cache operation |
| 40 | + {(uint8_t *)XIP_NOALLOC_BASE, 0x00100000, XIP}, // XIP check for hit, no update on miss |
| 41 | + {(uint8_t *)XIP_NOCACHE_BASE, 0x00100000, XIP}, // XIP don't check for hit, no update on miss |
| 42 | + {(uint8_t *)XIP_NOCACHE_NOALLOC_BASE, 0x00100000, XIP}, // XIP bypass cache completely |
| 43 | + {(uint8_t *)XIP_CTRL_BASE, 0x00004000, IO}, // XIP control registers |
| 44 | + {(uint8_t *)XIP_SRAM_BASE, 0x00004000, SRAM}, // XIP SRAM 16KB XIP cache |
| 45 | + {(uint8_t *)XIP_SSI_BASE, 0x00004000, IO}, // XIP SSI registers |
| 46 | + {(uint8_t *)SRAM_BASE, 0x00042000, SRAM}, // SRAM 256KB striped plus 16KB contiguous |
| 47 | + {(uint8_t *)SRAM0_BASE, 0x00040000, SRAM}, // SRAM0 to SRAM3 256KB non-striped |
| 48 | + {(uint8_t *)SYSINFO_BASE, 0x00070000, IO}, // APB peripherals |
| 49 | + {(uint8_t *)DMA_BASE, 0x00004000, IO}, // DMA registers |
| 50 | + {(uint8_t *)USBCTRL_DPRAM_BASE, 0x00001000, SRAM}, // USB DPSRAM 4KB |
| 51 | + {(uint8_t *)USBCTRL_REGS_BASE, 0x00004000, IO}, // USB registers |
| 52 | + {(uint8_t *)PIO0_BASE, 0x00004000, IO}, // PIO0 registers |
| 53 | + {(uint8_t *)PIO1_BASE, 0x00004000, IO}, // PIO1 registers |
| 54 | + {(uint8_t *)SIO_BASE, 0x00001000, IO}, // SIO registers, no aliases |
| 55 | + {(uint8_t *)PPB_BASE, 0x00004000, IO} // PPB registers |
| 56 | +}; |
| 57 | + |
| 58 | +void common_hal_memorymap_addressrange_construct(memorymap_addressrange_obj_t *self, |
| 59 | + uint8_t *start_address, size_t length) { |
| 60 | + for (size_t i = 0; i < MP_ARRAY_SIZE(rp2_ranges); i++) { |
| 61 | + if (start_address <= rp2_ranges[i].start_address) { |
| 62 | + uint8_t *range_end_address = rp2_ranges[i].start_address + rp2_ranges[i].len - 1; |
| 63 | + uint8_t *end_address = start_address + length - 1; |
| 64 | + if (start_address > range_end_address || end_address > range_end_address) { |
| 65 | + break; |
| 66 | + } |
| 67 | + self->start_address = start_address; |
| 68 | + self->len = length; |
| 69 | + self->type = rp2_ranges[i].type; |
| 70 | + return; |
| 71 | + } |
| 72 | + } |
| 73 | + |
| 74 | + mp_raise_ValueError(translate("Address range not allowed")); |
| 75 | +} |
| 76 | + |
| 77 | +size_t common_hal_memorymap_addressrange_get_length(const memorymap_addressrange_obj_t *self) { |
| 78 | + return self->len; |
| 79 | +} |
| 80 | + |
| 81 | +void common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_obj_t *self, |
| 82 | + size_t start_index, uint8_t *values, size_t len) { |
| 83 | + uint8_t *dest_addr = self->start_address + start_index; |
| 84 | + switch (self->type) { |
| 85 | + case SRAM: |
| 86 | + // Writes to SRAM may be arbitrary length and alignment. We use memcpy() which |
| 87 | + // may optimize aligned writes depending on CIRCUITPY_FULL_BUILD of the CP build. |
| 88 | + memcpy(dest_addr, values, len); |
| 89 | + break; |
| 90 | + case IO: |
| 91 | + if ((size_t)dest_addr & 0x03 || len & 0x03) { |
| 92 | + // Unaligned access or unaligned length not supported by RP2 for IO registers |
| 93 | + mp_raise_RuntimeError(translate("Unable to access unaligned IO register")); |
| 94 | + } else { |
| 95 | + // Aligned access and length, use 32-bit writes |
| 96 | + uint32_t *dest_addr32 = (uint32_t *)dest_addr; |
| 97 | + size_t access_count = len >> 2; |
| 98 | + for (size_t i = 0; i < access_count; i++) { |
| 99 | + *dest_addr32++ = ((uint32_t *)values)[i]; |
| 100 | + } |
| 101 | + } |
| 102 | + break; |
| 103 | + case XIP: |
| 104 | + case ROM: |
| 105 | + // XIP and ROM are read-only |
| 106 | + mp_raise_RuntimeError(translate("Unable to write to read-only memory")); |
| 107 | + break; |
| 108 | + } |
| 109 | +} |
| 110 | + |
| 111 | +void common_hal_memorymap_addressrange_get_bytes(const memorymap_addressrange_obj_t *self, |
| 112 | + size_t start_index, size_t len, uint8_t *values) { |
| 113 | + uint8_t *src_addr = self->start_address + start_index; |
| 114 | + switch (self->type) { |
| 115 | + case SRAM: |
| 116 | + case XIP: |
| 117 | + case ROM: |
| 118 | + // Reads from these sources may be arbitrary length and alignment. We use memcpy() |
| 119 | + // which may optimize aligned writes depending on CIRCUITPY_FULL_BUILD of the CP build. |
| 120 | + memcpy(values, src_addr, len); |
| 121 | + break; |
| 122 | + case IO: |
| 123 | + if ((size_t)src_addr & 0x03 || len & 0x03) { |
| 124 | + // Unaligned access or unaligned length not supported by RP2 for IO registers |
| 125 | + mp_raise_RuntimeError(translate("Unable to access unaligned IO register")); |
| 126 | + } else { |
| 127 | + // Aligned access and length, use 32-bit reads |
| 128 | + uint32_t *src_addr32 = (uint32_t *)src_addr; |
| 129 | + size_t access_count = len >> 2; |
| 130 | + for (size_t i = 0; i < access_count; i++) { |
| 131 | + ((uint32_t *)values)[i] = *src_addr32++; |
| 132 | + } |
| 133 | + } |
| 134 | + break; |
| 135 | + } |
| 136 | +} |
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