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#endif
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static frequencyio_frequencyin_obj_t * active_frequencyins [TC_INST_NUM ];
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- volatile uint8_t reference_tc = 0xff ;
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+ volatile uint8_t reference_tc ;
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#ifdef SAM_D5X_E5X
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static uint8_t dpll_gclk ;
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#endif
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- void frequencyin_emergency_cancel_capture (uint8_t index ) {
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+ void frequencyin_reset (void ) {
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+ for (uint8_t i = 0 ; i < TC_INST_NUM ; i ++ ) {
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+ active_frequencyins [i ] = NULL ;
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+ }
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+
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+ reference_tc = 0xff ;
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+ #ifdef SAM_D5X_E5X
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+ dpll_gclk = 0xff ;
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+ #endif
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+ }
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+
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+ static void frequencyin_emergency_cancel_capture (uint8_t index ) {
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frequencyio_frequencyin_obj_t * self = active_frequencyins [index ];
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NVIC_DisableIRQ (self -> TC_IRQ );
@@ -93,7 +104,7 @@ void frequencyin_interrupt_handler(uint8_t index) {
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uint64_t current_ns = common_hal_time_monotonic_ns ();
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- for (uint8_t i = 0 ; i <= ( TC_INST_NUM - 1 ) ; i ++ ) {
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+ for (uint8_t i = 0 ; i < TC_INST_NUM ; i ++ ) {
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if (active_frequencyins [i ] != NULL ) {
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frequencyio_frequencyin_obj_t * self = active_frequencyins [i ];
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Tc * tc = tc_insts [self -> tc_index ];
@@ -143,7 +154,7 @@ void frequencyin_interrupt_handler(uint8_t index) {
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ref_tc -> COUNT16 .INTFLAG .reg |= TC_INTFLAG_OVF ;
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}
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- void frequencyin_reference_tc_init () {
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+ static void frequencyin_reference_tc_init (void ) {
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if (reference_tc == 0xff ) {
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return ;
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}
@@ -154,9 +165,6 @@ void frequencyin_reference_tc_init() {
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// use the DPLL we setup so that the reference_tc and freqin_tc(s)
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// are using the same clock frequency.
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#ifdef SAM_D5X_E5X
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- if (dpll_gclk == 0xff ) {
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- frequencyin_samd51_start_dpll ();
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- }
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set_timer_handler (true, reference_tc , TC_HANDLER_FREQUENCYIN );
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turn_on_clocks (true, reference_tc , dpll_gclk );
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#endif
@@ -178,15 +186,15 @@ void frequencyin_reference_tc_init() {
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#endif
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}
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- bool frequencyin_reference_tc_enabled () {
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+ static bool frequencyin_reference_tc_enabled (void ) {
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if (reference_tc == 0xff ) {
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return false;
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}
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Tc * tc = tc_insts [reference_tc ];
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return tc -> COUNT16 .CTRLA .bit .ENABLE ;
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}
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- void frequencyin_reference_tc_enable (bool enable ) {
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+ static void frequencyin_reference_tc_enable (bool enable ) {
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if (reference_tc == 0xff ) {
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return ;
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}
@@ -195,15 +203,15 @@ void frequencyin_reference_tc_enable(bool enable) {
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}
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#ifdef SAM_D5X_E5X
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- void frequencyin_samd51_start_dpll () {
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+ static bool frequencyin_samd51_start_dpll (void ) {
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if (clock_get_enabled (0 , GCLK_SOURCE_DPLL1 )) {
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- return ;
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+ return true ;
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}
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uint8_t free_gclk = find_free_gclk (1 );
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if (free_gclk == 0xff ) {
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dpll_gclk = 0xff ;
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- return ;
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+ return false ;
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}
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GCLK -> PCHCTRL [OSCCTRL_GCLK_ID_FDPLL1 ].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN (free_gclk );
@@ -228,23 +236,25 @@ void frequencyin_samd51_start_dpll() {
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while (!(OSCCTRL -> Dpll [1 ].DPLLSTATUS .bit .LOCK || OSCCTRL -> Dpll [1 ].DPLLSTATUS .bit .CLKRDY )) {}
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enable_clock_generator (free_gclk , GCLK_GENCTRL_SRC_DPLL1_Val , 1 );
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dpll_gclk = free_gclk ;
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+ return true;
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}
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- void frequencyin_samd51_stop_dpll () {
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+ static void frequencyin_samd51_stop_dpll (void ) {
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if (!clock_get_enabled (0 , GCLK_SOURCE_DPLL1 )) {
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return ;
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}
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- disable_clock_generator (dpll_gclk );
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+ if (dpll_gclk != 0xff ) {
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+ disable_clock_generator (dpll_gclk );
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+ dpll_gclk = 0xff ;
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+ }
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GCLK -> PCHCTRL [OSCCTRL_GCLK_ID_FDPLL1 ].reg = 0 ;
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OSCCTRL -> Dpll [1 ].DPLLCTRLA .reg = 0 ;
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OSCCTRL -> Dpll [1 ].DPLLRATIO .reg = 0 ;
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OSCCTRL -> Dpll [1 ].DPLLCTRLB .reg = 0 ;
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-
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while (OSCCTRL -> Dpll [1 ].DPLLSYNCBUSY .bit .ENABLE ) {
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}
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- dpll_gclk = 0xff ;
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}
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#endif
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@@ -421,7 +431,7 @@ void common_hal_frequencyio_frequencyin_deinit(frequencyio_frequencyin_obj_t* se
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self -> pin = NO_PIN ;
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bool check_active = false;
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- for (uint8_t i = 0 ; i <= ( TC_INST_NUM - 1 ) ; i ++ ) {
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+ for (uint8_t i = 0 ; i < TC_INST_NUM ; i ++ ) {
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if (active_frequencyins [i ] != NULL ) {
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check_active = true;
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}
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