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Merge pull request #7889 from stonehippo/wio-terminal-pins-note
Added notes re the RTL8720D pins
2 parents e667c23 + 031667e commit adfb9b1

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  • ports/atmel-samd/boards/seeeduino_wio_terminal

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ports/atmel-samd/boards/seeeduino_wio_terminal/pins.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -95,13 +95,13 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
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{ MP_OBJ_NEW_QSTR(MP_QSTR_I2S_SDIN), MP_ROM_PTR(&pin_PA22) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_I2S_BCLK), MP_ROM_PTR(&pin_PB16) },
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98-
// RTL8720D
98+
// RTL8720D - follows the schematic, but see comments
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{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_PWR), MP_ROM_PTR(&pin_PA18) }, // CHIP_PU
100-
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_RXD), MP_ROM_PTR(&pin_PC22) },
101-
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_TXD), MP_ROM_PTR(&pin_PC23) },
102-
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_MOSI), MP_ROM_PTR(&pin_PB24) },
100+
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_RXD), MP_ROM_PTR(&pin_PC22) }, // *NOT* THE MAIN RX FOR THE RTL CHIP (may be a log UART?)
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{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_TXD), MP_ROM_PTR(&pin_PC23) }, // *NOT* THE MAIN TX FOR THE RTL CHIP (may be a log UART?)
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{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_MOSI), MP_ROM_PTR(&pin_PB24) }, // used as the UART TX for the RTL chip
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{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_CLK), MP_ROM_PTR(&pin_PB25) },
104-
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_MISO), MP_ROM_PTR(&pin_PC24) },
104+
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_MISO), MP_ROM_PTR(&pin_PC24) }, // used as the UART RX for the RTL chip
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{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_CS), MP_ROM_PTR(&pin_PC25) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_READY), MP_ROM_PTR(&pin_PC20) }, // IRQ0
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{ MP_OBJ_NEW_QSTR(MP_QSTR_RTL_DIR), MP_ROM_PTR(&pin_PA19) }, // SYNC

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