@@ -44,10 +44,6 @@ STATIC bool never_reset_tim[TIM_BANK_ARRAY_LEN];
44
44
STATIC void tim_clock_enable (uint16_t mask );
45
45
STATIC void tim_clock_disable (uint16_t mask );
46
46
47
- //--------
48
- //STATICS
49
- //--------
50
-
51
47
// Get the frequency (in Hz) of the source clock for the given timer.
52
48
// On STM32F405/407/415/417 there are 2 cases for how the clock freq is set.
53
49
// If the APB prescaler is 1, then the timer clock is equal to its respective
@@ -91,10 +87,6 @@ STATIC void timer_get_optimal_divisors(uint32_t*period, uint32_t*prescaler,
91
87
}
92
88
}
93
89
94
- //--------
95
- //COMMON HAL
96
- //--------
97
-
98
90
void pwmout_reset (void ) {
99
91
uint16_t never_reset_mask = 0x00 ;
100
92
for (int i = 0 ;i < TIM_BANK_ARRAY_LEN ;i ++ ) {
@@ -328,80 +320,128 @@ bool common_hal_pulseio_pwmout_get_variable_frequency(pulseio_pwmout_obj_t* self
328
320
329
321
STATIC void tim_clock_enable (uint16_t mask ) {
330
322
#ifdef TIM1
331
- if (mask & 1 <<0 ) __HAL_RCC_TIM1_CLK_ENABLE ();
323
+ if (mask & 1 <<0 ) {
324
+ __HAL_RCC_TIM1_CLK_ENABLE ();
325
+ }
332
326
#endif
333
327
#ifdef TIM2
334
- if (mask & 1 <<1 ) __HAL_RCC_TIM2_CLK_ENABLE ();
328
+ if (mask & 1 <<1 ) {
329
+ __HAL_RCC_TIM2_CLK_ENABLE ();
330
+ }
335
331
#endif
336
332
#ifdef TIM3
337
- if (mask & 1 <<2 ) __HAL_RCC_TIM3_CLK_ENABLE ();
333
+ if (mask & 1 <<2 ) {
334
+ __HAL_RCC_TIM3_CLK_ENABLE ();
335
+ }
338
336
#endif
339
337
#ifdef TIM4
340
- if (mask & 1 <<3 ) __HAL_RCC_TIM4_CLK_ENABLE ();
338
+ if (mask & 1 <<3 ) {
339
+ __HAL_RCC_TIM4_CLK_ENABLE ();
340
+ }
341
341
#endif
342
342
#ifdef TIM5
343
- if (mask & 1 <<4 ) __HAL_RCC_TIM5_CLK_ENABLE ();
343
+ if (mask & 1 <<4 ) {
344
+ __HAL_RCC_TIM5_CLK_ENABLE ();
345
+ }
344
346
#endif
345
347
//6 and 7 are reserved ADC timers
346
348
#ifdef TIM8
347
- if (mask & 1 <<7 ) __HAL_RCC_TIM8_CLK_ENABLE ();
349
+ if (mask & 1 <<7 ) {
350
+ __HAL_RCC_TIM8_CLK_ENABLE ();
351
+ }
348
352
#endif
349
353
#ifdef TIM9
350
- if (mask & 1 <<8 ) __HAL_RCC_TIM9_CLK_ENABLE ();
354
+ if (mask & 1 <<8 ) {
355
+ __HAL_RCC_TIM9_CLK_ENABLE ();
356
+ }
351
357
#endif
352
358
#ifdef TIM10
353
- if (mask & 1 <<9 ) __HAL_RCC_TIM10_CLK_ENABLE ();
359
+ if (mask & 1 <<9 ) {
360
+ __HAL_RCC_TIM10_CLK_ENABLE ();
361
+ }
354
362
#endif
355
363
#ifdef TIM11
356
- if (mask & 1 <<10 ) __HAL_RCC_TIM11_CLK_ENABLE ();
364
+ if (mask & 1 <<10 ) {
365
+ __HAL_RCC_TIM11_CLK_ENABLE ();
366
+ }
357
367
#endif
358
368
#ifdef TIM12
359
- if (mask & 1 <<11 ) __HAL_RCC_TIM12_CLK_ENABLE ();
369
+ if (mask & 1 <<11 ) {
370
+ __HAL_RCC_TIM12_CLK_ENABLE ();
371
+ }
360
372
#endif
361
373
#ifdef TIM13
362
- if (mask & 1 <<12 ) __HAL_RCC_TIM13_CLK_ENABLE ();
374
+ if (mask & 1 <<12 ) {
375
+ __HAL_RCC_TIM13_CLK_ENABLE ();
376
+ }
363
377
#endif
364
378
#ifdef TIM14
365
- if (mask & 1 <<13 ) __HAL_RCC_TIM14_CLK_ENABLE ();
379
+ if (mask & 1 <<13 ) {
380
+ __HAL_RCC_TIM14_CLK_ENABLE ();
381
+ }
366
382
#endif
367
383
}
368
384
369
385
STATIC void tim_clock_disable (uint16_t mask ) {
370
386
#ifdef TIM1
371
- if (mask & 1 <<0 ) __HAL_RCC_TIM1_CLK_DISABLE ();
387
+ if (mask & 1 <<0 ) {
388
+ __HAL_RCC_TIM1_CLK_DISABLE ();
389
+ }
372
390
#endif
373
391
#ifdef TIM2
374
- if (mask & 1 <<1 ) __HAL_RCC_TIM2_CLK_DISABLE ();
392
+ if (mask & 1 <<1 ) {
393
+ __HAL_RCC_TIM2_CLK_DISABLE ();
394
+ }
375
395
#endif
376
396
#ifdef TIM3
377
- if (mask & 1 <<2 ) __HAL_RCC_TIM3_CLK_DISABLE ();
397
+ if (mask & 1 <<2 ) {
398
+ __HAL_RCC_TIM3_CLK_DISABLE ();
399
+ }
378
400
#endif
379
401
#ifdef TIM4
380
- if (mask & 1 <<3 ) __HAL_RCC_TIM4_CLK_DISABLE ();
402
+ if (mask & 1 <<3 ) {
403
+ __HAL_RCC_TIM4_CLK_DISABLE ();
404
+ }
381
405
#endif
382
406
#ifdef TIM5
383
- if (mask & 1 <<4 ) __HAL_RCC_TIM5_CLK_DISABLE ();
407
+ if (mask & 1 <<4 ) {
408
+ __HAL_RCC_TIM5_CLK_DISABLE ();
409
+ }
384
410
#endif
385
411
//6 and 7 are reserved ADC timers
386
412
#ifdef TIM8
387
- if (mask & 1 <<7 ) __HAL_RCC_TIM8_CLK_DISABLE ();
413
+ if (mask & 1 <<7 ) {
414
+ __HAL_RCC_TIM8_CLK_DISABLE ();
415
+ }
388
416
#endif
389
417
#ifdef TIM9
390
- if (mask & 1 <<8 ) __HAL_RCC_TIM9_CLK_DISABLE ();
418
+ if (mask & 1 <<8 ) {
419
+ __HAL_RCC_TIM9_CLK_DISABLE ();
420
+ }
391
421
#endif
392
422
#ifdef TIM10
393
- if (mask & 1 <<9 ) __HAL_RCC_TIM10_CLK_DISABLE ();
423
+ if (mask & 1 <<9 ) {
424
+ __HAL_RCC_TIM10_CLK_DISABLE ();
425
+ }
394
426
#endif
395
427
#ifdef TIM11
396
- if (mask & 1 <<10 ) __HAL_RCC_TIM11_CLK_DISABLE ();
428
+ if (mask & 1 <<10 ) {
429
+ __HAL_RCC_TIM11_CLK_DISABLE ();
430
+ }
397
431
#endif
398
432
#ifdef TIM12
399
- if (mask & 1 <<11 ) __HAL_RCC_TIM12_CLK_DISABLE ();
433
+ if (mask & 1 <<11 ) {
434
+ __HAL_RCC_TIM12_CLK_DISABLE ();
435
+ }
400
436
#endif
401
437
#ifdef TIM13
402
- if (mask & 1 <<12 ) __HAL_RCC_TIM13_CLK_DISABLE ();
438
+ if (mask & 1 <<12 ) {
439
+ __HAL_RCC_TIM13_CLK_DISABLE ();
440
+ }
403
441
#endif
404
442
#ifdef TIM14
405
- if (mask & 1 <<13 ) __HAL_RCC_TIM14_CLK_DISABLE ();
443
+ if (mask & 1 <<13 ) {
444
+ __HAL_RCC_TIM14_CLK_DISABLE ();
445
+ }
406
446
#endif
407
447
}
0 commit comments