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dhalbertdhalbert
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Merge pull request #6945 from flom84/main
Add circuitpython support for STM Nucleo-F446RE development board.
2 parents f8d2ff0 + 96a83ec commit b8c8e85

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‎ports/stm/boards/STM32F446_fs.ld‎

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/*
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GNU linker script for STM32F446 with filesystem
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*/
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/* Specify the memory areas */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */
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FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
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FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 48K /* sectors 1,2,3 are 16K */
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FLASH_FIRMWARE (rx) : ORIGIN = 0x08010000, LENGTH = 448K /* sector 4 is 64K, sectors 5,6,7 are 128K */
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
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}
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/* produce a link error if there is not this amount of RAM for these sections */
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_minimum_stack_size = 24K;
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_minimum_heap_size = 16K;
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/* Define tho top end of the stack. The stack is full descending so begins just
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above last byte of RAM. Note that EABI requires the stack to be 8-byte
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aligned for a call. */
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_estack = ORIGIN(RAM) + LENGTH(RAM);
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/* RAM extents for the garbage collector */
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_ram_start = ORIGIN(RAM);
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_ram_end = ORIGIN(RAM) + LENGTH(RAM);

‎ports/stm/boards/nucleo_f446re/board.c‎

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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 flom84
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "supervisor/board.h"
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// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here.

‎ports/stm/boards/nucleo_f446re/mpconfigboard.h‎

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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 flom84
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// Micropython setup
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#define MICROPY_HW_BOARD_NAME "NUCLEO F446RE"
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#define MICROPY_HW_MCU_NAME "STM32F446xx"
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#define FLASH_SIZE (0x80000u) // 512K
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#define FLASH_PAGE_SIZE (0x4000u) // 16K
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#define HSE_VALUE ((uint32_t)8000000u)
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#define BOARD_HSE_SOURCE (RCC_HSE_ON)
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// The schematic has a 32k crystal that isn't fitted. Uncommented the line below if you add it.
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// #define BOARD_HAS_LOW_SPEED_CRYSTAL (1)
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// #define LSE_VALUE ((uint32_t)32000U)
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#define BOARD_HAS_LOW_SPEED_CRYSTAL (0)
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// USART3 + USB FTDI
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// #define CIRCUITPY_CONSOLE_UART_TX (&pin_PC10)
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// #define CIRCUITPY_CONSOLE_UART_RX (&pin_PC11)
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// USART2 + ST link
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// #define CIRCUITPY_CONSOLE_UART_TX (&pin_PA02)
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// #define CIRCUITPY_CONSOLE_UART_RX (&pin_PA03)
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// Status LEDs
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#define MICROPY_HW_LED_STATUS (&pin_PA05)
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#define MICROPY_FATFS_EXFAT 0
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#define BOARD_NO_VBUS_SENSE (1)

‎ports/stm/boards/nucleo_f446re/mpconfigboard.mk‎

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USB_VID = 0x0483
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USB_PID = 0x572A
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USB_PRODUCT = "NUCLEO-F446RE - CPy"
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USB_MANUFACTURER = "STMicroelectronics"
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INTERNAL_FLASH_FILESYSTEM = 1
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MCU_SERIES = F4
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MCU_VARIANT = STM32F446xx
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MCU_PACKAGE = LQFP64
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LD_COMMON = boards/common_default.ld
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LD_FILE = boards/STM32F446_fs.ld
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# Too big for the flash
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CIRCUITPY_AUDIOCORE = 0
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CIRCUITPY_AUDIOPWMIO = 0
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CIRCUITPY_BITMAPTOOLS = 0
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CIRCUITPY_BLEIO_HCI = 0
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CIRCUITPY_VECTORIO = 0
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CIRCUITPY_TOUCHIO = 0
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CIRCUITPY_RAINBOWIO = 0
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CIRCUITPY_USB_HID = 0
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CIRCUITPY_USB_MIDI = 0
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CIRCUITPY_JSON = 0
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# Requires neopixel_write or SPI (dotstar)
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CIRCUITPY_PIXELBUF = 0
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# No requirements, but takes extra flash
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CIRCUITPY_ULAB = 0
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CIRCUITPY_GAMEPADSHIFT = 0
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CIRCUITPY_BITBANGIO = 0
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CIRCUITPY_NEOPIXEL_WRITE = 0
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CIRCUITPY_SDCARDIO = 0
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CIRCUITPY_DISPLAYIO = 0
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CIRCUITPY_KEYPAD = 0

‎ports/stm/boards/nucleo_f446re/pins.c‎

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#include "shared-bindings/board/__init__.h"
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STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
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{MP_ROM_QSTR(MP_QSTR_ID), MP_ROM_PTR(&board_module_id_obj)},
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{MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA03)},
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{MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA02)},
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{MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA10)},
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{MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PB03)},
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{MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PB05)},
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{MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PB04)},
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{MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PB10)},
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{MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA08)},
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{MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA09)},
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{MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PC07)},
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{MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PB06)},
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{MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07)},
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{MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06)},
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{MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05)},
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{MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09)},
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{MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08)},
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{MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00)},
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{MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01)},
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{MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA04)},
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{MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PB00)},
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{MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC01)},
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{MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PC00)},
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{MP_ROM_QSTR(MP_QSTR_PA0), MP_ROM_PTR(&pin_PA00)},
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{MP_ROM_QSTR(MP_QSTR_PA1), MP_ROM_PTR(&pin_PA01)},
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{MP_ROM_QSTR(MP_QSTR_PA2), MP_ROM_PTR(&pin_PA02)},
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{MP_ROM_QSTR(MP_QSTR_PA3), MP_ROM_PTR(&pin_PA03)},
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{MP_ROM_QSTR(MP_QSTR_PA4), MP_ROM_PTR(&pin_PA04)},
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{MP_ROM_QSTR(MP_QSTR_PA5), MP_ROM_PTR(&pin_PA05)},
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{MP_ROM_QSTR(MP_QSTR_PA6), MP_ROM_PTR(&pin_PA06)},
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{MP_ROM_QSTR(MP_QSTR_PA7), MP_ROM_PTR(&pin_PA07)},
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{MP_ROM_QSTR(MP_QSTR_PA8), MP_ROM_PTR(&pin_PA08)},
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{MP_ROM_QSTR(MP_QSTR_PA9), MP_ROM_PTR(&pin_PA09)},
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{MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10)},
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{MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11)},
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{MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12)},
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{MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15)},
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{MP_ROM_QSTR(MP_QSTR_PB0), MP_ROM_PTR(&pin_PB00)},
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{MP_ROM_QSTR(MP_QSTR_PB1), MP_ROM_PTR(&pin_PB01)},
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{MP_ROM_QSTR(MP_QSTR_PB2), MP_ROM_PTR(&pin_PB02)},
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{MP_ROM_QSTR(MP_QSTR_PB3), MP_ROM_PTR(&pin_PB03)},
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{MP_ROM_QSTR(MP_QSTR_PB4), MP_ROM_PTR(&pin_PB04)},
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{MP_ROM_QSTR(MP_QSTR_PB5), MP_ROM_PTR(&pin_PB05)},
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{MP_ROM_QSTR(MP_QSTR_PB6), MP_ROM_PTR(&pin_PB06)},
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{MP_ROM_QSTR(MP_QSTR_PB7), MP_ROM_PTR(&pin_PB07)},
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{MP_ROM_QSTR(MP_QSTR_PB8), MP_ROM_PTR(&pin_PB08)},
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{MP_ROM_QSTR(MP_QSTR_PB9), MP_ROM_PTR(&pin_PB09)},
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{MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10)},
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{MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12)},
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{MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13)},
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{MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14)},
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{MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15)},
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{MP_ROM_QSTR(MP_QSTR_PC0), MP_ROM_PTR(&pin_PC00)},
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{MP_ROM_QSTR(MP_QSTR_PC1), MP_ROM_PTR(&pin_PC01)},
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{MP_ROM_QSTR(MP_QSTR_PC2), MP_ROM_PTR(&pin_PC02)},
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{MP_ROM_QSTR(MP_QSTR_PC3), MP_ROM_PTR(&pin_PC03)},
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{MP_ROM_QSTR(MP_QSTR_PC4), MP_ROM_PTR(&pin_PC04)},
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{MP_ROM_QSTR(MP_QSTR_PC5), MP_ROM_PTR(&pin_PC05)},
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{MP_ROM_QSTR(MP_QSTR_PC6), MP_ROM_PTR(&pin_PC06)},
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{MP_ROM_QSTR(MP_QSTR_PC7), MP_ROM_PTR(&pin_PC07)},
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{MP_ROM_QSTR(MP_QSTR_PC8), MP_ROM_PTR(&pin_PC08)},
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{MP_ROM_QSTR(MP_QSTR_PC9), MP_ROM_PTR(&pin_PC09)},
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{MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10)},
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{MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11)},
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{MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12)},
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{MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13)},
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{MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14)},
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{MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15)},
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{MP_ROM_QSTR(MP_QSTR_PD2), MP_ROM_PTR(&pin_PD02)},
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{MP_ROM_QSTR(MP_QSTR_PH0), MP_ROM_PTR(&pin_PH00)},
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{MP_ROM_QSTR(MP_QSTR_PH1), MP_ROM_PTR(&pin_PH01)},
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{MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PA05)},
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{MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13)},
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};
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MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);

‎ports/stm/peripherals/periph.h‎

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#include "stm32f4/stm32f407xx/periph.h"
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#endif
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#ifdef STM32F446xx
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#define HAS_DAC 0
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#define HAS_TRNG 0
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#define HAS_BASIC_TIM 0
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#include "stm32f4/stm32f446xx/periph.h"
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#endif
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// F7 Series
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#ifdef STM32F746xx

‎ports/stm/peripherals/pins.h‎

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#ifdef STM32F407xx
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#include "stm32f4/stm32f407xx/pins.h"
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#endif
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#ifdef STM32F446xx
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#include "stm32f4/stm32f446xx/pins.h"
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#endif
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// F7 Series
102105
#ifdef STM32F746xx

‎ports/stm/peripherals/stm32f4/clocks.c‎

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#ifdef STM32F407xx
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#include "stm32f4/stm32f407xx/clocks.h"
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#endif
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#ifdef STM32F446xx
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#include "stm32f4/stm32f446xx/clocks.h"
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#endif
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5154
void stm32_peripherals_clocks_init(void) {
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
54-
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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5659
// Set voltage scaling in accordance with system clock speed
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__HAL_RCC_PWR_CLK_ENABLE();

‎ports/stm/peripherals/stm32f4/stm32f446xx/clocks.h‎

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/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 flom84
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
9+
* of this software and associated documentation files (the "Software"), to deal
10+
* in the Software without restriction, including without limitation the rights
11+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12+
* copies of the Software, and to permit persons to whom the Software is
13+
* furnished to do so, subject to the following conditions:
14+
*
15+
* The above copyright notice and this permission notice shall be included in
16+
* all copies or substantial portions of the Software.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24+
* THE SOFTWARE.
25+
*/
26+
27+
#include "stm32f4xx_hal.h"
28+
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// Chip: STM32F446xC/xV
30+
// Line Type: Access Line
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// Speed: 168MHz (max 180MHz)
32+
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// Defaults:
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#ifndef CPY_CLK_VSCALE
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#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1)
36+
#endif
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#ifndef CPY_CLK_PLLM
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#define CPY_CLK_PLLM (8)
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#endif
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#ifndef CPY_CLK_PLLN
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#define CPY_CLK_PLLN (336)
42+
#endif
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#ifndef CPY_CLK_PLLP
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#define CPY_CLK_PLLP (RCC_PLLP_DIV2)
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#endif
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#ifndef CPY_CLK_PLLQ
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#define CPY_CLK_PLLQ (7)
48+
#endif
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#ifndef CPY_CLK_AHBDIV
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#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1)
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#endif
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#ifndef CPY_CLK_APB1DIV
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#define CPY_CLK_APB1DIV (RCC_HCLK_DIV4)
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#endif
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#ifndef CPY_CLK_APB2DIV
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#define CPY_CLK_APB2DIV (RCC_HCLK_DIV2)
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#endif
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#ifndef CPY_CLK_FLASH_LATENCY
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#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_5)
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#endif
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#ifndef CPY_CLK_USB_USES_AUDIOPLL
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#define CPY_CLK_USB_USES_AUDIOPLL (0)
63+
#endif
64+
#ifndef BOARD_HSE_SOURCE
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#define BOARD_HSE_SOURCE (RCC_HSE_ON)
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#endif

‎ports/stm/peripherals/stm32f4/stm32f446xx/gpio.c‎

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/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 flom84
7+
*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
9+
* of this software and associated documentation files (the "Software"), to deal
10+
* in the Software without restriction, including without limitation the rights
11+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12+
* copies of the Software, and to permit persons to whom the Software is
13+
* furnished to do so, subject to the following conditions:
14+
*
15+
* The above copyright notice and this permission notice shall be included in
16+
* all copies or substantial portions of the Software.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24+
* THE SOFTWARE.
25+
*/
26+
27+
#include "peripherals/gpio.h"
28+
#include "stm32f4xx_hal.h"
29+
#include "common-hal/microcontroller/Pin.h"
30+
31+
void stm32_peripherals_gpio_init(void) {
32+
// * GPIO Ports Clock Enable */
33+
__HAL_RCC_GPIOC_CLK_ENABLE();
34+
__HAL_RCC_GPIOH_CLK_ENABLE();
35+
__HAL_RCC_GPIOA_CLK_ENABLE();
36+
__HAL_RCC_GPIOB_CLK_ENABLE();
37+
38+
// Never reset pins
39+
never_reset_pin_number(2, 13); // PC13 anti tamp
40+
never_reset_pin_number(2, 14); // PC14 OSC32_IN
41+
never_reset_pin_number(2, 15); // PC15 OSC32_OUT
42+
never_reset_pin_number(0, 13); // PA13 SWDIO
43+
never_reset_pin_number(0, 14); // PA14 SWCLK
44+
}
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46+
void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
47+
}

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